This driver works both with native_posix and native_sim.
native_sim will eventually not set NATIVE_SIM_NATIVE_POSIX_COMPAT
(i.e. not pretend to be native_posix) so let's correct the
dependencies.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
GRTC needs to use direct clock source path instead of system clock path
to support ELV mode for nRF54L targets.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Currently function `z_nrf_grtc_wakeup_prepare()` should be available
only for the GRTC manager (`CONFIG_NRF_GRTC_START_SYSCOUNTER` is active).
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Add checks to return value of esp_intr_alloc to avoid drivers init
returning 0 when interrupt allocation fails.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
The current driver implements the global defined "systick" interrupt
callback "sys_clock_isr" as a standard C function with an argument.
However, ARM's direct interrupt handlers do not have any arguments;
they must be declared as "void handler(void)".
Additionally, the direct handler should include some missing special
header/footer.
Fixes: #75693
Signed-off-by: Andrey VOLKOV <andrey.volkov@munic.io>
Replace useless "TICKLESS" define by
IS_ENABLED(CONFIG_TICKLESS_KERNEL) one, and replace error-prone
'cycle_t' pseudotype defs by real typedefs.
Signed-off-by: Andrey VOLKOV <andrey.volkov@munic.io>
LPTIM is not available in STOP3 mode, so RTC needs to be used instead.
This code usese similar approach as STM32WBAx for suspend to ram.
The STOP3 is disabled by default in device tree.
Signed-off-by: Adam Berlinger <adam.berlinger@st.com>
Fix timing in suspend-to-ram when using STM32WBA.
Switch to use RTC timer should be done only when idle is set
and LPTIM clocks should be switched off
Signed-off-by: Adam Berlinger <adam.berlinger@st.com>
Changes to bring support for esp32c6 SoC.
- clock control
- gpio
- pinctrl
- serial
- timer
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
When both MCUBoot and application run, systimer is initialized twice.
As a consequence, application freezes as systimer new initialization
conflicts with previous.
This PR adds the systimer clock disable function, that shall be called
before mcuboot jump to application, making sure it will
work as expected.
Fixes#74189
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The reason is that this driver needs to call the function
'irq_connect_dynamic()' which is implemented with DYNAMIC_INTERRUPTS.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
TI Dual-Mode timer is used as the arch timer for systick on J721E R5
cores. Add DM Timer for systick timer support.
Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
Signed-off-by: Andrew Davis <afd@ti.com>
The original driver has two defects: 1. When setting the next timeout
value the original implementation simply sets a delta value equal to
ticks * CYC_PER_TICK. This operation is reckless and may incorrectly
"reset" the fractional tick, causing clock skew. 2. The original
implementation doesn't handle the counter overflow situation. When the
counter overflows from 0xffffffff to 0x0, the uptimer counter becomes
incorrect. We have fixed above issue by rewriting most of the functions in
this driver and verified it by running all tests under
tests/kernel/timer folder.
Signed-off-by: Zhengwei Wang <zwang@ambiq.com>
Fix error due to compatible string changing in DT and
forgetting to update this driver with the change.
Also make the counter symbol hidden.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
These devices have a somewhat odd hybrid design, with a free-running
64 bit up counter but no comparator. Instead interrupts are triggered
by (one of an array of) 32 bit down counters with reset (a-la SysTick,
but without the 24 bit precision issues). The combination actually
results in a fairly simple driver as we can skip the comparator
rounding math.
Signed-off-by: Andy Ross <andyross@google.com>
This driver is impossible to make time-accurate using single-shot
mode. Time accuracy may be obtained only by using periodic mode, meaning
it is not tickless capable either. Let's simplify the code by only
supporting periodic mode and strip out the TSC stuff. Any hardware with
TSC capability should now use the apic-tsc driver instead.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This adds support for the local APIC in one-shot mode as the timeout
event source for those cases where the CPU supports invariant TSC but
no TSC deadline capability. It is presented as another timer choice.
Existing Kconfig symbols were preserved to minimize board config
disturbance.
This hybrid approach was implemented kind of backward in the apic_timer
driver but it is far cleaner to carry this here.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Let's replicate a common code pattern for this to be abstracted more
easily in the future. In addition to duplicating the correctness fixes
implemented in the ARM and RISC-V drivers, this eliminates a couple large
runtime divisions.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The `z_nrf_grtc_timer_get_ticks()` function converts system ticks
to GRTC ticks. It gets the current system tick to calculate an
absolute GRTC value. The same does the test function to provide
an argument to be converted. If the system tick occurs between those
`sys_clock_tick_get()` calls the `z_nrf_grtc_timer_get_ticks()` will
take into account the newer tick while the test estimate bases on
the old tick value. Due to that the maximum result error is 1 system
tick minus 1 GRTC tick which equals (`CYC_PER_TICK` - 1) for GRTC
ticks.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
This commit aligns the GRTC driver to changes introduced in
hal_nordic. Some of the features regarding GRTC sleep/wakeup
functionality has been modified and moved out to the nrfx
driver's code.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Clock must be restored as soon as the SoC leaves standby.
Keep the logic inside the SoC instead of delegate it to the pm
subsystem.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The RTC subsystem in espressif's SOCs, among other tasks
is responsible for clock selection for CPU and for low
power domain clocks such as RTC_SLOW and RTC_FAST.
This commit allows for proper clock source and rate
selection for CPU, using the espressif,riscv and
espressif,xtensa-lx6/7 bindings.
It also enables clock selection for RTC_FAST and RTC_SLOW,
that impacts some peripherals, such as rtc_timer.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
When function sys_clock_set_timout() is called with small value
(i.e. 1) calculated time to be programmed to TIMER2 reload
register may be such that is expires before code set's it
up. In that case timer interrupt will be scheduled in far
future.
With this change, code checks after it sets reload value if
requested time already passed and if so TIMER2 interrupt
is marked as pending to avoid races.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
d599e2b670 removed early return from sys_clock_timeout_handler if
current counter value is less than cc_val. It seems that this return is
needed as after the removal some stress tests which were using system
timers heavily started to hang.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
We have already code using toolchain provided __get_cpuid(), clean up
apic_tsc and make it consistent with the rest of the code.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Misc fixes for the grtc timer driver:
* In non tickless mode:
* The tick time would drift a bit with each interrupt
* If something would cause a very significant delay
in handling the tick interrupt the number of announcements
would be incorrect
* Fortickless mode: The calculation of the next tick time
in sys_clock_set_timeout() was incorrectly done,
resulting in two spurious, too early, wakes of the kernel
before each correct wake. This caused tests/kernel/context/
to fail.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The code currently clamps timeout length so not to overflow the computed
cycle difference variable or the sys_clock_announce() argument's range.
But this completely fails to take into account the case where two
successive timeouts with enough time between them will still overflow the
cycle difference and/or the tick count.
Fix this by clamping the actual number of cycles to wait for based on
the previous report occurrence rather than clamping the timeout ticks.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
In commit 6068255512 ("drivers/timer/arm_arch_timer: Fix cycles
overflow with GDB stub") an extra TO_CYCLE_DIFF() macro was introduced
to bypass the cycle_diff_t type cast in some cases.
The actual fix consists in defining that type properly in the first
place. That's the very reason why such type was abstracted.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
There are two issues being fixed here:
1) The code currently clamps timeout length so not to overflow the
computed cycle difference variable or the sys_clock_announce()
argument's range. But this completely fails to take into account
the case where two successive timeouts with enough time between them
will still overflow the cycle difference and/or the tick count.
2) If a timeout with K_TICKS_FOREVER is provided then the comparator is
set with UINT64_MAX which is bogus. Not only this value doesn't make
much sense in the context of a running cycle counter, but it also
opens the possibility for the same cycle diff and/or ticks overflow
as above.
Fix both of those by clamping the actual number of cycles to wait for
based on the previous report occurrence rather than clamping the timeout
ticks.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
add support for retrieve clock frequency (HW clock cycle per sec) of
system timer at runtime by reading cpu clock via cpuid
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
This enabled extended sleep for Renesas SmartBond(tm).
Extended sleep is low power mode where ARM core is powered off and can
be woken up by PDC. This is default sleep mode when CONFIG_PM is
enabled.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
This adds timer driver for Renesas SmartBond(tm) family.
It uses TIMER2 block which is in PD_TIM power domain so it can work even
if ARM core is disabled, thus can work as a sleep timer.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
