smartbond_timer: Fix convertion of watchdog value to LP clock ticks
Fix convertion of watchdog value to LP clock ticks Signed-off-by: Ioannis Damigos <ioannis.damigos.uj@renesas.com>
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1 changed files with 31 additions and 3 deletions
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@ -5,6 +5,8 @@
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*/
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#include <zephyr/device.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/smartbond_clock_control.h>
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#include <zephyr/drivers/timer/system_timer.h>
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#include <zephyr/sys_clock.h>
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#include <zephyr/spinlock.h>
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@ -17,6 +19,10 @@
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#define TICK_TO_CYC(tick) k_ticks_to_cyc_ceil32(tick)
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#define CYC_TO_TICK(cyc) k_cyc_to_ticks_ceil32(cyc)
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#define MAX_TICKS (((COUNTER_SPAN / 2) - CYC_PER_TICK) / (CYC_PER_TICK))
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#define SMARTBOND_CLOCK_CONTROLLER DEVICE_DT_GET(DT_NODELABEL(osc))
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/* Margin values are based on DA1469x characterization data */
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#define RC32K_FREQ_POSITIVE_MARGIN_DUE_TO_VOLTAGE (675)
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#define RC32K_FREQ_MARGIN_DUE_TO_TEMPERATURE (450)
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static uint32_t last_timer_val_reg;
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static uint32_t timer_val_31_24;
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@ -25,6 +31,19 @@ static uint32_t last_isr_val;
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static uint32_t last_isr_val_rounded;
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static uint32_t announced_ticks;
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static uint32_t get_rc32k_max_frequency(void)
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{
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/* According to DA1469x datasheet */
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uint32_t r32k_frequency = 37000;
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clock_control_get_rate(SMARTBOND_CLOCK_CONTROLLER,
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(clock_control_subsys_t)SMARTBOND_CLK_RC32K, &r32k_frequency);
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r32k_frequency += RC32K_FREQ_POSITIVE_MARGIN_DUE_TO_VOLTAGE +
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RC32K_FREQ_MARGIN_DUE_TO_TEMPERATURE;
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return r32k_frequency;
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}
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static void set_reload(uint32_t val)
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{
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TIMER2->TIMER2_RELOAD_REG = val & TIMER2_TIMER2_RELOAD_REG_TIM_RELOAD_Msk;
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@ -88,11 +107,20 @@ void sys_clock_set_timeout(int32_t ticks, bool idle)
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uint32_t watchdog_expire_ticks;
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if (CRG_TOP->CLK_RCX_REG & CRG_TOP_CLK_RCX_REG_RCX_ENABLE_Msk) {
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watchdog_expire_ticks = SYS_WDOG->WATCHDOG_REG * 21 *
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CONFIG_SYS_CLOCK_TICKS_PER_SEC / 1000;
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/*
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* When LP clock is RCX, the watchdog is clocked by RCX clock
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* divided by 320.
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*/
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watchdog_expire_ticks = SYS_WDOG->WATCHDOG_REG * 320;
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} else {
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/*
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* When LP clock is not RCX, the watchdog is clocked by RC32K
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* divided by 320. In this case watchdog value to LP clock
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* ticks must be calculated according to XTAL32K frequency and
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* RC32K maximum frequency.
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*/
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watchdog_expire_ticks = SYS_WDOG->WATCHDOG_REG *
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CONFIG_SYS_CLOCK_TICKS_PER_SEC / 100;
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CONFIG_SYS_CLOCK_TICKS_PER_SEC / (get_rc32k_max_frequency() / 320);
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}
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if (watchdog_expire_ticks - 2 < ticks) {
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ticks = watchdog_expire_ticks - 2;
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