arm_arch_timer: fix maximum allowed cycles between reports
The code currently clamps timeout length so not to overflow the computed cycle difference variable or the sys_clock_announce() argument's range. But this completely fails to take into account the case where two successive timeouts with enough time between them will still overflow the cycle difference and/or the tick count. Fix this by clamping the actual number of cycles to wait for based on the previous report occurrence rather than clamping the timeout ticks. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
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1 changed files with 50 additions and 25 deletions
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@ -27,6 +27,40 @@ static uint32_t cyc_per_tick;
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/* the unsigned long cast limits divisors to native CPU register width */
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#define cycle_diff_t unsigned long
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#endif
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#define CYCLE_DIFF_MAX (~(cycle_diff_t)0)
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/*
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* We have two constraints on the maximum number of cycles we can wait for.
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*
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* 1) sys_clock_announce() accepts at most INT32_MAX ticks.
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*
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* 2) The number of cycles between two reports must fit in a cycle_diff_t
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* variable before converting it to ticks.
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*
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* Then:
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*
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* 3) Pick the smallest between (1) and (2).
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*
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* 4) Take into account some room for the unavoidable IRQ servicing latency.
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* Let's use 3/4 of the max range.
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*
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* Finally let's add the LSB value to the result so to clear out a bunch of
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* consecutive set bits coming from the original max values to produce a
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* nicer literal for assembly generation.
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*/
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#define CYCLES_MAX_1 ((uint64_t)INT32_MAX * (uint64_t)CYC_PER_TICK)
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#define CYCLES_MAX_2 ((uint64_t)CYCLE_DIFF_MAX)
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#define CYCLES_MAX_3 MIN(CYCLES_MAX_1, CYCLES_MAX_2)
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#define CYCLES_MAX_4 (CYCLES_MAX_3 / 2 + CYCLES_MAX_3 / 4)
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#define CYCLES_MAX_5 (CYCLES_MAX_4 + LSB_GET(CYCLES_MAX_4))
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#ifdef CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
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/* precompute CYCLES_MAX at driver init to avoid runtime double divisions */
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static uint64_t cycles_max;
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#define CYCLES_MAX cycles_max
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#else
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#define CYCLES_MAX CYCLES_MAX_5
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#endif
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static struct k_spinlock lock;
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static uint64_t last_cycle;
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@ -106,39 +140,29 @@ static void arm_arch_timer_compare_isr(const void *arg)
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void sys_clock_set_timeout(int32_t ticks, bool idle)
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{
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#if defined(CONFIG_TICKLESS_KERNEL)
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if (ticks == K_TICKS_FOREVER) {
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if (idle) {
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return;
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}
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ticks = INT32_MAX;
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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return;
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}
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/*
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* Clamp the max period length to a number of cycles that can fit
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* in half the range of a cycle_diff_t for native width divisions
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* to be usable elsewhere. Also clamp it to half the range of an
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* int32_t as this is the type used for elapsed tick announcements.
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* The half range gives us one bit of extra room to cope with the
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* unavoidable IRQ servicing latency (we never need as much but this
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* is simple). The compiler should optimize away the least restrictive
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* of those tests automatically.
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*/
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ticks = CLAMP(ticks, 0, (cycle_diff_t)-1 / 2 / CYC_PER_TICK);
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ticks = CLAMP(ticks, 0, INT32_MAX / 2);
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if (idle && ticks == K_TICKS_FOREVER) {
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return;
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}
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k_spinlock_key_t key = k_spin_lock(&lock);
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uint64_t next_cycle = (last_tick + last_elapsed + ticks) * CYC_PER_TICK;
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uint64_t next_cycle;
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if (ticks == K_TICKS_FOREVER) {
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next_cycle = last_cycle + CYCLES_MAX;
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} else {
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next_cycle = (last_tick + last_elapsed + ticks) * CYC_PER_TICK;
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if ((next_cycle - last_cycle) > CYCLES_MAX) {
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next_cycle = last_cycle + CYCLES_MAX;
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}
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}
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arm_arch_timer_set_compare(next_cycle);
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arm_arch_timer_set_irq_mask(false);
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k_spin_unlock(&lock, key);
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#else /* CONFIG_TICKLESS_KERNEL */
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ARG_UNUSED(ticks);
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ARG_UNUSED(idle);
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#endif
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}
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uint32_t sys_clock_elapsed(void)
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@ -210,6 +234,7 @@ static int sys_clock_driver_init(void)
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arm_arch_timer_init();
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#ifdef CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
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cyc_per_tick = sys_clock_hw_cycles_per_sec() / CONFIG_SYS_CLOCK_TICKS_PER_SEC;
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cycles_max = CYCLES_MAX_5;
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#endif
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arm_arch_timer_enable(true);
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last_tick = arm_arch_timer_count() / CYC_PER_TICK;
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