Commit graph

859 commits

Author SHA1 Message Date
Lucas Tamborrino
c435dea191 soc: xtensa: esp32s3: add support for SPIRAM
Add support for external PSRAM for esp32s3.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2023-07-26 14:42:20 +02:00
Iuliana Prodan
1295283a8a soc: xtensa: nxp: add resource_table section in linker script
Add resource_table section in linker script for nxp_adsp_imx8m
for inter-process communication.

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2023-07-26 14:33:36 +02:00
Marek Matej
6b57b3b786 soc: xtensa,riscv: esp32xx: refactor folder structure
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:

- changing the CONFIG_SOC_ESP32* to refer to
  the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
  the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
  provide a SOC model config
- introducing the 'common' folder to hide all
  commonly used configs and files.
- updating west.yml to reflect previous changes in hal

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-07-25 18:12:33 +02:00
Gerard Marull-Paretas
f603061938 soc: xtensa: intel_adsp: cavs: fix PM hooks guards
The PM hooks were guarded with CONFIG_PM_POLICY_CUSTOM, however, they
need to be guarded (if file is always compiled) with CONFIG_PM. In fact,
CONFIG_PM_POLICY_CUSTOM requires to implement a custom policy hook,
something this module did not provide.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-07-20 10:33:00 +00:00
Gerard Marull-Paretas
55f5a75c58 pm: remove unnecessary __weak from pm_state_set/pm_exit_post_ops
Remove unnecessary __weak attribute from power management functions.
These functions are now defined once, globally, and mandatory for
systems that support CONFIG_PM.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-07-20 10:33:00 +00:00
Gerard Marull-Paretas
3d2194f11e pm: introduce HAS_PM
Add a new Kconfig option that has to be selected by SoCs providing PM
hooks. This option will be now required to enable CONFIG_PM. Before this
change, CONFIG_PM could always be enabled, regardless of SoC providing
any kind of low-power support.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-07-20 10:33:00 +00:00
Daniel Leung
e55fb88bcb soc: intel_adsp/ace: update clock rate
The clock rates for ACE series of Intel Audio DSP have changed.
The values come from the SOF project in their board configs.

CONFIG_XTENSA_CCOUNT_HZ is also set so the arch timing test
can pass.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-07-17 16:27:08 -04:00
Marc Herbert
35e8e6fa03 soc/xtensa/nxp_adsp/CMakeLists.txt: use new WEST_SIGN_OPTS variable
Align `soc/nxp_adsp` with new `WEST_SIGN_OPTS` option added to
`soc/intel_adsp` by recent commit d98a7c2f8d ("soc: xtensa: cmake: add
new WEST_SIGN_OPTS variable").

This allows per-board rimage customization at the CMake level. Example
in `zephyr/boards/xtensa/nxp_adsp_NEWBOARD/board.cmake`:

  set(WEST_SIGN_OPTS -- -c rimage/config/special.toml)

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-07-13 14:19:26 +02:00
Daniel Leung
25c6553edd soc: intel_adsp/ace: use functions to do CPU power control
Instead of relying on direct memory access via structs to
control CPU power and status, using inline functions instead
to hide the details. This makes reading the common code a bit
cleaner.

The function names are generic and not architecture or
platform specific, in an attempt to ease future arch or
platform additions with code reuse. Or else we would need to
rename these.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-07-10 16:13:03 +02:00
Tomasz Leman
3764814831 intel_adsp: boot: d3: hp sram reinit
Adding HP SRAM initialization in D3 power state exit procedure.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2023-07-10 16:08:32 +02:00
Marek Matej
0038620b37 soc: xtensa: disable SPIRAM when MCUBOOT
Some boards has ESP_SPIRAM enabled by default, which is
causing issues when MCUboot is used as 2nd bootloader.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-07-10 15:10:14 +02:00
Iuliana Prodan
dc49a314fd west: sign.py: fix sign when CONFIG_KERNEL_BIN_NAME is used
This fixes the following build error:
```
zephyr/zephyr.elf', needed by 'zephyr/zephyr.ri', missing and no known
rule to make it
```
This appears when CONFIG_KERNEL_BIN_NAME is used.

Therefore, do not use zephyr.elf since some samples might be called
based on CONFIG_KERNEL_BIN_NAME.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2023-07-10 09:29:33 +02:00
Keith Packard
710422ec5e include/zephyr: Fix linker scripts to define _end after all static RAM data
The Zephyr linker scripts have inconsistent ordering of various chunks of
data which lands in RAM at runtime. This leads to the value of _end not
being consistently defined as the maximum address of static variables used
in the application.

Create a helper linker fragment, zephyr/linker/ram-end.ld, which can be
included after the last possible definition of RAM data, that consistently
sets _image_ram_end, _end and z_mapped_end.

Signed-off-by: Keith Packard <keithp@keithp.com>
2023-06-28 08:41:02 +00:00
Serhiy Katsyuba
431108d89e intel_adsp: ace: Restore IDC interrupt on D3 exit
After exiting D3 state if IMR context save is enabled, IDC interrupt
must be re-enabled again for all cores.

Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
2023-06-28 06:50:27 +00:00
Anas Nashif
7584c17374 intel_adsp: restructure dmic headers and move regs to soc
The ifdefs in in dmic headers is getting out of control and makes
maintainence very ddifficult, especially when having to maintain out of
tree SoCs sharing the same data and information.

Keep header clean and per SoC and share some common registers in one
place instead avoiding confusion and making it easier to read and
maintain.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-06-23 14:27:44 -04:00
Anas Nashif
c62e55973b intel_adsp: remove deprecated cache macros
SOC_DCACHE_FLUSH and SOC_DCACHE_INVALIDATE are not being used anywhere.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-06-23 11:14:08 -04:00
Andrey Borisovich
23b3cae1b1 inte_adsp: ipc: prevent ipc message send during Device power transition
When CONFIG_PM_DEVICE is enabled IPC Device may be during power transition
during a call to intel_adsp_ipc_send_message function.
Changed signatures of intel_adsp_ipc_send_message and its sync version
to return int and negative error codes on error.
On attempt to send IPC message during Device power transition
-ESHUTDOWN error code is returned, on busy state -EBUSY.
Updated all function references.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2023-06-22 06:14:57 -04:00
Andrey Borisovich
355f8cfe4f intel_adsp: ipc: device support D3 power state change
When option CONFIG_PM_DEVICE is enabled, IPC driver is capable
of entering D3 power state described as PM_DEVICE_ACTION_SUSPEND
(and leaving that state - powering back to PM_DEVICE_ACTION_ACTIVE).
New power control callbacks 'ipc_power_control_api' are introduced for
use during power state transisions. They allow Zephyr application
specific code to be executed.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2023-06-22 06:14:57 -04:00
Andrey Borisovich
1d58b1b83f intel_adsp: mem_window: reinitialize after idle exit
Exiting idle state requires to reinitialize all memory window
instances to flush the cached memory.
Added function that calls initialization of devices during runtime.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2023-06-22 06:14:57 -04:00
Andrey Borisovich
7595cafb02 intel_adsp: timer: implemented sys_clock_idle_exit function
Generic header for system clock allows to define a sys_clock_idle_exit
function for the clock implementation.
Implemented the function in the intel_adsp_timer to reinitialize
device driver after the idle exit state.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2023-06-22 06:14:57 -04:00
Lucas Tamborrino
e229898caf drivers: pinctrl: esp32xx: allow internal loopback
Provides a way to use pinctrl to allow internal loopback
on a peripheral pin for testing purposes.
This is done by using output-enable on a input pin and
input-enable on a output pin.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2023-06-22 08:13:36 +00:00
Lucas Tamborrino
ba3766a75f debug: coredump: xtensa: add esp32s2
Add coredump support for esp32s2.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2023-06-21 16:06:06 -04:00
Adrian Warecki
64b2246dbc soc: adsp: clk: Add multiple clock sources support for dai
Added a new function to check whether a clock source is supported by a
platform and to retrieve its frequency.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-06-20 14:19:13 -04:00
Adrian Warecki
1a4bc7580b adsp: Rename cpu clock related functions
The word cpu was added to the names of functions, structs, types
and definitions to disambiguate the names and make room in the namespace
for soc clock control functions.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-06-20 14:19:13 -04:00
Adrian Warecki
b9e5cf5110 adsp: ace: ace_dfpmccu structure field description
Added ace_dfpmccu structure field descriptions to make the code more
readable.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-06-20 14:19:13 -04:00
Jaska Uimonen
a8b28f13c1 soc: intel_adsp: cavs: add simple IMR functionality
Add simple mechanism to load the image from IMR memory. Basically we are
only setting a flag in power off for the next boot to jump to existing
image in IMR.

Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
2023-06-20 09:28:56 +01:00
Jaska Uimonen
339b00de11 soc: xtensa: intel_adsp: fix memory bank shutdown
Amount of memory banks should vary depending on platform, otherwise
power down sequence might result in ipc timeout as the memory used by
the ipc itself is shutdown.

Lift the needed defines from sram.c to adsp_memory.h and shorten the
names to avoid collision with sof code. No functional change to sram.c.

Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
2023-06-17 07:31:11 -04:00
Flavio Ceolin
5dfaf23f47 xtensa: intel_adsp: lnl: Fix dspcs struct
This is struct is used to access to contiguous registers for each core
and lnl has 5.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2023-06-17 07:30:21 -04:00
Gerard Marull-Paretas
c59b57c0be soc: esp32*: do not enable HAS_DYNAMIC_DEVICE_HANDLES
It doesn't make sense to select this option at SoC level. This feature
is meant for subsystems/modules that need device handles to be
modifiable at runtime.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-06-15 10:09:26 -04:00
Pierre-Louis Bossart
b871138fae soc/intel_adsp: fix typo in L1EXP definition
The field offset is incorrect, L1EXP is at bit 24 and L1ETP at bit 25.

Fixes: cc6e9c094a ("soc/intel_adsp: Low level HDA driver and tests")
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
2023-06-06 17:20:01 -04:00
Marc Herbert
d98a7c2f8d soc: xtensa: cmake: add new WEST_SIGN_OPTS variable
This allows per-board rimage customization.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-06-02 15:07:59 -04:00
Marek Matej
02d157b8db soc: esp32: Update soc startup and cache init
Updated the cache init functions
and clean-up the soc startup function.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-06-01 10:05:20 +02:00
Marek Matej
548e8b717d soc: esp32: Fix linker scripts
Updated the flash segment alignment on S3,
so that mapping corresponds with the linkage.
Fixed hard-coded flash size for ESP32.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-06-01 10:05:20 +02:00
Kai Vehmanen
aa5b66be5f intel_adsp: cavs25: configure access to ALH
For Intel cavs2.5, access from LPGPDMAC to Audio Link Hub
RX/TX registers needs to be explicitly enabled before use.

The logic follow hardware initialization done in
SOF project sof/src/platform/intel/cavs/platform.c

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2023-05-30 10:50:02 -04:00
Anas Nashif
8e3437461d soc: intel_adsp: remove obsolete headers for cAVS platforms
The SoCs/Boards using those headers were dropped, so remove those
remaining headers that were forgotten.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-05-26 09:06:12 -04:00
Flavio Ceolin
44415eb881 intel_adsp: Initialize threadptr register
Initialize threadptr with 0 during the boot before it possibly be used
since the architectural reset state is undefined.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2023-05-25 18:23:39 -04:00
Marek Matej
4796746b5e soc: esp32: MCUboot support
This make MCUboot build as Zephyr application.
Providing optinal 2nd stage bootloader to the
IDF bootloader, which is used by default.
This provides more flexibility when building
and loading multiple images and aims to
brings better DX to users by using the sysbuild.
MCUboot and applications has now separate
linker scripts.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-05-25 16:15:54 +02:00
Rander Wang
49c7aa56fa soc: intel_adsp: undefine NOP32
It should not be NOP16.

Signed-off-by: Rander Wang <rander.wang@intel.com>
2023-05-25 04:49:14 -04:00
Tomasz Leman
7d54586751 soc: intel_adsp: ipc: check for pending ack
This patch modifies intel_adsp_ipc_is_complete function so it don't
report that IPC is completed when we are still waiting for ACK from
HOST.

This change will allow to solve the problem that occurs during the power
state transitions. Occasionally, the Application decides to enter the
power gating state after sending an IPC message, before receiving an ACK
from the HOST. This results in broken IPC communication when coming back
to Idle state.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2023-05-23 22:07:08 -04:00
Laurentiu Mihalcea
58d1c6146c soc: xtensa: nxp_adsp: Enable cache management API for NXP SoCs
Thanks to PR [1] which introduces support for cache management
operations on xtensa architecture NXP SoCs can now use the
Zephyr native cache management API.

This commit enables some configurations that will allow us
to use the native Zephyr cache management API.

[1]: https://github.com/zephyrproject-rtos/zephyr/pull/50136

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2023-05-17 18:34:24 -04:00
Flavio Ceolin
706cfbbb76 intel_adsp: ace: Fix heap in the linker
The end of the heap should be the same as _heap_sentry. The current end
marker just covers the range of memory that is explicitly put in
.heap_memand not account until the end of L2_SRAM_BASE +
L2_SRAM_SIZE memory.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2023-05-16 20:56:20 -04:00
Peter Mitsis
2ebb2bb1ab soc: xtensa: Lower HW_STATE_CHECK_DELAY
The macro HW_STATE_CHECK_DELAY represents the number of usec to
busy-wait when waiting for a h/w register state change. This value
has been lowered by 75% to correct a couple of issues related
to Power Management (PM).

1. This resolves a kernel.timer.tickless test failure (see
tests/kernel/timer/timer_api) on the LNL simulator where the test
was taking too long to wake after sleeping for 50 ticks. This
was tracked down to the xtensa SOC power management code where
it was performing a busy wait of 256 usec, which was equivalent
to 2.56 ticks.

2. Furthermore, this delay of 256 usec contradicted the information
in the DTSI (see power-states for d0i3) which states that the
"exit-latency-us" is 100 usec. Reducing this value to 64 helps to
keep that in line.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2023-05-16 06:12:27 -04:00
Marc Herbert
5ae7bd84d3 soc: xtensa: nxp: invoke west sign at west build time
This aligns `soc/xtensa/nxp_adsp/` with commit
fad2da39aa ("intel_adsp: move `west sign` from `west flash` to earlier
`west build`")

The --if-tool-available option preserves backwards-compatibility:
nothing happens if rimage is not found.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-05-16 12:08:43 +02:00
Daniel Leung
9fc99928ca soc: intel_adsp/ace: update SOC_TOOLCHAIN_NAME
Update the SOC_TOOLCHAIN_NAME to intel_ace15_mtpm so that
we use the correct overlay in Xtensa HAL module. Note that
ace20_lnl will also be using this as well. That will change
once we have a proper toolchain for ace20_lnl.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-05-16 01:50:00 +09:00
Daniel Leung
49d0ad5520 soc: intel_adsp: update toolchain for cavs25
This updates the toolchain used for intel_adsp_cavs25 to
the proper toolchain.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-05-16 01:50:00 +09:00
Jaroslaw Stelter
9c0dd7e3be intel_adsp: ace20_lnl: Change LNL core count to 5
The ACE 2.0 LNL platform has 5 HIFI4 cores. Change number
of cores to enable 5th core on the platform.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
2023-05-15 08:00:11 -04:00
Flavio Ceolin
15a3f8c7e7 intel_adsp: ace: Fix __rodata_region_end marker on linker
Move __rodata_region_end to after the inclusion of common-rom.ld

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2023-05-12 18:20:54 -04:00
Guennadi Liakhovetski
986eb6aafd xtensa: remove ELF section address rewriting
(resubmitting after it has been reverted by 0f2a352cbd ('Revert
"xtensa: remove ELF section address rewriting"')

Now rimage can handle both cached and uncached addresses correctly,
ELF rewriting isn't needed any more.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2023-05-12 18:19:59 -04:00
Flavio Ceolin
665812f994 xtensa: intel_adsp: Lock vecbase after initial setup
Lock the vecbase register after the hw initialization.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2023-05-12 06:01:46 -04:00
Flavio Ceolin
05cd4b07f7 intel_adsp: linker: Rename text area variables
Use Zephyr's convention for text region start and end.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2023-05-10 08:06:30 -04:00