Commit slters z_impl_nrf_qspi_nor_xip_enable to not call
qspi_device_init in case when xip_enabled has the same value
as requested.
In case when qspi_device_init returns non-zero no further actions
are taken and xip_enabled will not be to set requested value.
Fixes#59535.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Now that all in-tree phys are declared under their mdio bus, drop the
`mdio` property and use DT_INST_BUS to find the bus.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
`k_thread_create` function has the 'adin' device passed as 1st
entry pointer. Therefore the device configuration is obtained directly
from the `dev` structure.
Adujst the code accodringly.
Fixes: 75dde83 ("drivers: ethernet: adin2111: add adin1110 support")
Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
`DEVICE_DT_INST_DEFINE` requires to pass pointer to the device's
private constant data so make it const.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
Since VWGPSM (Virtual Wire GPIO Target-to-Controller) registers are
introduced in npcx9 and later series, the CL moves the related DT nodes
from npcx-espi-vws-map.dtsi (Used for all npcx series) to the specific
dtsi files for npcx9 and npcx4 series.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This is a follow-up to commit fa609e5844.
This driver implements SPI slave operations only and cannot be used
without the corresponding Kconfig option enabled.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
To allow the ADC API unit test to skip tests for non-implemented
features, return -ENOTSUP.
Signed-off-by: Eric Holmberg <eric.holmberg@northriversystems.co.nz>
When we lock an hwspinlock, we must write the CPU identifier to
the hwspinlock register. If we want to unlock the locked hwspinlock,
we have to rewrite the same CPU identifier.
To define the CPU identifier, we use affinity 1 and affinity 2 fields
of the MPIDR register.
Signed-off-by: Aziz Idomar <aidomar@sequans.com>
The intention of hardware spinlock is to allow two processors,
that have no alternative mechanism for accomplish synchronization
and mutual exclusion operations, to share resources (such as
memory and/or any other element).
Here, we add the hwspinlock framework, that makes possible to use
those hwspinlock devices and stay platform-independent. Each
platform wishing to support hardware spinlock must describe a
driver using this framework.
Signed-off-by: Aziz Idomar <aidomar@sequans.com>
Add support for ADIN1110 10BASE-T1L Ethernet MAC-PHY.
The ADIN1110 is an ultra low power, single port, 10BASE-T1L
transceiver design for industrial Ethernet applications and is com-
pliant with the IEEE® 802.3cg-2019™ Ethernet standard for long
reach, 10 Mbps single pair Ethernet (SPE). Featuring an integrated
media access control (MAC) interface, the ADIN1110 enables direct
connectivity with a variety of host controllers via a 4-wire serial
peripheral interface (SPI). This SPI enables the use of lower power
processors without an integrated MAC, which provides for the
lowest overall system level power consumption. The SPI can be
configured to use the Open Alliance SPI protocol or a generic SPI
protocol.
Documentation:
https://www.analog.com/en/products/adin1110.html
Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
To be consistent with other xmc4xxx drivers.
A few other device tree changes:
- Rename clock signal option as it's handled by DX1.
- Remove clock-frequency option as it's already added in
i2c-controller.yaml, and interrupts is already defined as array
in base.yaml.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Currently the driver is not configured as controller during initialization.
Any use of I2C in controller mode without an explicit i2c_configure() will
not work.
In this commit the driver is automatically configured.
But, delay the configuraition until first use instead of during init
because otherwise tests/drivers/i2c/i2c_target_api hangs without any
errors on xmc47_relax_kit (when internal pulls are used). This issue
needs to be investigated.
There are a few other fixes/cleanups:
- Change the default master_frequency from XMC4_I2C_SPEED_STANDARD to
I2C_SPEED_STANDARD.
- Use devicetree clock frequency for target configuration instead of
I2C_SPEED_STANDARD.
- Rename master_frequency to bitrate as it's also used by the target
configuration now.
- Remove several uneeded casts.
- Forward backup config in get_config().
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
The simple executor was removed with the usage of the spsc queue but
some stray references remained. Remove those.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Remove redundant function during child node initialization.
Move log related header file near log related macro.
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Based on the standard based definitions given in previous commits, the
TX timestamp used for timed TX now refers to the start of PHR. As OT
continues to calculate timestamps based on a "start of SHR" definition,
the duration of the PHY specific SHR is added in the OT adaptation layer
to make up for this OT quirk.
Fixes: #59245
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Builds upon the newly introduced nrf_802154_phr_timestamp_get() function
to calculate RX timestamps according to the timestamp definitions
introduced in earlier commits and removes the prior workaround to
calculate the start-of-frame message timestamp point.
Fixes: #59245
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
OT does not have 64 bit timestamp support. This is a limitation of OT
and not of the IEEE 802.15.4 driver API. Therefore any workaround
related to such OT idiosyncracies should be encapsulated inside the OT
adapatation layer.
This change moves the OT-specific conversion of OT 32 bit timestamps to
Zephyr 64 bit timestamps into the OT adaptation layer.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Fixes#61401
The ADS1x1x driver has a bad habit of assuming i2c operations will
always suceed - this fixes the two worse cases in the code I could
identify (there may yet be more).
* During initial ADC setup, if either of the two I2C operations
(read or write) fails, raise the error immediately to the caller
rather than letting it fall through to the acquisition thread.
This ensures that we only ever attempt to give a result that was
definitely connected to our attempt to start the capture.
* If the acquisition thread encounters an I2C error, raise the error
but do not terminate the aquisition thread. This ensures the
application can attempt to fix the condition that caused the I2C
error and try again.
Signed-off-by: Chris Collins <kuroneko@sysadninjas.net>
Since the driver can now be also used on nRF91 Series, its name need to
be updated to not cause confusion.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Instead of directly configuring PPI channels, use the GPPI helper
provided by nrfx. This allows using the driver on nRF53 an nRF91
Series where DPPI is available instead of PPI.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
When possible, use separate GPIOTE tasks for setting the PWM output
high and low instead of using one task to toggle it. This is crucial
for DPPI where the same task cannot be used in more than one channel.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Otherwise a glitch can appear on the PWM output when the GPIOTE channel
is reconfigured (when GPIOTE releases the pin, GPIO takes control and
drives it to the last written state which may be different than that
used recently by GPIOTE).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Rework the devicetree definition for smsc91x to put the mdio and
ethernet device at the same level, and make the phy a child of the mdio
node.
This allows matching up the device initialization sequence with the
devicetree hierarchy.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Move few variable inside a case statement to avoid build warning for
unused variables in some specific configuration.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This driver implements an MDIO device. Enable the MDIO driver to avoid a
build error for:
orphan section `._device.static.3_CONFIG_MDIO_INIT_PRIORITY_'
Also set the proper compatible in mdio_shell so that the ethernet tests
build correctly.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Rename the STM32H7 FDCAN driver Kconfig symbol and implementation file to
match the naming used in the ST reference manuals.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename the STM32 FDCAN driver Kconfig symbol and implementation file to
match the naming used in the ST reference manuals.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename the STM32 bxCAN driver DTS compatible, Kconfig symbol, and
implementation file to match the naming used in the ST reference manuals.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Fold the contents of the private header for the STM32 bxCAN driver into the
implementation file.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The timing_max parameters defined in the stm32 bxcan driver don't match the
register description in the reference manuals.
- sjw does have only 2 bits representing 1 to 4 tq.
- phase_seg1 and phase_seg2 max is one tq higher.
I have checked the following reference manuals and all match:
- RM0090: STM32F405, F415, F407, F417, F427, F437 AND F429
- RM0008: STM32F101, F102, F103, F105, F107 advanced arm-based mcus
- RM0351, RM0394: all STM32L4
- RM0091: all STM32F0 with CAN support
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Following #60410, the NXP S32 external interrupt controller device
initializes after the core interrupt controller. Bump the NXP S32 intc
init level to initialize after the core intc and before the GPIO
device driver.
Fixes#61218
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Check the packet lenght in flash_write operation beforeSigned-off-by
copying it to an internal buffer.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
