drivers: pwm_nrf5_sw: Extend to work also with DPPI
Instead of directly configuring PPI channels, use the GPPI helper provided by nrfx. This allows using the driver on nRF53 an nRF91 Series where DPPI is available instead of PPI. Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
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2 changed files with 25 additions and 23 deletions
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@ -7,9 +7,9 @@ config PWM_NRF5_SW
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bool "Nordic Semiconductor nRF5x series S/W PWM"
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default y if !PWM_NRFX
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depends on DT_HAS_NORDIC_NRF_SW_PWM_ENABLED
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depends on DT_HAS_NORDIC_NRF_PPI_ENABLED
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select NRFX_GPIOTE
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select NRFX_PPI
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select NRFX_PPI if HAS_HW_NRF_PPI
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select NRFX_DPPI if HAS_HW_NRF_DPPIC
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help
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Enable driver to utilize PWM on the Nordic Semiconductor nRF5x series.
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@ -10,7 +10,7 @@
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#include <zephyr/drivers/pwm.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <nrfx_gpiote.h>
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#include <nrfx_ppi.h>
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#include <helpers/nrfx_gppi.h>
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#include <hal/nrf_gpio.h>
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#include <hal/nrf_rtc.h>
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#include <hal/nrf_timer.h>
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@ -41,11 +41,17 @@ BUILD_ASSERT(DT_INST_PROP(0, clock_prescaler) == 0,
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#error "Invalid number of PWM channels configured."
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#endif
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#if defined(PPI_FEATURE_FORKS_PRESENT) || defined(DPPI_PRESENT)
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#define PPI_FORK_AVAILABLE 1
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#else
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#define PPI_FORK_AVAILABLE 0
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#endif
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/* When RTC is used, one more PPI task endpoint is required for clearing
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* the counter, so when FORK feature is not available, one more PPI channel
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* needs to be used.
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*/
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#if USE_RTC && !defined(PPI_FEATURE_FORKS_PRESENT)
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#if USE_RTC && !PPI_FORK_AVAILABLE
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#define PPI_PER_CH 3
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#else
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#define PPI_PER_CH 2
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@ -165,7 +171,7 @@ static int pwm_nrf5_sw_set_cycles(const struct device *dev, uint32_t channel,
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/* clear PPI used */
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ppi_mask = BIT(ppi_chs[0]) | BIT(ppi_chs[1]) |
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(PPI_PER_CH > 2 ? BIT(ppi_chs[2]) : 0);
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nrf_ppi_channels_disable(NRF_PPI, ppi_mask);
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nrfx_gppi_channels_disable(ppi_mask);
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active_level = (flags & PWM_POLARITY_INVERTED) ? 0 : 1;
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@ -265,15 +271,13 @@ static int pwm_nrf5_sw_set_cycles(const struct device *dev, uint32_t channel,
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nrf_rtc_event_address_get(rtc,
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nrf_rtc_compare_event_get(0));
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#if defined(PPI_FEATURE_FORKS_PRESENT)
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nrf_ppi_fork_endpoint_setup(NRF_PPI,
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ppi_chs[1],
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clear_task_address);
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#if PPI_FORK_AVAILABLE
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nrfx_gppi_fork_endpoint_setup(ppi_chs[1],
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clear_task_addr);
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#else
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nrf_ppi_channel_endpoint_setup(NRF_PPI,
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ppi_chs[2],
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period_end_event_address,
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clear_task_address);
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nrfx_gppi_channel_endpoints_setup(ppi_chs[2],
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period_end_event_address,
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clear_task_address);
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#endif
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} else {
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pulse_end_event_address =
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@ -284,15 +288,13 @@ static int pwm_nrf5_sw_set_cycles(const struct device *dev, uint32_t channel,
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nrf_timer_compare_event_get(0));
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}
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nrf_ppi_channel_endpoint_setup(NRF_PPI,
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ppi_chs[0],
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pulse_end_event_address,
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pulse_end_task_address);
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nrf_ppi_channel_endpoint_setup(NRF_PPI,
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ppi_chs[1],
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period_end_event_address,
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period_end_task_address);
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nrf_ppi_channels_enable(NRF_PPI, ppi_mask);
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nrfx_gppi_channel_endpoints_setup(ppi_chs[0],
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pulse_end_event_address,
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pulse_end_task_address);
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nrfx_gppi_channel_endpoints_setup(ppi_chs[1],
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period_end_event_address,
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period_end_task_address);
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nrfx_gppi_channels_enable(ppi_mask);
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/* start timer, hence PWM */
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if (USE_RTC) {
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@ -347,7 +349,7 @@ static int pwm_nrf5_sw_init(const struct device *dev)
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/* Allocate resources. */
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for (uint32_t j = 0; j < PPI_PER_CH; j++) {
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err = nrfx_ppi_channel_alloc(&data->ppi_ch[i][j]);
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err = nrfx_gppi_channel_alloc(&data->ppi_ch[i][j]);
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if (err != NRFX_SUCCESS) {
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/* Do not free allocated resource. It is a fatal condition,
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* system requires reconfiguration.
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