Commit graph

764 commits

Author SHA1 Message Date
Gerard Marull-Paretas
7ccc1a41bc pm: use actions for device PM control
Instead of passing target states, use actions for device PM control.
Actions represent better the meaning of the callback argument.
Furthermore, they are more future proof as they can be suitable for
other PM actions that have no direct mapping to a state. If we compare
with Linux, we could have a multi-stage suspend/resume. Such scenario
would not have a good mapping when using target states.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-08-04 08:23:01 -04:00
Gerard Marull-Paretas
11eef4d8c8 pm: device: remove pointer usage for state
Since the state is no longer modified by the device PM callback, just
use the state value.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-08-04 08:23:01 -04:00
Gerard Marull-Paretas
9e7d545bb4 pm: device: remove ctrl_command callback argument
The ctrl_command is not used anymore, so remove it from the callback
signature.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-08-04 08:23:01 -04:00
Felipe Neves
3917203d52 driver: timer: esp32c3: added tickless support
For esp32c3 system timer clock driver enabling tickless mode
kernel

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-27 17:42:01 -04:00
Scott Worley
dd1a9559be Microchip: XEC RTOS timer: Add MEC172x support to driver
Update Microchip XEC RTOS timer driver adding MEC172x support and
using more device tree properities in the driver. We must also update
the XEC counter driver to use the new GIRQ DT properties.
Add new properties to RTOS timer and RTC timer YAML. These two timers
are linked due to option using a high speed timer for kernel busy wait.
Add Kconfig logic for XEC RTOS timer to MEC172x SoC.
Enable the Microchip XEC RTOS timer in the MEC172x evaluation board.
Add device tree nodes for most peripeherals.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2021-07-27 09:29:34 -04:00
Ruibin Chang
21f0f958fe ITE drivers/ite_it8xxx2_timer: re-write ite timer driver
Re-write ite timer driver.

Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
2021-07-24 21:26:49 -04:00
Guennadi Liakhovetski
45b70e1500 smp: limit the scope of some SMP-only functions
z_smp_init() is only available if CONFIG_SMP is defined,
smp_timer_init() also depends on two Kconfig parameters. Also make it
conditional in cavs_timer.c. Also clarify some SMP-related comments
there.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2021-07-23 16:06:54 -04:00
Daniel Leung
f7d82da541 timer: hpet: convert register access to functions
This converts register access from macro to functions.
This allows SoCs to override these functions if needed.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-07-20 13:35:14 +02:00
Daniel Leung
b9cc043434 timer: hpet: don't force TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
This allows the HPET timer to use kconfig to specify clock
frequency instead of relying on calculation at runtime.
When the frequency is known at build, this allow the toolchain
to optimize some calculations.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-07-20 13:35:14 +02:00
Daniel Leung
fc5f698551 timer: hpet: allow overriding MIN_DELAY
This renames MIN_DELAY to HPET_CMP_MIN_DELAY, and also allows it
to be overridden. The default delay is for HPET with relative
high frequency, and may not suitable for all HPET
implementations.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-07-20 13:35:14 +02:00
Daniel Leung
aadcd10a6e timer: hpet: extract Counter Clock Period into a macro
This extracts the hard-coded value into a macro which can be
overridden. This is in preparation for SoCs where the period
is not in femptoseconds.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-07-20 13:35:14 +02:00
Krzysztof Chruscinski
482fae74a8 drivers: timer: nrf_rtc_timer: Fix race condition
RTC interrupt was reading CC value and passing it to the handler.
However, higher priority interrupt could preempt RTC interrupt
and set new CC value. In that case CC value read in the RTC
interrupt context was not the one that triggered the interrupt.
Added fallback to COUNTER value if that case is detected.

Using COUNTER is not as precise as CC because it returns time
when event was handled and not when event occured but it is the
only option since CC value is overwritten.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2021-07-19 12:02:27 +02:00
Henrik Brix Andersen
21806b569f drivers: timer: add NXP LPTMR timer driver
Add NXP Kinetis Low Power Timer (LPTMR) OS timer driver shim. Since the
LPTMR does not support asynchronous changes to the timer period, only
non-tickless mode is supported.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-07-14 22:54:34 +03:00
Dino Li
7d5411d6e0 soc: it8xxx2: introduce SOC_IT8XXX2_PLL_FLASH_48M option
Enable SOC_IT8XXX2_PLL_FLASH_48M at default to reduce latency of
fetching code from flash.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-07-13 09:44:29 -04:00
Gerard Marull-Paretas
26ad8376bd pm: remove callback from control function
The callback is not used anymore, so just delete it from the pm_control
callback signature.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-07-13 09:36:45 -04:00
Felipe Neves
600f8c64e1 soc: riscv: esp32c3: use the new esp_rom prefix
For esp32c3 related ROM located functions instead
of esp32c3_rom.

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-07 20:58:50 -04:00
Felipe Neves
132ab922a8 drivers: timer: esp32c3: add esp32c3 systimer driver to CODEOWNERS
Also added maintainer to the entry

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-07 20:58:50 -04:00
Felipe Neves
5d736766ed soc: esp32c3: added initial soc support files for esp32c3
by adding the soc specific files such: soc initialization code,
linker scripts and support for esp32c3 devkitm

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-07 20:58:50 -04:00
Gerard Marull-Paretas
cc2f0e9c08 pm: use enum for device PM states
Move all PM_DEVICE_STATE_* definitions to an enum. The
PM_DEVICE_STATE_SET and PM_DEVICE_STATE_GET definitions have been kept
out of the enum since they do not represent any state. However, their
name has not been changed since they will be removed soon.

All drivers and tests have been adjusted accordingly.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-07-07 14:13:12 -04:00
Mahesh Mahadevan
c3567c6f33 tests: arch: arm_irq_vector_table: Update to run on MXRT685
Fix for Issue#35658.
Update the custom vector table to add the OS Event timer
interrupt which is used on RT685 as the kernel system timer

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2021-07-07 08:25:06 -04:00
Fabio Baltieri
9c82898127 drivers: stm32_lptim_timer: add support for STM32WL series
Add the lptim1 device node definition and enable the corresponding
exti interrupt in sys_clock_driver_init().

Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
2021-07-06 09:51:22 -04:00
Fabio Baltieri
3af832868c drivers: npcx: convert NPCX drivers clock client to DEVICE_DT_GET
Convert the various device_get_binding() calls used to get the device
clock node to use DEVICE_DT_GET. The latter is processed at link time,
so it should be a bit more efficient.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2021-06-27 23:02:39 -04:00
Fabio Baltieri
93554f050b drivers: timer: make lptim depend on the dt node
The stm32_lptim driver is hardcoded to use lptim1.

Make the Kconfig option depend on the presence of the node label in the
devicetree, so that there's one less list of supported SoC to keep track
of.

Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
2021-06-24 21:06:25 -04:00
Mulin Chao
6885afe432 driver: timer: npcx: add check for system kernel timer frequency
In npcx series, we use ITIM64 as system kernel timer. Its source clock
frequency must equal to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC. This CL
added check during initialization to prevent ambiguous condition.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2021-06-21 18:47:31 -04:00
Henrik Brix Andersen
35733ca385 drivers: timer: hide CONFIG_APIC_TIMER_IRQ_PRIORITY when not applicable
Make the APIC_TIMER_IRQ_PRIORITY Kconfig depend on APIC_TIMER ||
APIC_TSC_DEADLINE_TIMER to hide it in menuconfig when not applicable.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-06-10 18:15:01 -04:00
Andrzej Głąbek
457a28bf78 drivers: nrf_rtc_timer: Remove unnecessary locking
As per description of the sys_clock_elapsed() function, "the kernel
will call this with appropriate locking, the driver needs only provide
an instantaneous answer". Remove then the unnecessary locking from the
function, as it only adds an undesirable delay.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2021-05-24 23:53:18 -04:00
Maksim Masalski
0f5aab1182 drivers: change suffix ull to ULL
Replace suffix ull to ULL to increase code readability and prevent
unexpected behaviours, because the lowercase character l shall not be
used in a literal suffix

Found as a coding guideline violation (MISRA R7.3) by static
coding scanning tool.

Signed-off-by: Maksim Masalski <maksim.masalski@intel.com>
2021-05-21 18:13:01 -04:00
Simon Guinot
aa8e34302a drivers: systick: fix cycle count in sys_clock_set_timeout()
With this patch the sys_clock_set_timeout function counts the cycles
elapsed while computing the systick timer's new load (tickless mode).
This cycles are then added to the total cycle count instead of being
lost.

This patch mitigates uptime drifting in tickless mode (especially when
high frequency timers are registered).

Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
2021-05-20 08:44:55 -05:00
Gerard Marull-Paretas
7268b6fe01 drivers: timer: sys_clock: return -ENOSYS if not implemented
-ENOSYS should be returned if the operation is not implemented. This
issue was causing some PM tests to fail, as -ENOSYS was expected.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-05-13 07:16:02 -05:00
Daniel Leung
84a6a292c0 timer: hpet: mark functions as boot/pinned/isr
This marks the data and functions into appropriate
linker sections.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-05-10 16:00:43 -05:00
Flavio Ceolin
7eba310220 power: device: void *context -> uint32_t *state
The context parameter used across device power management is
actually the power state. Just use it and avoid a lot of
unnecessary casts.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2021-05-07 16:55:31 -04:00
Andy Ross
662b0bf765 drivers/timer: Add x86 APIC TSC_DEADLINE driver
Modern hardware all supports a TSC_DEADLINE mode for the APIC timer,
where the same GHz-scale 64 bit TSC used for performance monitoring
becomes the free-running counter used for cpu-local timer interrupts.
Being a free running counter that does not need to be reset, it will
not lose time in an interrupt.  Being 64 bit, it needs no rollover or
clamping logic in the driver when presented with a 32 bit tick count.
Being a proper comparator, it will correctly trigger interrupts for
times set "in the past" and thus needs no minimum/clamping logic.  The
counter is synchronized across the system architecturally (modulo one
burp where firmware likes to change the adjustment value) so usage is
SMP-safe by default.  Access to the 64 bit counter and comparator
value are single-instruction atomics even on 32 bit systems, so it
beats even the RISC-V machine timer in complexity (which was our
reigning champ for "simplest timer driver").

Really this is just ideal for Zephyr.  So rather than try to add
support for it to the existing APIC driver and increase complexity,
make this a new standalone driver instead.  All modern hardware has
what it needs.  The sole gotcha is that it's not easily emulatable
(qemu supports it only under kvm where they can freeload on the host
TSC) so it can be exercised only on hardware platforms right now.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-05-07 16:48:58 -04:00
Mahesh Mahadevan
84e7807190 drivers: timer: MXRT600 OS timer to wake platform from deep sleep
Enable OS Timer interrupt to wake up platform from deep sleep
mode

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2021-05-05 22:28:44 -05:00
Gerard Marull-Paretas
dbf46b3815 pm: rename device_pm_cb to pm_device_cb
Prefix all device PM functions/data structures with pm.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-05-05 18:35:49 -04:00
Jennifer Williams
ca75bbef3c tests: boot_time: remove all the code and instrumentation feeding into test
Remove the config BOOT_TIME_MEASUREMENT and corresponding #ifdef'd code
throughout (kernel/init.c, idle.c, core/common.S , reset.S, ... ) which
hold the extern hooks for z_timestamp_main and z_timestamp_idle in the
removed boot_time test suite.

Signed-off-by: Jennifer Williams <jennifer.m.williams@intel.com>
2021-05-05 10:41:15 -04:00
Guennadi Liakhovetski
a871f0be49 xtensa: cavs: fix irq_enable() argument
irq_enable() should be called with the composite IRQ code as its
argument, not just the Xtensa proper part of it.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2021-05-03 17:13:01 -04:00
Mulin Chao
440d9dc5d4 driver: itim: npcx: check ITEN bit to prevent return fake error.
During polling ITEN bit to make sure ITIM timer is enabled, we might
have the chance that npcx_itim_evt_enable() return fake error when
timeout expired but ITEN bit is set already if CONFIG_ZERO_LATENCY_IRQS
is enabled. (Since SVCall's interrupt priority is not the highest, the
other interrupts with IRQ_ZERO_LATENCY flag could preempt CPU resource
at this moment.)

In order to prevent return fake error code, this CL adjusts the check
conditions for ITEN bit and timeout.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2021-04-22 18:03:06 -04:00
Julien Massot
20fdb6cbfb drivers: timer: add R-Car cmt driver
Compare Match Timer is a 32 bit compare match timer
that can be found on various Renesas R-Car SoC.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-04-22 10:38:45 +02:00
Mahesh Mahadevan
243d6a2ed1 drivers: timer: Add MCUX OS timer
Add OS timer for the MCUX SoC's

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2021-04-21 20:40:24 -04:00
Francois Ramu
9d2aead97b drivers: timer: st_stm32: add lptimer management to stm32l5 series
This patch introduces the support of the LowPower Timer
for the STM32L5xx from STMicroelectronics.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2021-03-26 18:06:01 -04:00
Mulin Chao
291c61fd47 driver: timer: npcx: fix dead code flow for K_TICKS_FOREVER.
Fix dead code flow if ticks is K_TICKS_FOREVER.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2021-03-26 07:03:09 -04:00
Krzysztof Chruscinski
ab49673bc8 drivers: timer: nrf_rtc_timer: Change type of channel argument
There was an inconsistency in the API as z_nrf_rtc_timer_chan_alloc
returned int but other function were using uint32_t for channel
argument. Updated api to use int32_t everywhere.

Update nrf_802154 driver which was using this api to use int32_t.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2021-03-25 15:54:49 +01:00
Kumar Gala
95e4b3eb2c arch: arm: Add initial support for Cortex-M55 Core
Add initial support for the Cortex-M55 Core which is an implementation
of the Armv8.1-M mainline architecture and includes support for the
M‑profile Vector Extension (MVE).

The support is based on the Cortex-M33 support that already exists in
Zephyr.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-03-23 13:13:32 -05:00
Anas Nashif
5d6c219210 drivers: device: do not reuse tag name 'device'
Do not reuse tag name (misra rule 5.7).

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-03-22 19:48:14 -04:00
Anas Nashif
c076d94eec kernel: remove tickless idle
This feature predated the tickless kernel and has been in legacy mode
for a while. We now have no drivers or systems that do not support
tickless, so remove this option and cleanup the code to only use
tickless.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-03-19 11:22:17 -04:00
Anas Nashif
fe0872c0ab clocks: rename z_tick_get -> sys_clock_tick_get
Do not use z_ for internal APIs, z_ is for private APIs within one
subsystem only.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-03-19 11:22:17 -04:00
Anas Nashif
ffd01833d3 clock: z_clock_device_ctrl -> sys_clock_device_ctrl
Do not use z_ for internal APIs, z_ is for private APIs within one
subsystem only.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-03-19 11:22:17 -04:00
Anas Nashif
771cc9705c clock: z_clock_isr -> sys_clock_isr
Do not use z_ for internal APIs, z_ is for private APIs within one
subsystem only.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-03-19 11:22:17 -04:00
Anas Nashif
38eca45b32 drivers: arcv2_timer0: fix comment
Comment talking about z_timer_int_handler which does not exist, replace
with timer_int_handler.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-03-19 11:22:17 -04:00
Anas Nashif
12b53d121e clock: rename z_timer_cycle_get_32 -> sys_clock_cycle_get_32
This is another API that is being used in all timer drivers and is not
internal to the clock subsystem. Remove the leading z_ and make promote
it to a cross-subsystem API.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-03-19 11:22:17 -04:00