clock: rename z_timer_cycle_get_32 -> sys_clock_cycle_get_32
This is another API that is being used in all timer drivers and is not internal to the clock subsystem. Remove the leading z_ and make promote it to a cross-subsystem API. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
parent
11779e3faf
commit
12b53d121e
34 changed files with 49 additions and 49 deletions
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@ -247,7 +247,7 @@ uint32_t sys_clock_elapsed(void)
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return ret;
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}
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uint32_t z_timer_cycle_get_32(void)
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uint32_t sys_clock_cycle_get_32(void)
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{
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k_spinlock_key_t key = k_spin_lock(&lock);
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uint32_t ret = counter_sub(counter(), last_count) + last_count;
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@ -30,12 +30,12 @@ config APIC_TIMER_IRQ_PRIORITY
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This option specifies the IRQ priority used by the local APIC timer.
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config APIC_TIMER_TSC
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bool "Use invariant TSC for z_timer_cycle_get_32()"
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bool "Use invariant TSC for sys_clock_cycle_get_32()"
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help
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If your CPU supports invariant TSC, and you know the ratio of the
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TSC frequency to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC (the local APIC
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timer frequency), then enable this for a much faster and more
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accurate z_timer_cycle_get_32().
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accurate sys_clock_cycle_get_32().
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if APIC_TIMER_TSC
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@ -49,7 +49,7 @@ int sys_clock_driver_init(const struct device *device)
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return 0;
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}
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uint32_t z_timer_cycle_get_32(void)
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uint32_t sys_clock_cycle_get_32(void)
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{
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/* Per the Altera Embedded IP Peripherals guide, you cannot
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* use a timer instance for both the system clock and timestamps
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@ -16,7 +16,7 @@ BUILD_ASSERT(!IS_ENABLED(CONFIG_SMP), "APIC timer doesn't support SMP");
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* This driver enables the local APIC as the Zephyr system timer. It supports
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* both legacy ("tickful") mode as well as TICKLESS_KERNEL. The driver will
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* work with any APIC that has the ARAT "always running APIC timer" feature
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* (CPUID 0x06, EAX bit 2); for the more accurate z_timer_cycle_get_32(),
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* (CPUID 0x06, EAX bit 2); for the more accurate sys_clock_cycle_get_32(),
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* the invariant TSC feature (CPUID 0x80000007: EDX bit 8) is also required.
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* (Ultimately systems with invariant TSCs should use a TSC-based driver,
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* and the TSC-related parts should be stripped from this implementation.)
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@ -31,7 +31,7 @@ BUILD_ASSERT(!IS_ENABLED(CONFIG_SMP), "APIC timer doesn't support SMP");
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* by the local APIC timer block (before it gets to the timer divider).
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*
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* CONFIG_APIC_TIMER_TSC=y enables the more accurate TSC-based cycle counter
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* for z_timer_cycle_get_32(). This also requires the next options be set.
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* for sys_clock_cycle_get_32(). This also requires the next options be set.
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*
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* CONFIG_APIC_TIMER_TSC_N=<n>
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* CONFIG_APIC_TIMER_TSC_M=<m>
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@ -187,7 +187,7 @@ uint32_t sys_clock_elapsed(void)
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#ifdef CONFIG_APIC_TIMER_TSC
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uint32_t z_timer_cycle_get_32(void)
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uint32_t sys_clock_cycle_get_32(void)
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{
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uint64_t tsc = z_tsc_read();
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uint32_t cycles;
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@ -198,7 +198,7 @@ uint32_t z_timer_cycle_get_32(void)
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#else
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uint32_t z_timer_cycle_get_32(void)
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uint32_t sys_clock_cycle_get_32(void)
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{
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uint32_t ret;
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uint32_t ccr;
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@ -437,7 +437,7 @@ uint32_t sys_clock_elapsed(void)
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return cyc / CYC_PER_TICK;
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}
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uint32_t z_timer_cycle_get_32(void)
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uint32_t sys_clock_cycle_get_32(void)
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{
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#if SMP_TIMER_DRIVER
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return z_arc_connect_gfrc_read() - start_time;
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@ -109,7 +109,7 @@ uint32_t sys_clock_elapsed(void)
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return ret;
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}
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uint32_t z_timer_cycle_get_32(void)
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uint32_t sys_clock_cycle_get_32(void)
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{
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return (uint32_t)arm_arch_timer_count();
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}
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@ -176,7 +176,7 @@ uint32_t sys_clock_elapsed(void)
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return ret;
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}
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uint32_t z_timer_cycle_get_32(void)
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uint32_t sys_clock_cycle_get_32(void)
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{
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return count32();
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}
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@ -238,7 +238,7 @@ uint32_t sys_clock_elapsed(void)
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return ret;
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}
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uint32_t z_timer_cycle_get_32(void)
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uint32_t sys_clock_cycle_get_32(void)
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{
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return (AONRTCCurrent64BitValueGet() / RTC_COUNTS_PER_CYCLE)
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& 0xFFFFFFFF;
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@ -238,7 +238,7 @@ uint32_t sys_clock_elapsed(void)
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return cyc / CYC_PER_TICK;
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}
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uint32_t z_timer_cycle_get_32(void)
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uint32_t sys_clock_cycle_get_32(void)
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{
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k_spinlock_key_t key = k_spin_lock(&lock);
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uint32_t ret = elapsed() + cycle_count;
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@ -204,7 +204,7 @@ uint32_t sys_clock_elapsed(void)
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return ret;
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}
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uint32_t z_timer_cycle_get_32(void)
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uint32_t sys_clock_cycle_get_32(void)
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{
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return MAIN_COUNTER_REG;
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}
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@ -240,7 +240,7 @@ uint32_t sys_clock_elapsed(void)
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return ret;
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}
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uint32_t z_timer_cycle_get_32(void)
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uint32_t sys_clock_cycle_get_32(void)
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{
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return get_timer_combine_count(CTIMER_HW_TIMER_INDEX);
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}
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@ -86,7 +86,7 @@ uint32_t sys_clock_elapsed(void)
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return 0;
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}
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uint32_t z_timer_cycle_get_32(void)
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uint32_t sys_clock_cycle_get_32(void)
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{
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volatile struct gptimer_regs *regs = get_regs();
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volatile struct gptimer_timer_regs *tmr = ®s->timer[1];
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@ -39,7 +39,7 @@ static void litex_timer_irq_handler(const void *device)
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irq_unlock(key);
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}
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uint32_t z_timer_cycle_get_32(void)
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uint32_t sys_clock_cycle_get_32(void)
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{
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static struct k_spinlock lock;
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uint32_t timer_total;
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@ -286,7 +286,7 @@ uint32_t sys_clock_elapsed(void)
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* z_impl_k_busy_wait calls here. This code path uses the value as uint32_t.
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*
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*/
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uint32_t z_timer_cycle_get_32(void)
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uint32_t sys_clock_cycle_get_32(void)
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{
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uint32_t ret;
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uint32_t ccr;
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@ -27,7 +27,7 @@ static uint64_t last_tick_time;
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* Return the current HW cycle counter
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* (number of microseconds since boot in 32bits)
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*/
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uint32_t z_timer_cycle_get_32(void)
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uint32_t sys_clock_cycle_get_32(void)
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{
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return hwm_get_time();
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}
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@ -254,7 +254,7 @@ uint32_t sys_clock_elapsed(void)
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return (uint32_t)((current - cyc_sys_announced) / SYS_CYCLES_PER_TICK);
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}
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uint32_t z_timer_cycle_get_32(void)
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uint32_t sys_clock_cycle_get_32(void)
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{
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k_spinlock_key_t key = k_spin_lock(&lock);
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uint64_t current = npcx_itim_get_sys_cyc64();
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@ -393,7 +393,7 @@ uint32_t sys_clock_elapsed(void)
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return ret;
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}
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uint32_t z_timer_cycle_get_32(void)
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uint32_t sys_clock_cycle_get_32(void)
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{
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k_spinlock_key_t key = k_spin_lock(&lock);
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uint32_t ret = counter_sub(counter(), last_count) + last_count;
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@ -143,7 +143,7 @@ uint32_t sys_clock_elapsed(void)
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return ret;
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}
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uint32_t z_timer_cycle_get_32(void)
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uint32_t sys_clock_cycle_get_32(void)
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{
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return (uint32_t)mtime();
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}
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@ -131,7 +131,7 @@ int sys_clock_driver_init(const struct device *unused)
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return 0;
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}
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uint32_t z_timer_cycle_get_32(void)
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uint32_t sys_clock_cycle_get_32(void)
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{
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return cycle_count + SYSTEM_TIMER_INSTANCE->CNR;
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}
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#endif
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}
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uint32_t z_timer_cycle_get_32(void)
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uint32_t sys_clock_cycle_get_32(void)
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{
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/* Just return the absolute value of RTC cycle counter. */
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return rtc_count();
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@ -59,7 +59,7 @@ static void lptim_irq_handler(const struct device *unused)
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LL_LPTIM_ClearFLAG_ARRM(LPTIM1);
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/* increase the total nb of autoreload count
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* used in the z_timer_cycle_get_32() function.
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* used in the sys_clock_cycle_get_32() function.
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* Reading the CNT register gives a reliable value
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*/
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uint32_t autoreload = LL_LPTIM_GetAutoReload(LPTIM1) + 1;
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return (uint32_t)(ret);
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}
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uint32_t z_timer_cycle_get_32(void)
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uint32_t sys_clock_cycle_get_32(void)
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{
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/* just gives the accumulated count in a number of hw cycles */
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@ -189,7 +189,7 @@ uint32_t sys_clock_elapsed(void)
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#endif
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}
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uint32_t z_timer_cycle_get_32(void)
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uint32_t sys_clock_cycle_get_32(void)
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{
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/* Return the current counter value */
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return read_count();
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@ -110,7 +110,7 @@ uint32_t sys_clock_elapsed(void)
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return ret;
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}
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uint32_t z_timer_cycle_get_32(void)
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uint32_t sys_clock_cycle_get_32(void)
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{
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return ccount();
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}
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#ifndef _ASMLANGUAGE
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extern unsigned int z_arc_cpu_sleep_mode;
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extern uint32_t z_timer_cycle_get_32(void);
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extern uint32_t sys_clock_cycle_get_32(void);
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static inline uint32_t arch_k_cycle_get_32(void)
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{
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return z_timer_cycle_get_32();
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return sys_clock_cycle_get_32();
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}
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#endif
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@ -19,11 +19,11 @@ extern "C" {
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#endif
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#ifndef _ASMLANGUAGE
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extern uint32_t z_timer_cycle_get_32(void);
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extern uint32_t sys_clock_cycle_get_32(void);
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static inline uint32_t arch_k_cycle_get_32(void)
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{
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return z_timer_cycle_get_32();
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return sys_clock_cycle_get_32();
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}
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static ALWAYS_INLINE void arch_nop(void)
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@ -20,11 +20,11 @@ extern "C" {
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#endif
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#ifndef _ASMLANGUAGE
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extern uint32_t z_timer_cycle_get_32(void);
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extern uint32_t sys_clock_cycle_get_32(void);
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static inline uint32_t arch_k_cycle_get_32(void)
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{
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return z_timer_cycle_get_32();
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return sys_clock_cycle_get_32();
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}
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static ALWAYS_INLINE void arch_nop(void)
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@ -171,11 +171,11 @@ enum nios2_exception_cause {
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BIT(NIOS2_EXCEPTION_ECC_DATA_ERR))
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extern uint32_t z_timer_cycle_get_32(void);
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extern uint32_t sys_clock_cycle_get_32(void);
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static inline uint32_t arch_k_cycle_get_32(void)
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{
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return z_timer_cycle_get_32();
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return sys_clock_cycle_get_32();
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}
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static ALWAYS_INLINE void arch_nop(void)
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@ -44,11 +44,11 @@ struct __esf {
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typedef struct __esf z_arch_esf_t;
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extern uint32_t z_timer_cycle_get_32(void);
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extern uint32_t sys_clock_cycle_get_32(void);
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static inline uint32_t arch_k_cycle_get_32(void)
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{
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return z_timer_cycle_get_32();
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return sys_clock_cycle_get_32();
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}
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static ALWAYS_INLINE void arch_nop(void)
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__asm__ volatile("nop");
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}
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extern uint32_t z_timer_cycle_get_32(void);
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extern uint32_t sys_clock_cycle_get_32(void);
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static inline uint32_t arch_k_cycle_get_32(void)
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{
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return z_timer_cycle_get_32();
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return sys_clock_cycle_get_32();
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}
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#ifdef CONFIG_USERSPACE
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__asm__ volatile ("nop");
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}
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extern uint32_t z_timer_cycle_get_32(void);
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extern uint32_t sys_clock_cycle_get_32(void);
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static inline uint32_t arch_k_cycle_get_32(void)
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{
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return z_timer_cycle_get_32();
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return sys_clock_cycle_get_32();
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}
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extern void arch_irq_enable(unsigned int irq);
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extern void arch_irq_disable(unsigned int irq);
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extern uint32_t z_timer_cycle_get_32(void);
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extern uint32_t sys_clock_cycle_get_32(void);
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static inline uint32_t arch_k_cycle_get_32(void)
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{
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return z_timer_cycle_get_32();
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return sys_clock_cycle_get_32();
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}
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static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
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@ -56,11 +56,11 @@ extern void z_irq_spurious(const void *unused);
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#define XTENSA_ERR_NORET
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extern uint32_t z_timer_cycle_get_32(void);
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extern uint32_t sys_clock_cycle_get_32(void);
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static inline uint32_t arch_k_cycle_get_32(void)
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{
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return z_timer_cycle_get_32();
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return sys_clock_cycle_get_32();
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}
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static ALWAYS_INLINE void arch_nop(void)
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@ -718,9 +718,9 @@ enum usdhc_reset {
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static void usdhc_millsec_delay(unsigned int cycles_to_wait)
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{
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unsigned int start = z_timer_cycle_get_32();
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unsigned int start = sys_clock_cycle_get_32();
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while (z_timer_cycle_get_32() - start < (cycles_to_wait * 1000))
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while (sys_clock_cycle_get_32() - start < (cycles_to_wait * 1000))
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;
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}
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@ -29,7 +29,7 @@ static uint32_t sync(const struct device *cmos)
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}
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} while (last == this);
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return z_timer_cycle_get_32();
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return sys_clock_cycle_get_32();
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}
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void timer(void)
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