Commit graph

945 commits

Author SHA1 Message Date
Anas Nashif
400c7950b6 soc: intel_adsp: use abstracted arch APIs for cache ops
Use architecture APIs for cache operations with this soc family.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-04-26 07:31:22 -04:00
Jaroslaw Stelter
5ff2ca8415 intel_adsp: ace20_lnl: Add imr layout header to LNL
To enable IMR on LNL platform new header added to
support context save/restore must be added also to LNL.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
2023-04-20 13:14:34 -04:00
Daniel Leung
1e9d4602ab xtensa: add some structs for interrupt stack frames
This adds some structs for interrupt stack frames to make it
easier to access individual elements, and ultimately getting
rid of magic array element numbers in the code. Hopefully,
this would aid in debugging where you can view the whole
struct in debugger.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-04-20 04:45:52 -04:00
Marek Matej
ddab8786fd soc: kconfig: Add config for ESP32 family
Introduce config for all ESP32 chips which
may be using different architectures but
shares common peripherals and features.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-04-19 17:12:26 +02:00
Sylvio Alves
a6c8c6e546 soc: esp32s3: add Wi-Fi support
This adds Wi-Fi linker areas and also bring wi-Fi entry
into SoC device tree.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-04-19 17:11:58 +02:00
Jaska Uimonen
bdffde3695 soc: xtensa: intel_adsp: do power off only with custom pm policy
The power off sequence in cavs is meant to be used only by custom pm
policy handler thus guard it with proper ifdefs.

Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
2023-04-17 15:12:24 +02:00
Gerard Marull-Paretas
4863c5f05b sys/util: extend usage of DIV_ROUND_UP
Many areas of Zephyr divide and round up without using the DIV_ROUND_UP
macro. Make use of it, so that we make use of a tested system macro and
at the same time we make code more readable.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-04-12 16:42:29 +02:00
Gerard Marull-Paretas
a5fd0d184a init: remove the need for a dummy device pointer in SYS_INIT functions
The init infrastructure, found in `init.h`, is currently used by:

- `SYS_INIT`: to call functions before `main`
- `DEVICE_*`: to initialize devices

They are all sorted according to an initialization level + a priority.
`SYS_INIT` calls are really orthogonal to devices, however, the required
function signature requires a `const struct device *dev` as a first
argument. The only reason for that is because the same init machinery is
used by devices, so we have something like:

```c
struct init_entry {
	int (*init)(const struct device *dev);
	/* only set by DEVICE_*, otherwise NULL */
	const struct device *dev;
}
```

As a result, we end up with such weird/ugly pattern:

```c
static int my_init(const struct device *dev)
{
	/* always NULL! add ARG_UNUSED to avoid compiler warning */
	ARG_UNUSED(dev);
	...
}
```

This is really a result of poor internals isolation. This patch proposes
a to make init entries more flexible so that they can accept sytem
initialization calls like this:

```c
static int my_init(void)
{
	...
}
```

This is achieved using a union:

```c
union init_function {
	/* for SYS_INIT, used when init_entry.dev == NULL */
	int (*sys)(void);
	/* for DEVICE*, used when init_entry.dev != NULL */
	int (*dev)(const struct device *dev);
};

struct init_entry {
	/* stores init function (either for SYS_INIT or DEVICE*)
	union init_function init_fn;
	/* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows
	 * to know which union entry to call.
	 */
	const struct device *dev;
}
```

This solution **does not increase ROM usage**, and allows to offer clean
public APIs for both SYS_INIT and DEVICE*. Note that however, init
machinery keeps a coupling with devices.

**NOTE**: This is a breaking change! All `SYS_INIT` functions will need
to be converted to the new signature. See the script offered in the
following commit.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

init: convert SYS_INIT functions to the new signature

Conversion scripted using scripts/utils/migrate_sys_init.py.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

manifest: update projects for SYS_INIT changes

Update modules with updated SYS_INIT calls:

- hal_ti
- lvgl
- sof
- TraceRecorderSource

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

tests: devicetree: devices: adjust test

Adjust test according to the recently introduced SYS_INIT
infrastructure.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

tests: kernel: threads: adjust SYS_INIT call

Adjust to the new signature: int (*init_fn)(void);

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-04-12 14:28:07 +00:00
Gerard Marull-Paretas
0ebe14beb4 sys: util: migrate all files to DIV_ROUND_UP
ceiling_fraction is deprecated, use DIV_ROUND_UP.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-04-11 12:00:37 +02:00
Marc Herbert
fad2da39aa intel_adsp: move west sign from west flash to earlier west build
Invoking `west sign` in `west build` accelerates twister because `west
build` is run in parallel, see rationale in superseded and very
different (CMake-based) PR #52942.

To maximize backwards compatibility:
- `west sign` is optional in `west build`
- `west flash` will sign (again) if any rimage --option is passed

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-04-10 22:04:47 -04:00
Lucas Tamborrino
fcd9234111 soc: xtensa: esp32s3: Add FPU support
Enable FPU on esp32s3

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2023-04-08 12:34:25 +02:00
Anas Nashif
c71b71a662 soc: intel_adsp: simplify for only cavs25
Remove conditional code now that we only support CAVS25.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-04-06 18:51:56 +02:00
Anas Nashif
98e3699cf7 soc: remove intel_adsp_cavs20
Remove SoC definition for cavs20.
Support for this platform was removed in SOF.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-04-06 18:51:56 +02:00
Anas Nashif
683a9d90ab soc: remove intel_adsp_cavs18
Remove SoC for cavs18.
Support for this platform was removed in SOF.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-04-06 18:51:56 +02:00
Anas Nashif
d2cf740e68 soc: remove intel_adsp_cavs15
Remove SoC for cavs15.
Support for this platform was removed in SOF.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-04-06 18:51:56 +02:00
Jaroslaw Stelter
872907f42c intel_adsp: ace20_lnl: Enable PM on LNL platform
LNL uses MM_DRV_INTEL_ADSP_MTL_TLB to save / restore context.
This is exactly the same like on MTL. Enable PM for ACE 2.0 then.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
2023-04-03 15:17:21 +02:00
Jaroslaw Stelter
55caa18f3e intel_adsp: ace20_lnl: Update power and status registers
PWRCTL and PWRSTS registers for ACE 2.0 must be updated.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
2023-04-03 15:17:21 +02:00
Jaroslaw Stelter
feee9405b2 intel_adsp: ace20_lnl: dts: add L3 memory definitions macros
Add helper macros for l3 memory definitions from
the Device Tree

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
2023-04-03 15:17:21 +02:00
Flavio Ceolin
bfcef7da8c intel_adsp: ace20_lnl: Add L3 region definition
Add L3_MEM* definitions to adsp_memory.h

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2023-04-03 15:17:21 +02:00
Jaroslaw Stelter
e2881fe61a intel_adsp: ace20_lnl: add soc definitions for LNL platform.
LNL platform is ACE 2.0 series with changes in shim registers and HW
features. Initial definition replicates MTL as much as possible, however
it will vary after enabling LNL platform.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-04-03 15:17:21 +02:00
Adrian Warecki
ea405eb49e drivers: wdt: Add wdt_intel_adsp driver
Added a new watchdog driver which can handle a multiple wdt_dw instances
and can control the pause signal.

The mlt platform has three designware watchdogs, one for each core.
I decided to create a separate intel watchdog driver for the following
reasons:

1. All three devices share the same interrupt number. Each watchdog reports
an interrupt to the core to which it has been assigned. The same interrupt
number cannot be used by multiple devices in the device tree. So, it would
be assigned to only one device. The other dw watchdog devices would use
this assignment, even though it would not be described for them in the dt.
The interrupt handler function in dw watchdog checks the interrupt flag.
If the interrupt was connected to the first watchdog, and the second or
third watchdog signal an interrupt, the interrupt handler of the first
device would ignore it because it would not have set the interrupt flag.
The watchdog device don't knows anything about the existence of the others
devices.

2. The designware watchdog only supports a hardware pause signal. It cannot
be paused programmatically. On the mtl platform, there is a separate group
of control registers for all per-core watchdogs. There are GPIO-like
registers that allows control of a hardware pause signal for subordinate
watchdogs. This separate block is shared by all three watchdogs.

3. The base addresses of the subordinate watchdogs are read from the
aforementioned control registers. As a result, in the device tree we have
only one base address for the intel watchdog, which points to the pause
control registers and containing the base addresses of the subordinate
devices.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-03-29 09:45:49 -04:00
Marc Herbert
67f7b43136 soc: xtensa: remote-fw-service.py: fix usage without sudo
It's best practice to run as little code as possible as root (especially
when listening to network ports). When not itself running as root
already, remote-fw-service.py has always tried to invoke cavstool.py
with "sudo". Unfortunately this looks like it never worked; at least not
on Ubuntu 22 where this commit was tested. Moreover it did not fail
immediately but mysteriously timed out without any useful error message.

- The first, most obvious bug was that "sudo" does not propagate
SIGKILL (and a few other signals), see "man sudo". Compare:

```
$ sudo sleep 30 &
$ kill  $! # sudo propagates the TERM signal and sleep is terminated

$ sudo sleep 30 & sudoPID=$!
$ kill -KILL $sudoPID
$  ps  xfao pid,ppid,pgid,sid,comm | grep -C 5 -e PID -e sleep -e sudo
```

Fix this by invoking proc.terminate() first before proc.kill().
proc.terminate() is more "polite" with cavstool even when not using
sudo.

- Second issue: when signals are sent to sudo, strace shows that its
signal handler invokes `getpgid()` and then ignores signals coming from
its own process group. `man sudo` states: "sudo will not relay signals
that were sent by the command it is running...", which seems related.

`start_new_session=True` option moves sudo to a different PGID which
stops sudo from ignoring signals from its remote-fw-service.py parent.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-03-28 16:42:29 -04:00
Sylvio Alves
10a7baba0e soc: esp32s3: add bluetooth support
This only adds proper HEAP and HCI definition to enable
BLE support to ESP32-S3.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-03-27 13:19:38 +00:00
Jaska Uimonen
95168e6776 soc: intel_adsp: cavs: start using zephyr power management
Start using zephyr power management in cavs platform in a similar way
that is already done in ace. This commit only addresses the power off/on
sequence. Runtime power management is not implemented.

Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
2023-03-23 07:57:14 -04:00
Anas Nashif
0f2a352cbd Revert "xtensa: remove ELF section address rewriting"
This reverts commit 7a85983ebc.

This commit was merged prematurely and is causing issues on multiple
platforms.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-03-22 08:35:52 -04:00
Guennadi Liakhovetski
7a85983ebc xtensa: remove ELF section address rewriting
Now rimage can handle both cached and uncached addresses correctly,
ELF rewriting isn't needed any more.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2023-03-20 09:52:15 +01:00
Felipe
bd705e68b0 soc: xtensa: esp32: increase shared memory region
for esp32 and esp32_net because the default 2048
bytes are not sufficient for rpmsg usage.

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
2023-03-16 16:42:13 +01:00
Tomasz Leman
9854c915ff intel_adsp: cpu init refactor
Reusing existing code during CPU init at power gating exit.

Additional changes:
- replacing magic value for memctl and atomctl with more readable
  definitions,
- using dedicated macros in place of asm inlines.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2023-03-14 10:48:38 +01:00
Marc Herbert
a8c0123d3c intel_adsp: cmake: add_custom_command(.mod) to fix incremental build
Now building twice back to back does not build anything the second time
when CONFIG_CLEANUP_INTERMEDIATE_FILES (which obviously breaks
incremental builds) is also turned off.

Fixes commit 2906d1aa51 ("soc/intel_adsp: Build bootloader with Zephyr")

Properly implementing custom commands requires BOTH
`add_custom_command()` and an `add_custom_target()` wrapper with some
careful DEPENDS wizardry between them.

https://cmake.org/cmake/help/latest/command/add_custom_target.html
> Use the add_custom_command() command to generate a file with
> dependencies.

The documentation of add_custom_command() also similarly refers to
add_custom_target()

When this is not done properly, the build is cursed in various, very
time-consuming ways which are not officially documented but here
instead:
https://samthursfield.wordpress.com/2015/11/21/cmake-dependencies-between-targets-and-files-and-custom-commands

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-03-02 15:34:55 -05:00
Ning Shang
bd240d1fe5 ESP32-S2: fix - use correct storage label
This is a bugfix. It uses the right storage label `slot0_partition` for
esp32s2. Note that this is already the case for esp32 and esp32s3.

This should address
https://github.com/zephyrproject-rtos/zephyr/issues/55286.

Signed-off-by: Ning Shang <syncom.dev@gmail.com>
2023-03-02 09:59:10 +01:00
Sylvio Alves
bbd40b85c0 soc: esp32s3: add base source content
This brings esp32s3 linker, DTS and all
necessary files to allow the soc support.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-02-27 19:41:33 +01:00
Marc Herbert
eead89e7f2 soc: intel_adsp: cavstool.py: simplify asyncio.run() call
Fixes the following warning:

cavstool.py:706: DeprecationWarning: There is no current event loop
  asyncio.get_event_loop().run_until_complete(main())

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-02-26 09:18:24 -05:00
Daniel Leung
53316d5c8e toolchain: rename xcc-clang to xt-clang
This reflects the actual compiler executable name of the Xtensa
LLVM/Clang compiler.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-02-22 08:35:46 -05:00
Adrian Warecki
ddad6226c0 adsp: boot: power: Separate watchdog state from core power
The watchdog is controlled by ll-scheduler and should not be resumed when
a core is bringing up. Watchdog pause control code was removed.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-02-19 20:36:31 -05:00
Adrian Warecki
da4f20901f adsp: ipc: Emergency ipc message send
Added intel_adsp_ipc_send_message_emergency function that allows to send an
ipc message notifying about emergency event, such as watchdog timeout.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-02-19 20:36:31 -05:00
Adrian Warecki
625f226842 adsp: ace: Non-maskable interrupt handling
The non-maskable interrupt have no corresponding bit in INTERRUPT and
INTENABLE registers so its occurrence cannot be confirmed. Removed the code
that checked if the interrupt flag is set.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-02-19 20:36:31 -05:00
Aastha Grover
8f5bcb2e76 intel_adsp: ace: fix linker script for xcc-clang compiler
rodata section for xtensa overrides the .ctors section
containing the constructor info and the _ZEPHYR_CTOR_LIST_.
Removes the ctor related linker script lines from the rodata
section of the ace linker script to ensure that the .ctors is
properly generated and placed when using the xcc-clang compiler.

Fixes #54730

Signed-off-by: Aastha Grover <aastha.grover@intel.com>
2023-02-10 18:05:14 -06:00
Tomasz Leman
60a20471b5 intel_adsp: ace: enable interrupts for secondary core
Temporary re-enabling interrupts before going to waiti. Right now
secondary cores don't have proper context restore flow and after leaving
D3 state core will return here and stuck. This is temporary workaround.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2023-02-02 03:29:20 +09:00
Tomasz Leman
6045eed2f3 intel_adsp: ace: enable core power gating
Allowing the power domain of non-active cores to enter power gating
state.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2023-02-02 03:29:20 +09:00
Tomasz Leman
e1dbc2efef intel_adsp: ace: add core power off step
Adding additional core power-off before core is properly power-up after
power domains is wake up from power gaiting state.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2023-02-02 03:29:20 +09:00
Tomasz Leman
a99b073392 intel_adsp: ace: d3 exit update
This patch is moving common power configuration code outside of the
section only for the primary core. This should be enabled for all cores
and it was put there probably by mistake.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2023-02-02 03:29:20 +09:00
Tom Burdick
156c7cd217 intel_adsp: bbzero/bmemcpy with picolibc fix
When building with picolibc and gcc, the loops to do zeroing/copying
get replaced by gcc with calls to memset/memcpy. This fails this early in
the boot process and results in an illegal instruction exception.

Marking the variables being manipulated in the calls as volatile prevents
the compiler from optimizing the loops (replacing them with memset/memcpy).

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2023-02-02 03:09:35 +09:00
Jamie McCrae
ec7044437e treewide: Disable automatic argparse argument shortening
Disables allowing the python argparse library from automatically
shortening command line arguments, this prevents issues whereby
a new command is added and code that wrongly uses the shortened
command of an existing argument which is the same as the new
command being added will silently change script behaviour.

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2023-01-26 20:12:36 +09:00
Tom Burdick
a684714d5c soc: intel_adsp: Correct HDA parameter docstrings
The parameter doc string for hda was incorrect as the parameters
had been updated to take the IP base address, block size, and stream id
instead. Updates all doc string comments to account for the change.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2023-01-23 11:51:21 -08:00
Tom Burdick
b14296af38 dma: HDA ignore repeated start/stop requests
The DMA API contract specifies that start/stop may be called multiple
times. Prior to adding power management this was perfectly fine as it was.
In adding power management, there are additional side effects that can
cause issues. Instead check the state of the channel prior to start/stop
and do nothing if already in the desired state.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2023-01-23 11:51:21 -08:00
Guennadi Liakhovetski
8ff8834695 xtensa: sparse: fix address space mismatch
Fix remaining sparse address space mismatch warnings.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2023-01-20 15:01:12 -05:00
Adrian Warecki
8794de2934 intel_adsp: soc: ace: Add communication widget driver
Intel DSP Communication Widget is a device for generic sideband
message transmit/receive between IPs in a SOC.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-01-18 10:47:21 +01:00
Piotr Makaruk
00b5114344 dma: hda: enable xrun handling
Enable link under/overruns handling and reporting such events in dma
status

Signed-off-by: Piotr Makaruk <piotr.makaruk@intel.com>
2023-01-17 18:50:15 -05:00
Tomasz Leman
d6048afeea Revert "soc: intel_adsp/ace: fix CPU halting"
This reverts commit 81908cd367.

This commit introduced a regression on SOF. Value of soc_cpus_active is
set by the core X it self in functions pm_state_set and
pm_state_exit_post_ops. soc_adsp_halt_cpu can by called only by the
primary core.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2023-01-11 07:06:10 -05:00
Adrian Warecki
21f278c04b adsp: boot: power: Fixed used register name
The code used the name DFDSPBRCP referring to the DSP Boot / Recovery
Capability Pointer register from DSP Subsystem Capability / Status
Registers range. The address used, however, pointed to DSP Core Shim
(DSPCS) registers block. Changed define names to not be misleading.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-01-09 17:05:58 -05:00