If defined(CONFIG_ASSERT) and !defined(CONFIG_ADSP_IMR_CONTEXT_SAVE),
build will fail as symbol "global_imr_ram_storage" is not defined.
Link: https://github.com/thesofproject/sof/issues/6896
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
ESP32 and ESP32-S2 HW clock are tied to DTS clock configuration.
This changes updates the default configuration to retrieve
this information from DTS.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Xtensa's ESP32 misses this base CCOUNT value, which causes wrong
arch_timing_freq_get() value reference.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Save FP user register and FP register file during context switch.
This change enables shared FP registers mode using CONFIG_FPU_SHARING.
Since there is no lazy stacking, the FPU registers will be saved regardless
of whether floating point calculations are performed in the threads when
CONFIG_FPU_SHARING is enabled. This require 72 additional bytes in the
stack memory.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Add region calculations and implementation of
sys_mm_drv_query_memory_regions to pass calculated regions down
the line.
Signed-off-by: Jakub Dabek <jakub.dabek@intel.com>
Add virtual memory entry in dt to use as virtual space
regions for aplication.
Add virtual memory definition in adsp_memory.h
Signed-off-by: Jakub Dabek <jakub.dabek@intel.com>
This patch makes IMR context save an option that can be enabled. By
default FW, after D3 state transition, will be boot using normal flow.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Low-power management is part of the RTC peripherals' domain
on ESP32S2. This dependency implies the need to bring some RTC
registers to a known state, during system initialization, to
achieve proper low-power handling.
The RTC slow memory region is also delimited and used during
power domain options selection.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
- Adds initial system power management support.
- Adds option to add extra delay when waking from
deep sleep.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Low-power management is part of the RTC peripherals' domain
on ESP32. This dependency implies the need to bring some RTC
registers to a known state, during system initialization, to
achieve proper low-power handling.
The RTC slow memory region is also delimited and used during
power domain options selection.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
When MCUBoot is enabled, IRAM region needs to be set
to a smaller value to avoid overlapping. This shall be re-worked
when MCUboot build for ESP32 is performed in Zephyr environment.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Be consistency with zephyr.strip
This will help with reproducibility issues like the one in
https://github.com/thesofproject/sof-bin/pull/106
Use the `strip_command` introduced by commit c060b075a6 ("cmake:
toolchain: bintools abstraction")
boot.mod is already deterministic because it has no debug symbols; no
need to strip it.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
SOF compilation is sensitive to compilation warnings
Some simple and neutral changes to avoid them
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
IMR save and restore context is a flow implemented for ACE
move boot specific procedures to ace subdir
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
In ACE architecture, only core 0 should receive IPC interrupts from host.
Unmasking secodnary core IPC interrupts was causing race condition in
ipc irq handler after enabling secondary core.
Signed-off-by: Przemyslaw Blaszkowski <przemyslaw.blaszkowski@intel.com>
The linker script for intel_adsp ace was missing the
snippets-sections.ld include, causing it to ignore any custom section
defined in with cmake zephyr_linker_sources().
Adding it in the same location as it's done in xtensa-cavs-linker.ld.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Context save is saving whole memory to persistent
memory area, than turning off memory and CPU
Context restore is a modified boot flow, where
the previously saved context is restored
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
This patch updates ipc response procedure in power down function. New
flow is only limited to the writs into two registers. We need to clear
the IPCxIDD register in case if its contains any leftovers from a
previous responce. And then write a response to the IPCxIDR.
To prepare response we need to copy incoming request and then mark it as
replay. New message with IPC Busy bit set is then send to host.
The reason for this is a change in the behavior of the IPC driver
compared to how it worked when this function was originaly implemented.
The biggest difference are enabled interrupts in register IPCxCTL.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Zephyr maps start/end of rodata section with variables
using __rodata_region namespace. The exception was Xtensa.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Move setting soc_num_cpus into its own SYS_INIT function such
that we can ensure it happens as one of the first things. We
need soc_num_cpus set before soc_mp_init is called but also before
interrupt controller init functions might be called.
Also, by having it in its own function, it ensures that
soc_num_cpus gets set regardless of how CONFIG_MP_MAX_NUM_CPUS
is set. Since if CONFIG_MP_MAX_NUM_CPUS=1, we do not call
soc_mp_init().
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
\MTL SOF is not compiling when
8d0eb6ce10
(devicetree: remove deprecated DT_CHOSEN_*_LABEL macros)
is applied
Fix - zephyr/toolchain used to be included by
devicetree/zephyr.h. The file has been removed by 8d0eb6ce10
Include is needed for ALWAYS_INLINE macro
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
When CONFIG_MP_MAX_NUM_CPUS=1, which it does for some tests, we will
get compiler warnings with soc_adsp_halt_cpu(), so only build it
when CONFIG_MP_MAX_NUM_CPUS > 1.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
We look at the Intra DSP communications capability register (DFIDCCP)
to determine the number of cores. There might be a better way to
determine the number of cores, but this works for now.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Basically:
- Name RAMABLE_REGION as "RAM";
- Insert the relocation hooks for gen_relocate_app.py.
Also, to help with "rimage" peculiarities, `fix_elf_addrs.py` changed to
not copy empty sections to output, as this would prevent someone trying
to move all of some section (such as BSS) to a different location and
reuse the platform linker script - which would generate an empty section
anyway.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Besides adding ARCH_HAS_CODE_DATA_RELOCATION, this patch also adds
support for the "sample_controller" SoC (used by qemu_xtensa) as
demonstration.
As Xtensa lacks a common linker script at the arch level, enabling it
for each platform will be a piecemeal effort. This patch adds it to the
`soc/xtensa/sample_controller` SoC. Basically, default RAMABLE_REGION is
set to be called "RAM", and hooks are inserted so that
gen_relocate_app.py can add the relevant linker bits.
Also, `tests/application_developent/code_relocation` was tweaked to
support the qemu_xtensa platform. Basically, add the relevant linker
script and ensure that relevant memory regions have their program header
(PHDR) associated.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Xtensa is the odd one out by using _data_start/_data_end instead. Using
the Zephyr standard helps avoid ifdefs for common code, like tests.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Fix a bug where an IPC message is sent while the peer/host ack for
the previous message has not yet been processed. There is existing
logic to check 'idr' INTEL_ADSP_IPC_BUSY bit, but this leaves
the following race:
- DSP: msg A sent by DSP to host
- HOST: IRQ, msg A acked, host sets DONE bit -> ADSP_IPC_BUSY cleared
- DSP: msg B sent by DSP to host, IPC_BUSY is clear so proceeding to send
-> e.g. 'devdata->sem' is reset --> BUG!
- DSP: IRQ, msg A done
-> e.g. call to 'sem_give(&devdata->sem)' which is wrong as
the semaphore was just reset in previous step for msg B
Add additional state to track handling of the acks. This allows
to postpone sending message B (in above example), until message A
is fully processed.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Update Intel ADSP timer driver to use DT_HAS_<compat>_ENABLED Kconfig
symbol to expose the driver and enable it by default based on
devicetree.
We remove setting 'default y' for the timer driver in
Kconfig.defconfig.series as that is now handled in the driver Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Move runtime checks to use arch_num_cpus() and build checks
to use CONFIG_MP_MAX_NUM_CPUS. This is to allow runtime
determination of the number of CPUs in the future.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Move runtime checks to use arch_num_cpus(). This is to allow
runtime determination of the number of CPUs in the future.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Add #ifdef CONFIG_SMP around code that only needs to exist when
SMP is enabled.
Also include ksched.h to get decleration of z_sched_ipi.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Change for loops of the form:
for (i = 0; i < CONFIG_MP_NUM_CPUS; i++)
...
to
unsigned int num_cpus = arch_num_cpus();
for (i = 0; i < num_cpus; i++)
...
We do the call outside of the for loop so that it only happens once,
rather than on every iteration.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Fixes boot failure on CAVS platforms with
CONFIG_NO_OPTIMIZATIONS=y by moving z_soc_mp_asm_entry
into .text linker section to ensure it is copied to
SRAM.
Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
Sometimes IPC message acknowledgement should be done by external
code to provide sufficient timing (example assemble code related
to powering down). Added bool return type to ipc message done handler
that if callback function returns true, IPC API skips writing
IPC message completion bits.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
