This new binding allows to work on providing stm32u5 specific
alternate and complementary device clocks.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add a stm32u5_devices test which aims at testing devices
clock control configuration on stm32u5 targets
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add STM32 clock mux binding.
Only property of a node using such compatible is to
select a clock input.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add support for an alternate clock. If available,
alternate clock is enabled and used to get the
device clock rate.
Fixes#41650
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Make use of STM32_DT_CLOCKS_ macros to have the test work conditionally
based on alt clock presence.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add a DT based macros to be used by stm32 device drivers to
populate pclken[] arrays at build time.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add 2 clocks tests around device clock configuration on stm32h7.
For now, 'spi1_pllq_2_d1ppre_4' test variant is failed, which
illustrates issue reported in #41650.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add configure() function to clock_control API.
This function allows caller to configure a given clock.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
e8e88dea incorrectly changed registers
used in `sys_clock_cycle_get(32|64)` functions.
This commit fixes that.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
This is a follow-up to commit 586e26e8fc.
Add missing `qdec0` node labels in definitions of SoCs that have only
one QDEC instance so that the `HAS_HW_NRF_QDEC0` option is properly set
for them. Use the same pattern as in the WDT case and keep the existing
`qdec` labels for backward compatibility.
Also update validation of base addresses so that both QDEC0/QDEC and
QDEC1 are checked.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The PSM of the first channel in the connection request is used, but the
PSM value is used for all of them on the receiving side.
Signed-off-by: Herman Berget <herman.berget@nordicsemi.no>
There were some errors in the detection of ECRED connection collisions,
so the retry was triggered incorrectly.
The number of channels requested in the retry was wrong in some cases,
using the number of channels from the received request instead of the
sent request.
Signed-off-by: Herman Berget <herman.berget@nordicsemi.no>
ADC threshold control register offset is provided by devicetree, this
change will add this property into `adc_npcx_config` structure and
update macro to access register accordingly. Driver behavior is not
meant to be impacted.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Number of supported ADC thresholds is provided by devicetree, this
change will add this property into `adc_npcx_config` structure and
replace macro usage. Driver behavior is not meant to be impacted.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
When an object availability event triggers a k_work_poll
item, the object lock should not be held anymore
during the execution of the work callback.
Signed-off-by: Lucas Dietrich <ld.adecy@gmail.com>
This adds the internal function z_work_submit_to_queue(), which
submits the work item to the queue but doesn't force the thread to yield,
compared to the public function k_work_submit_to_queue().
When called from poll.c in the context of k_work_poll events, it ensures
that the thread does not yield in the context of the spinlock of object
that became available.
Fixes#45267
Signed-off-by: Lucas Dietrich <ld.adecy@gmail.com>
Debugger plugins use the `z_sys_post_kernel` variable to detect whether
the kernel is currently running, and hence whether any threads exist. As
this is just a standard variable however, after a reset the initial
value of this variable is whatever it was before reset (true) until the
bss section is zeroed halfway through `z_arm_prep_c`. Debuggers are
therefore unable to differentiate between a normally running application
and the very first stages of the boot process.
Clearing this variable as the first action upon reset allows debuggers
to display the correct thread state after the first 3 instructions have
run.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
This enables 'ARM_MPU' and 'HW_STACK_PROTECTION' for the following Texas
Instruments LaunchPad development boards:
- CC1352R1 LaunchXL
- CC1352R SensorTag
- CC26x2R1 LaunchXL
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
Incorrect device name for JLink runner causing wrong device selected,
causing issues flashing the device when flash size is large.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
The pm hooks for this target were not updated to follow the current API.
These weak functions will never be called for the pm subsystem.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
CSs now are configured properly according to DTS description during SPI
driver initialization. Earlier, additional configuration was required
due to a problem, fixed in f7466d2.
Signed-off-by: Volodymyr Bondarchuk <volodymyr.bondarchuk@nordicsemi.no>
The goal of this commit is to update existing STM32 boards descriptions
to use these size "DT_SIZE" macros to enhance readability. To realize this
i used a python script, which will detect the STM32 Boards
/zephyr/board/arm, and then will update in the dts files the partition
description using "DT_SIZE_K" and "DT_SIZE_M" macros.
Check manually and modify in .overlay files in samples and tests.
Signed-off-by: TLIG Dhaou <dhaou.tlig-ext@st.com>
Add build tests for the `espressif,esp-at` driver, together with both
the interrupt and async variants of modem_ifact_uart.
Only build the async API variant for emulated platforms, as many
platforms do not build cleanly when `UART_ASYNC_API` is enabled without
custom setup of DMA nodes.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Remove a custom Kconfig symbol that was used to indicate serial
interrupt support, as the test serial driver now selects the appropriate
symbols.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Adds a communications backend based on the asynchronous UART API,
instead of the interrupt-driven UART API. The primary advantage of this
backend is an improved robustness to dropping bytes under high interrupt
or critical section loads.
Under all loads system efficiency is improved by:
* Reducing the time spent writing out individual bytes.
* Reducing the number of UART interrupts fired.
* Waking up the RX thread much less often.
When utilising this backend over `nordic,nrf-uarte` on a nRF52840, the
baudrate of an esp-at modem could be pushed to at least 921600 without
dropping bytes, compared to a maximum of 230400 with the interrupt API.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add a choice symbol that is used to select which UART backend to use.
This allows backends that don't use the interrupt API to be implemented.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Use the proper `%p` printf specifier when printing memory addresses,
instead of casting to an integer, which may not be the same size as a
pointer.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Pretend that the serial test driver supports the interrupt and async
API's, as these can be required for various drivers. Also select
`SERIAL_HAS_DRIVER` so that the serial library will be included.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Depending on `!SERIAL_SUPPORT_INTERRUPT` to enable the driver does not
make any sense, as this is a symbol selected by drivers to signify that
they support interrupts. Simply not selecting this symbol is enough to
convey the desired intention.
This fixes Kconfig problems when the driver is compiled together with
a dummy serial driver which does select `SERIAL_SUPPORT_INTERRUPT`.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Fix writing of ICC_SRE_EL3 to or-in bits to align
with original intent to read-modify-write this
register.
Also disable FIQ and IRQ bypass so interrupt delivery
occurs through GIC. Platforms may choose to override
this behavior in z_arm64_el3_plat_init implementations.
Remove ICC_SRE_EL3 config from viper and qemu since
this is now handled in the arm64 arch core.
Signed-off-by: Eugene Cohen <quic_egmc@quicinc.com>
