This has been subsumed by the new implementation in drivers/pcie.
We remove the legacy subsystem, related tests, shell module, and
outdated documentation/config references.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Confirms build (and run) of C++17 applications that make use of STL
containers and other features.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Add a dedicated entry for Bluetooth Mesh, and include Trond from
Nordic as an owner, since he will be actively participating in
maintaining & developing the code.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
This commit adds support for the Zynq UltraScale+ MPSoC as a qemu based
platform for Cortex-R based testing. This SoC only supports an
interrupt controller and serial port for limited testing.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
This commit is an implementation of 6LoCAN, a 6Lo adaption layer for
Controller Area Networks. 6LoCAN is not yet standardised.
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
Removes very complex boot-time generation of page tables
with a much simpler runtime generation of them at bootup.
For those x86 boards that enable the MMU in the defconfig,
set the number of page pool pages appropriately.
The MMU_RUNTIME_* flags have been removed. They were an
artifact of the old page table generation and did not
correspond to any hardware state.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
littlefs is a fail-safe filesystem from ARM Mbed that has wear-leveling
capabilities.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Signed-off-by: Jim Paris <jim@bolt.io>
With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.
Redirects for the web documentation are also included.
Then zephyrbot complained about this:
"
New files added that are not covered in CODEOWNERS:
dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi
Please add one or more entries in the CODEOWNERS file to cover
those files
"
So I assigned them to those who created them. Feel free to readjust
as necessary.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Add support for virtual UART device that uses Segger RTT channels
for data transfers. Due to the RTT principle, this driver supports
only polling API.
Signed-off-by: Pavel Kral <pavel.kral@omsquare.com>
This board and SoC was discontinued some time ago and is currently not
maintained in the zephyr tree.
Remove all associated configurations and variants from the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This board and SoC was discontinued some time ago and is currently not
maintained in the zephyr tree.
Remove all associated configurations and variants from the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This board and SoC was discontinued some time ago and is currently not
maintained in the zephyr tree.
Remove all associated configurations and variants from the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add a new DTS/binding parser to scripts/dts/ for generating
generated_dts_board.conf and generated_dts_board_unfixed.h.
The old code is kept to generate some deprecated defines, using the
--deprecated-only flag. It will be removed later.
The new parser is implemented in three files in scripts/dts/:
dtlib.py:
A low-level .dts parsing library. This is similar to devicetree.py in
the old code, but is a general robust DTS parser that doesn't rely on
preprocessing.
edtlib.py (e for extended):
A library built on top of dtlib.py that brings together data from DTS
files and bindings and creates Device instances with all the data for
a device.
gen_defines.py:
A script that uses edtlib.py to generate generated_dts_board.conf and
generated_dts_board_unfixed.h. Corresponds to extract_dts_includes.py
and the files in extract/ in the old code.
testdtlib.py:
Test suite for dtlib.py. Can be run directly as a script.
testedtlib.py (uses test.dts and test-bindings/):
Test suite for edtlib.py. Can be run directly as a script.
The test suites will be run automatically in CI.
The new code turns some things that were warnings (or not checked) in
the old code into errors, like missing properties that are specified
with 'category: required' in the binding for the node.
The code includes lots of documentation and tries to give helpful error
messages instead of Python errors.
Co-authored-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This API defines following call for eSPI bus drivers
- espi_set_config
- espi_get_channel_status
- espi_send_read_request
- espi_send_write_request
- espi_send_vwire
- espi_receive_vwire
- espi_send_oob
- espi_receive_oob
- espi_flash_read
- espi_flash_write
- espi_flash_erase
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
The name disk_access_sdhc.c is ambiguous,
actually this driver depends on SPI,
rename this file.
In addition, move the generic sdhc stuff from C file
to head file for other sdhc drivers to use.
1) disk_access_sdhc.c->disk_access_spi_sdhc.c.
2) create .h and move sdhc specifications from .c to .h.
Signed-off-by: Jun Yang <jun.yang@nxp.com>
Provide two basic example samples to test the x-nucleo-iks01a3 shield:
- Standard (Mode 1)
- SensorHub (Mode 2)
Signed-off-by: Armando Visconti <armando.visconti@st.com>
A comma was added to a new path in
9dbdd81abe
But GitHub's CODEOWNERS parsing cannot handle commas in paths
=> Remove it
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Add support to STM LPS22HH pressure and temperature sensor.
The driver support I2C and SPI bus communication and both
polling and drdy trigger mode.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Making room for the Intel64 subarch in this tree. This header is
32-bit specific and so it's relocated, and references rewritten
to find it in its new location.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
The existing local APIC timer driver (loapic_timer.c) has bitrotted
and doesn't support TICKLESS_KERNEL, which is the preferred mode of
operation. This patch introduces a completely new driver, called
the APIC timer driver - the name is changed to allow the drivers to
continue to coexist in the short term, and also because "APIC timer"
isn't ambiguous (the I/O APICs do not have timers).
This driver makes no attempt to work with the MVIC timer as the
previous version did, because MVIC support is deprecated.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Add board support for 96Boards Avenger96 board from Arrow Electronics
based on STM32MP157A MPU from ST Microelectronics. This board is one
of the consumer editions boards of the 96Boards family following the
Extented CE form factor. More information about this board can be found
in 96Boards website: https://www.96boards.org/product/avenger96/
By default Zephyr console output is available via RAM console, but it
can also be changed to UART7 exposed as UART0 on 40 pin LS header.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
The Quark D2000 is the only x86 with an MVIC, and since support for
it has been dropped, the interrupt controller is orphaned. Removed.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Removed Quark D2000 SoC files and first-order related DT bindings.
A few config options have been moved from the CONFIG_* space to
the DT_* space, as they were defined in the D2000 Kconfig files
and "leaked" into the other Quark trees.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
split ext/hal/st into two modules:
- hal_stm32: For the code meant to run on STM32
- hal_st: For the code meant to drive ST components
Fixes#16316
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add board suppor for 96Boards Meerkat96 board from Novtech based on
NXP i.MX7 multi core processor. Zephyr is ported to run on the single
core Cortex-M co-processor on this board.
More information about this board can be found in 96Boards website:
https://www.96boards.org/product/imx7-96/
By default Zephyr console output is available via UART1 available at
the 40pin LS connector.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Create source directory for IA32-subarch specific files, and move
qualifying files to that subdirectory.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
