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ext: hal: make TI HAL a zephyr module

Browse source 
Move TI HAL to a module repository:
https://github.com/zephyrproject-rtos/hal_ti

managed by west.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2019-08-20 06:37:49 -07:00 • committed by Kumar Gala
commit f156e95bbd
518 changed files with 3 additions and 395654 deletions
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1
CODEOWNERS
View file

@ -211,7 +211,6 @@
/ext/hal/microchip/ @franciscomunoz @albertofloyd @scottwcpg
/ext/hal/nordic/ @carlescufi @anangl
/ext/hal/nxp/ @MaureenHelm
/ext/hal/ti/simplelink/ @vanti
/ext/lib/crypto/tinycrypt/ @ceolin
/include/ @nashif @carlescufi @galak @MaureenHelm
/include/drivers/adc.h @anangl

3
drivers/wifi/simplelink/CMakeLists.txt
View file

@ -3,9 +3,6 @@
if(CONFIG_WIFI_SIMPLELINK)
zephyr_include_directories(
.
$ENV{ZEPHYR_BASE}/ext/hal/ti/simplelink/kernel/zephyr/dpl
$ENV{ZEPHYR_BASE}/ext/hal/ti/simplelink/source
$ENV{ZEPHYR_BASE}/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/porting
$ENV{ZEPHYR_BASE}/subsys/net/lib/tls_credentials
)
zephyr_sources(

1
ext/hal/CMakeLists.txt
View file

@ -3,6 +3,5 @@ add_subdirectory(cmsis)
add_subdirectory(nordic)
add_subdirectory(nxp)
add_subdirectory(openisa)
add_subdirectory(ti)
add_subdirectory_ifdef(CONFIG_HAS_ALTERA_HAL altera)
add_subdirectory(microchip)

2
ext/hal/Kconfig
View file

@ -26,6 +26,4 @@ source "ext/hal/nxp/imx/Kconfig"
source "ext/hal/openisa/vega_sdk_riscv/Kconfig"
source "ext/hal/ti/simplelink/Kconfig"
endmenu

1
ext/hal/ti/CMakeLists.txt
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@ -1 +0,0 @@
add_subdirectory(simplelink)

60
ext/hal/ti/simplelink/CMakeLists.txt
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@ -1,60 +0,0 @@
add_subdirectory(source/ti/devices)
if(CONFIG_SIMPLELINK_HOST_DRIVER)
zephyr_include_directories(
.
source
kernel/zephyr/dpl
)
zephyr_compile_definitions(
SL_SUPPORT_IPV6
SL_PLATFORM_MULTI_THREADED
)
endif()
if(CONFIG_HAS_CC3220SDK)
if(CONFIG_SIMPLELINK_HOST_DRIVER)
zephyr_library()
zephyr_library_compile_definitions(${COMPILER})
zephyr_library_sources(
source/ti/drivers/SPI.c
source/ti/drivers/spi/SPICC32XXDMA.c
source/ti/drivers/dma/UDMACC32XX.c
source/ti/drivers/power/PowerCC32XX.c
source/ti/drivers/utils/List.c
source/ti/drivers/net/wifi/source/driver.c
source/ti/drivers/net/wifi/source/device.c
source/ti/drivers/net/wifi/source/flowcont.c
source/ti/drivers/net/wifi/source/fs.c
source/ti/drivers/net/wifi/source/netapp.c
source/ti/drivers/net/wifi/source/netcfg.c
source/ti/drivers/net/wifi/source/netutil.c
source/ti/drivers/net/wifi/source/nonos.c
source/ti/drivers/net/wifi/source/spawn.c
source/ti/drivers/net/wifi/source/wlan.c
source/ti/drivers/net/wifi/porting/CC3220SF_LAUNCHXL.c
source/ti/drivers/net/wifi/porting/cc_pal.c
source/ti/drivers/net/wifi/eventreg.c
source/ti/drivers/net/wifi/source/sl_socket.c
source/ti/devices/cc32xx/driverlib/timer.c
source/ti/devices/cc32xx/driverlib/udma.c
kernel/zephyr/dpl/dpl.c
kernel/zephyr/dpl/MutexP_zephyr.c
kernel/zephyr/dpl/SemaphoreP_zephyr.c
kernel/zephyr/dpl/ClockP_zephyr.c
kernel/zephyr/dpl/HwiP_zephyr.c
)
set_source_files_properties(source/ti/drivers/net/wifi/source/driver.c
PROPERTIES COMPILE_DEFINITIONS "__LINUX_ERRNO_EXTENSIONS__;${COMPILER}" )
set_source_files_properties(source/ti/drivers/net/wifi/source/driver.c
PROPERTIES COMPILE_FLAGS -Wno-incompatible-pointer-types) # driver.c warns on incompatible-pointer-types
endif()
elseif(CONFIG_HAS_MSP432P4XXSDK)
zephyr_include_directories(
source
)
endif()

90
ext/hal/ti/simplelink/README
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@ -1,90 +0,0 @@
The SimpleLink SDKs provide peripheral driver and WiFi libraries
and hardware register access header files for the Texas Instruments
SimpleLink SoCs.
For an explanation of the SimpleLink family SDK directory structure, see:
http://dev.ti.com/tirex/content/simplelink_cc32xx_sdk_2_40_01_01/docs/simplelink_mcu_sdk/Users_Guide.html#directory-structure
1. CC13x2/26x2 SDK
The current version supported in Zephyr is the SimpleLink CC13x2 and CC26x2 SDK
3.10.00.53, downloaded from:
http://www.ti.com/tool/simplelink-cc13x2-26x2-sdk
The driver library source is copied from the SDK, as follows:
EXT_DIR=$ZEPHYR_BASE/ext/hal/ti/simplelink/source/ti
pushd simplelink_cc13x2_26x2_sdk_3_10_00_53/source/ti
find devices/cc13x2_cc26x2/{driverlib,inc,rf_patches} -depth -name '*.[c|h]' -print0 | cpio --null -pvdm $EXT_DIR
find devices/cc13x2_cc26x2/startup_files -depth -name ccfg.c -print0 | cpio --null -pvd $EXT_DIR
find $EXT_DIR/devices/cc13x2_cc26x2 -name '*.[c|h]' -exec dos2unix {} \;
popd
The source file startup_files/ccfg.c has been modified to use the appropriate
sections when linking.
TI provides the driver library functions burned into ROM at the factory,
or updated via a service pack patch, thus saving application code space.
After setting CONFIG_HAS_CC13X2_CC26X2_SDK=y in Kconfig, most of the
peripheral driver library functions will be accessible from ROM.
2. CC32xx SDK
The current version supported in Zephyr is the SimpleLink CC32xx SDK
2.40.01.01, downloaded from:
http://www.ti.com/tool/download/simplelink-cc32xx-sdk
Source files from select subdirectories are copied from the
source/ti/ subdirectory of the SDK installation, as follows:
EXT_DIR=$ZEPHYR_BASE/ext/hal/ti/simplelink/source/ti
find devices -not -path '*/\.*' -name '*.[c|h]' | \
cpio -pdm $EXT_DIR
find drivers -name '*.[c|h]' | \
cpio -pdm $EXT_DIR
find net -maxdepth 1 -name '*.[c|h]' | cpio -pdm $EXT_DIR
cd $EXT_DIR
find . -name '*.[c|h]' -exec chmod 664 {} \;
In addition, some files in the drivers/net/wifi/porting directory
may need to be updated: notably user.h, cc_pal.h, and CC3220SF_LAUNCHXL.c.
Note: TI provides the driver library functions burned into ROM at the factory,
or updated via a service pack patch, thus saving application code space.
Calling driverlib APIs prefixed by "MAP_" will vector to those functions
already existing in ROM.
After setting CONFIG_HAS_CC3220SDK=y in Kconfig, most of the
peripheral driver library functions will be accessible from ROM,
except for some functions in the following modules, which are
compiled in the Kbuild file:
- driverlib/pin.c
- driverlib/utils.c
- driverlib/prcm.c
Setting CONFIG_SIMPLELINK_HOST_DRIVER=y builds the SimpleLink Host
Driver, which communicates over dedicated SPI to the
network coprocessor.
2. MSP432 SDK
The current version supported in Zephyr is MSP432 SDK V1.50.00.12, downloaded
from:
http://www.ti.com/tool/simplelink-msp432-sdk
Files in source/ti/devices/msp432p4xx/driverlib/ and inc/ are copied from
a Linux SDK installation (without modification).
TI provides the driver library functions burned into ROM at the factory,
or updated via a service pack patch, thus saving application code space.
Calling driverlib APIs prefixed by "MAP_" will vector to those functions
already existing in ROM.
After setting CONFIG_HAS_MSP432P4XXSDK=y in Kconfig, most of the
peripheral driver library functions will be accessible from ROM.

20
ext/hal/ti/simplelink/kernel/zephyr/dpl/ClockP_zephyr.c
View file

@ -1,20 +0,0 @@
/*
* Copyright (c) 2017, Texas Instruments Incorporated
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr.h>
#include <sys/__assert.h>
#include <kernel/zephyr/dpl/dpl.h>
#include <ti/drivers/dpl/ClockP.h>
uint32_t ClockP_getSystemTicks()
{
return (uint32_t)z_ms_to_ticks(k_uptime_get_32());
}
void ClockP_usleep(uint32_t usec)
{
k_sleep((s32_t)usec);
}

160
ext/hal/ti/simplelink/kernel/zephyr/dpl/HwiP_zephyr.c
View file

@ -1,160 +0,0 @@
/*
* Copyright (c) 2017, Texas Instruments Incorporated
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr.h>
#include <sys/__assert.h>
#include <kernel/zephyr/dpl/dpl.h>
#include <ti/drivers/dpl/HwiP.h>
#include <inc/hw_types.h>
#include <inc/hw_ints.h>
#include <driverlib/rom.h>
#include <driverlib/rom_map.h>
#include <driverlib/interrupt.h>
/*
* IRQ_CONNECT requires we know the ISR signature and argument
* at build time; whereas SimpleLink plugs the interrupts
* at run time, so we create an ISR shim, and register that.
* The callback argument doesn't change after the ISR is registered.
*/
struct sl_isr_args
{
HwiP_Fxn cb;
uintptr_t arg;
};
static struct sl_isr_args sl_UDMA_cb = {NULL, 0};
static struct sl_isr_args sl_UDMAERR_cb = {NULL, 0};
static struct sl_isr_args sl_NWPIC_cb = {NULL, 0};
static struct sl_isr_args sl_LSPI_cb = {NULL, 0};
static void sl_isr(void *isr_arg)
{
HwiP_Fxn cb = ((struct sl_isr_args *)isr_arg)->cb;
uintptr_t arg = ((struct sl_isr_args *)isr_arg)->arg;
/* Call the SimpleLink ISR Handler: */
if (cb) {
cb(arg);
}
}
/* Must hardcode the IRQ for IRQ_CONNECT macro. Must be <= CONFIG_NUM_IRQS.*/
#define EXCEPTION_UDMA 46 /* == INT_UDMA (62) - 16 */
#define EXCEPTION_UDMAERR 47 /* == INT_UDMAERR (63) - 16 */
#define EXCEPTION_NWPIC 171 /* == INT_NWPIC (187) - 16 */
#define EXCEPTION_LSPI 177 /* == INT_LSPI (193) - 16 */
HwiP_Handle HwiP_create(int interruptNum, HwiP_Fxn hwiFxn, HwiP_Params *params)
{
HwiP_Handle handle = 0;
uint32_t priority = ~0;
uintptr_t arg = 0;
if (params) {
priority = params->priority;
arg = params->arg;
}
/*
* SimpleLink only uses the NWPIC, UDMA, UDMAERR and LSPI interrupts:
*/
__ASSERT(INT_NWPIC == interruptNum || INT_UDMA == interruptNum ||
INT_UDMAERR == interruptNum || INT_LSPI == interruptNum,
"Unexpected interruptNum: %d\r\n",
interruptNum);
/*
* Priority expected is either:
* INT_PRIORITY_LVL_1,
* or ~0 or 255 (meaning lowest priority)
* ~0 and 255 are meant to be the same as INT_PRIORITY_LVL_7.
* For ~0 or 255, we want 7; but Zephyr IRQ_CONNECT adds +1,
* so we pass 6 for those TI drivers passing prio = ~0.
*/
__ASSERT((INT_PRIORITY_LVL_1 == priority) ||
(0xff == (priority & 0xff)),
"Expected priority: 0x%x or 0x%x, got: 0x%x\r\n",
INT_PRIORITY_LVL_1, 0xff, (unsigned int)priority);
switch(interruptNum) {
case INT_UDMA:
sl_UDMA_cb.cb = hwiFxn;
sl_UDMA_cb.arg = arg;
IRQ_CONNECT(EXCEPTION_UDMA, 6, sl_isr, &sl_UDMA_cb, 0);
break;
case INT_UDMAERR:
sl_UDMAERR_cb.cb = hwiFxn;
sl_UDMAERR_cb.arg = arg;
IRQ_CONNECT(EXCEPTION_UDMAERR, 6, sl_isr, &sl_UDMAERR_cb, 0);
break;
case INT_NWPIC:
sl_NWPIC_cb.cb = hwiFxn;
sl_NWPIC_cb.arg = arg;
IRQ_CONNECT(EXCEPTION_NWPIC, 1, sl_isr, &sl_NWPIC_cb, 0);
break;
case INT_LSPI:
sl_LSPI_cb.cb = hwiFxn;
sl_LSPI_cb.arg = arg;
IRQ_CONNECT(EXCEPTION_LSPI, 6, sl_isr, &sl_LSPI_cb, 0);
break;
default:
return(handle);
}
irq_enable(interruptNum - 16);
return (HwiP_Handle)interruptNum;
}
/* Can't actually de-register an interrupt in Zephyr, so just disable: */
void HwiP_delete(HwiP_Handle handle)
{
int interruptNum = (int)handle;
__ASSERT(INT_NWPIC == interruptNum || INT_UDMA == interruptNum ||
INT_UDMAERR == interruptNum || INT_LSPI == interruptNum,
"Unexpected interruptNum: %d\r\n",
interruptNum);
irq_disable(interruptNum - 16);
}
void HwiP_Params_init(HwiP_Params *params)
{
params->arg = 0;
params->priority = ~0;
}
/* Zephyr has no functions for clearing an interrupt, so use driverlib: */
void HwiP_clearInterrupt(int interruptNum)
{
MAP_IntPendClear((unsigned long)interruptNum);
}
void HwiP_enableInterrupt(int interruptNum)
{
irq_enable(interruptNum - 16);
}
void HwiP_disableInterrupt(int interruptNum)
{
irq_disable(interruptNum - 16);
}
uintptr_t HwiP_disable(void)
{
uintptr_t key;
key = irq_lock();
return (key);
}
void HwiP_restore(uintptr_t key)
{
irq_unlock(key);
}

95
ext/hal/ti/simplelink/kernel/zephyr/dpl/MutexP_zephyr.c
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@ -1,95 +0,0 @@
/*
* Copyright (c) 2017, Texas Instruments Incorporated
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr.h>
#include <sys/__assert.h>
#include <kernel/zephyr/dpl/dpl.h>
#include <ti/drivers/dpl/MutexP.h>
/*
* Zephyr kernel object pools:
*
* This bit of code enables the simplelink host driver, which assumes dynamic
* allocation of kernel objects (semaphores, mutexes, hwis), to be
* more easily ported to Zephyr (which supports static allocation).
*
* It leverages the Zephyr memory slab, enabling us to define a mutex object
* pool for use by the SimpleLink host driver.
*/
/* Define a Mutex pool: */
#define DPL_MAX_MUTEXES 4 /* From simplelink driver code inspection */
K_MEM_SLAB_DEFINE(mutex_slab, sizeof(struct k_mutex), DPL_MAX_MUTEXES,\
MEM_ALIGN);
static struct k_mutex *dpl_mutex_pool_alloc()
{
struct k_mutex *mutex_ptr = NULL;
if (k_mem_slab_alloc(&mutex_slab, (void **)&mutex_ptr,
K_NO_WAIT) < 0) {
/*
* We assert, as this is a logic error, due to a change in #
* of mutexes needed by the simplelink driver. In that case,
* the mutex pool must be increased programmatically to match.
*/
__ASSERT(0, "Increase size of DPL mutex pool");
}
return mutex_ptr;
}
static MutexP_Status dpl_mutex_pool_free(struct k_mutex *mutex)
{
k_mem_slab_free(&mutex_slab, (void **)&mutex);
return MutexP_OK;
}
MutexP_Handle MutexP_create(MutexP_Params *params)
{
struct k_mutex *mutex;
ARG_UNUSED(params);
mutex = dpl_mutex_pool_alloc();
__ASSERT(mutex, "MutexP_create failed\r\n");
if (mutex) {
k_mutex_init(mutex);
}
return ((MutexP_Handle)mutex);
}
void MutexP_delete(MutexP_Handle handle)
{
/* No way in Zephyr to "reset" the lock, so just re-init: */
k_mutex_init((struct k_mutex *)handle);
dpl_mutex_pool_free((struct k_mutex *)handle);
}
uintptr_t MutexP_lock(MutexP_Handle handle)
{
unsigned int key = 0;
int retval;
retval = k_mutex_lock((struct k_mutex *)handle, K_FOREVER);
__ASSERT(retval == 0,
"MutexP_lock: retval: %d\r\n", retval);
return ((uintptr_t)key);
}
void MutexP_Params_init(MutexP_Params *params)
{
params->callback = NULL;
}
void MutexP_unlock(MutexP_Handle handle, uintptr_t key)
{
ARG_UNUSED(key);
k_mutex_unlock((struct k_mutex *)handle);
}

140
ext/hal/ti/simplelink/kernel/zephyr/dpl/SemaphoreP_zephyr.c
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@ -1,140 +0,0 @@
/*
* Copyright (c) 2017, Texas Instruments Incorporated
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr.h>
#include <sys/__assert.h>
#include <kernel/zephyr/dpl/dpl.h>
#include <ti/drivers/dpl/SemaphoreP.h>
/*
* Zephyr kernel object pools:
*
* This bit of code enables the simplelink host driver, which assumes dynamic
* allocation of kernel objects (semaphores, mutexes, hwis), to be
* more easily ported to Zephyr (which supports static allocation).
*
* It leverages the Zephyr memory slab, enabling us to define a semaphore
* object pool for use by the SimpleLink host driver.
*/
#define DPL_MAX_SEMAPHORES 14 /* (user.h:MAX_CONCURRENT_ACTIONS+4) = 14 */
K_MEM_SLAB_DEFINE(sem_slab, sizeof(struct k_sem), DPL_MAX_SEMAPHORES,\
MEM_ALIGN);
static struct k_sem *dpl_sem_pool_alloc()
{
struct k_sem *sem_ptr = NULL;
if (k_mem_slab_alloc(&sem_slab, (void **)&sem_ptr, K_NO_WAIT) < 0) {
/*
* We assert, as this is a logic error, due to a change in #
* of semaphores needed by the simplelink driver. In that case,
* the sem pool must be increased programmatically to match.
*/
__ASSERT(0, "Increase size of DPL semaphore pool");
}
return sem_ptr;
}
static SemaphoreP_Status dpl_sem_pool_free(struct k_sem *sem)
{
k_mem_slab_free(&sem_slab, (void **)&sem);
return SemaphoreP_OK;
}
/* timeout comes in and out as milliSeconds: */
static int32_t dpl_convert_timeout(uint32_t timeout)
{
int32_t zephyr_timeout;
switch(timeout) {
case SemaphoreP_NO_WAIT:
zephyr_timeout = K_NO_WAIT;
break;
case SemaphoreP_WAIT_FOREVER:
zephyr_timeout = K_FOREVER;
break;
default:
zephyr_timeout = timeout;
}
return zephyr_timeout;
}
SemaphoreP_Handle SemaphoreP_create(unsigned int count,
SemaphoreP_Params *params)
{
unsigned int limit = UINT_MAX;
struct k_sem *sem;
if (params) {
limit = (params->mode == SemaphoreP_Mode_BINARY) ?
1 : UINT_MAX;
}
sem = dpl_sem_pool_alloc();
if (sem) {
k_sem_init(sem, 0, limit);
}
return (SemaphoreP_Handle)sem;
}
SemaphoreP_Handle SemaphoreP_createBinary(unsigned int count)
{
SemaphoreP_Params params;
SemaphoreP_Params_init(&params);
params.mode = SemaphoreP_Mode_BINARY;
return (SemaphoreP_create(count, &params));
}
void SemaphoreP_delete(SemaphoreP_Handle handle)
{
k_sem_reset((struct k_sem *)handle);
(void)dpl_sem_pool_free((struct k_sem *)handle);
}
void SemaphoreP_Params_init(SemaphoreP_Params *params)
{
params->mode = SemaphoreP_Mode_COUNTING;
params->callback = NULL;
}
/*
* The SimpleLink driver calls this function with a timeout of 0 to "clear"
* the SyncObject, rather than calling dpl_SyncObjClear() directly.
* See: <simplelinksdk>/source/ti/drivers/net/wifi/source/driver.h
* #define SL_DRV_SYNC_OBJ_CLEAR(pObj)
* (void)sl_SyncObjWait(pObj,SL_OS_NO_WAIT);
*
* So, we claim (via simplelink driver code inspection), that SyncObjWait
* will *only* be called with timeout == 0 if the intention is to clear the
* semaphore: in that case, we just call k_sem_reset.
*/
SemaphoreP_Status SemaphoreP_pend(SemaphoreP_Handle handle, uint32_t timeout)
{
int retval;
if (0 == timeout) {
k_sem_reset((struct k_sem *)handle);
retval = SemaphoreP_OK;
} else {
retval = k_sem_take((struct k_sem *)handle,
dpl_convert_timeout(timeout));
__ASSERT_NO_MSG(retval != -EBUSY);
retval = (retval >= 0) ? SemaphoreP_OK : SemaphoreP_TIMEOUT;
}
return retval;
}
void SemaphoreP_post(SemaphoreP_Handle handle)
{
k_sem_give((struct k_sem *)handle);
}

116
ext/hal/ti/simplelink/kernel/zephyr/dpl/dpl.c
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@ -1,116 +0,0 @@
/*
* Copyright (c) 2017, Texas Instruments Incorporated
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <zephyr.h>
#include <device.h>
#include <init.h>
#include <sys/util.h>
#include <sys/__assert.h>
#include <inc/hw_types.h>
#include <inc/hw_ints.h>
#include <driverlib/rom_map.h>
#include <driverlib/interrupt.h>
#include <ti/drivers/net/wifi/simplelink.h>
#include <kernel/zephyr/dpl/dpl.h>
#define SPAWN_TASK_STACKSIZE 2048
/*
* Priority must be higher than any thread priority in the system which
* might use the SimpleLink host driver, which involves the spawn_task().
* Since SimpleLink APIs may be called from any thread, including
* cooperative threads, and the _main kernel thread, we must set this
* as highest prioirty.
*/
#define SPAWN_TASK_PRIORITY K_HIGHEST_THREAD_PRIO
/* Spawn message queue size: Could be 1, but 3 is used by other DPL ports */
#define SPAWN_QUEUE_SIZE ( 3 )
/* Stack, for the simplelink spawn task: */
static K_THREAD_STACK_DEFINE(spawn_task_stack, SPAWN_TASK_STACKSIZE);
static struct k_thread spawn_task_data;
static void spawn_task(void *unused1, void *unused2, void *unused3);
/*
* MessageQ to send message from an ISR or other task to the SimpleLink
* "Spawn" task:
*/
K_MSGQ_DEFINE(spawn_msgq, sizeof(tSimpleLinkSpawnMsg), SPAWN_QUEUE_SIZE,\
MEM_ALIGN);
/*
* SimpleLink does not have an init hook, so we export this function to
* be called early during system initialization.
*/
static int dpl_zephyr_init(struct device *port)
{
(void)k_thread_create(&spawn_task_data, spawn_task_stack,
SPAWN_TASK_STACKSIZE, spawn_task,
NULL, NULL, NULL,
SPAWN_TASK_PRIORITY, 0, K_NO_WAIT);
return 0;
}
SYS_INIT(dpl_zephyr_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
/* SimpleLink driver code can call this from ISR or task context: */
_SlReturnVal_t os_Spawn(P_OS_SPAWN_ENTRY pEntry, void *pValue,
unsigned long flags)
{
tSimpleLinkSpawnMsg slMsg;
_SlReturnVal_t retval;
slMsg.pEntry = pEntry;
slMsg.pValue = pValue;
if (0 == k_msgq_put(&spawn_msgq, &slMsg, K_NO_WAIT)) {
retval = OS_OK;
}
else {
retval = -1;
__ASSERT(retval == OS_OK,
"os_Spawn: Failed to k_msgq_put failed\r\n");
}
return retval;
}
void spawn_task(void *unused1, void *unused2, void *unused3)
{
tSimpleLinkSpawnMsg slMsg;
ARG_UNUSED(unused1);
ARG_UNUSED(unused2);
ARG_UNUSED(unused3);
while (1) {
k_msgq_get(&spawn_msgq, &slMsg, K_FOREVER);
slMsg.pEntry(slMsg.pValue);
}
}
#if CONFIG_ERRNO && !defined(SL_INC_INTERNAL_ERRNO)
/*
* Called by the SimpleLink host driver to set POSIX error codes
* for the host OS.
*/
int dpl_set_errno(int err)
{
/* Ensure (POSIX) errno is positive.
* __errno() is a Zephyr function returning a pointer to the
* current thread's errno variable.
*/
*__errno() = (err < 0? -err : err);
return -1;
}
#endif

9
ext/hal/ti/simplelink/kernel/zephyr/dpl/dpl.h
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@ -1,9 +0,0 @@
/*
* Copyright (c) 2017, Texas Instruments Incorporated
*
* SPDX-License-Identifier: Apache-2.0
*/
#define MEM_ALIGN (sizeof(uint32_t))
extern int *__errno(void);

3
ext/hal/ti/simplelink/source/ti/devices/CMakeLists.txt
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@ -1,3 +0,0 @@
add_subdirectory_ifdef(CONFIG_HAS_CC3220SDK cc32xx)
add_subdirectory_ifdef(CONFIG_HAS_MSP432P4XXSDK msp432p4xx)
add_subdirectory_ifdef(CONFIG_HAS_CC13X2_CC26X2_SDK cc13x2_cc26x2)

198
ext/hal/ti/simplelink/source/ti/devices/DeviceFamily.h
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/*
* Copyright (c) 2017-2018, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** ============================================================================
* @file DeviceFamily.h
*
* @brief Infrastructure to select correct driverlib path and identify devices
*
* This module enables the selection of the correct driverlib path for the current
* device. It also facilitates the use of per-device conditional compilation
* to enable minor variations in drivers between devices.
*
* In order to use this functionality, DeviceFamily_XYZ must be defined as one of
* the supported values. The DeviceFamily_ID and DeviceFamily_DIRECTORY defines
* are set based on DeviceFamily_XYZ.
*/
#ifndef ti_devices_DeviceFamily__include
#define ti_devices_DeviceFamily__include
#ifdef __cplusplus
extern "C" {
#endif
/*
* DeviceFamily_ID_XYZ values.
*
* DeviceFamily_ID may be used in the preprocessor for conditional compilation.
* DeviceFamily_ID is set to one of these values based on the top level
* DeviceFamily_XYZ define.
*/
#define DeviceFamily_ID_CC13X0 1
#define DeviceFamily_ID_CC26X0 2
#define DeviceFamily_ID_CC26X0R2 3
#define DeviceFamily_ID_CC13X2 4
#define DeviceFamily_ID_CC26X2 5
#define DeviceFamily_ID_CC3200 8
#define DeviceFamily_ID_CC3220 9
#define DeviceFamily_ID_MSP432P401x 10
#define DeviceFamily_ID_MSP432P4x1xI 11
#define DeviceFamily_ID_MSP432P4x1xT 12
#define DeviceFamily_ID_MSP432E401Y 13
#define DeviceFamily_ID_MSP432E411Y 14
/*
* DeviceFamily_PARENT_XYZ values.
*
* DeviceFamily_PARENT may be used in the preprocessor for conditional
* compilation. DeviceFamily_PARENT is set to one of these values based
* on the top-level DeviceFamily_XYZ define.
*/
#define DeviceFamily_PARENT_CC13X0_CC26X0 1
#define DeviceFamily_PARENT_CC13X2_CC26X2 2
#define DeviceFamily_PARENT_MSP432P401R 3
#define DeviceFamily_PARENT_MSP432P4111 4
/*
* Lookup table that sets DeviceFamily_ID, DeviceFamily_DIRECTORY, and
* DeviceFamily_PARENT based on the DeviceFamily_XYZ define.
* If DeviceFamily_XYZ is undefined, a compiler error is thrown. If
* multiple DeviceFamily_XYZ are defined, the first one encountered is used.
*/
#if defined(DeviceFamily_CC13X0)
#define DeviceFamily_ID DeviceFamily_ID_CC13X0
#define DeviceFamily_DIRECTORY cc13x0
#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0
#elif defined(DeviceFamily_CC13X2)
#define DeviceFamily_ID DeviceFamily_ID_CC13X2
#define DeviceFamily_DIRECTORY cc13x2_cc26x2
#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2
#elif defined(DeviceFamily_CC26X0)
#define DeviceFamily_ID DeviceFamily_ID_CC26X0
#define DeviceFamily_DIRECTORY cc26x0
#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0
#elif defined(DeviceFamily_CC26X0R2)
#define DeviceFamily_ID DeviceFamily_ID_CC26X0R2
#define DeviceFamily_DIRECTORY cc26x0r2
#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0
#elif defined(DeviceFamily_CC26X2)
#define DeviceFamily_ID DeviceFamily_ID_CC26X2
#define DeviceFamily_DIRECTORY cc13x2_cc26x2
#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2
#elif defined(DeviceFamily_CC3200)
#define DeviceFamily_ID DeviceFamily_ID_CC3200
#define DeviceFamily_DIRECTORY cc32xx
#elif defined(DeviceFamily_CC3220)
#define DeviceFamily_ID DeviceFamily_ID_CC3220
#define DeviceFamily_DIRECTORY cc32xx
#elif defined(DeviceFamily_MSP432P401x) || defined(__MSP432P401R__)
#define DeviceFamily_ID DeviceFamily_ID_MSP432P401x
#define DeviceFamily_DIRECTORY msp432p4xx
#define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P401R
#if !defined(__MSP432P401R__)
#define __MSP432P401R__
#endif
#elif defined(DeviceFamily_MSP432P4x1xI)
#define DeviceFamily_ID DeviceFamily_ID_MSP432P4x1xI
#define DeviceFamily_DIRECTORY msp432p4xx
#define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P4111
#if !defined(__MSP432P4111__)
#define __MSP432P4111__
#endif
#elif defined(DeviceFamily_MSP432P4x1xT)
#define DeviceFamily_ID DeviceFamily_ID_MSP432P4x1xT
#define DeviceFamily_DIRECTORY msp432p4xx
#define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P4111
#if !defined(__MSP432P4111__)
#define __MSP432P4111__
#endif
#elif defined(DeviceFamily_MSP432E401Y)
#define DeviceFamily_ID DeviceFamily_ID_MSP432E401Y
#define DeviceFamily_DIRECTORY msp432e4
#if !defined(__MSP432E401Y__)
#define __MSP432E401Y__
#endif
#elif defined(DeviceFamily_MSP432E411Y)
#define DeviceFamily_ID DeviceFamily_ID_MSP432E411Y
#define DeviceFamily_DIRECTORY msp432e4
#if !defined(__MSP432E411Y__)
#define __MSP432E411Y__
#endif
#else
#error "DeviceFamily_XYZ undefined. You must define a DeviceFamily_XYZ!"
#endif
/* Ensure that only one DeviceFamily was specified */
#if (defined(DeviceFamily_CC13X0) + defined(DeviceFamily_CC13X2) \
+ defined(DeviceFamily_CC26X0) + defined(DeviceFamily_CC26X0R2) \
+ defined(DeviceFamily_CC26X2) \
+ defined(DeviceFamily_CC3200) + defined(DeviceFamily_CC3220) \
+ defined(DeviceFamily_MSP432P401x) + defined(DeviceFamily_MSP432P4x1xI) \
+ defined(DeviceFamily_MSP432P4x1xT) + defined(DeviceFamily_MSP432E401Y) \
+ defined(DeviceFamily_MSP432E411Y) \
) > 1
#error More then one DeviceFamily has been defined!
#endif
/*!
* @brief Macro to include correct driverlib path.
*
* @pre DeviceFamily_XYZ which sets DeviceFamily_DIRECTORY must be defined
* first.
*
* @param x A token containing the path of the file to include based on
* the root device folder. The preceding forward slash must be
* omitted. For example:
* - #include DeviceFamily_constructPath(inc/hw_memmap.h)
* - #include DeviceFamily_constructPath(driverlib/ssi.h)
*
* @return Returns an include path.
*
*/
#define DeviceFamily_constructPath(x) <ti/devices/DeviceFamily_DIRECTORY/x>
#ifdef __cplusplus
}
#endif
#endif /* ti_devices_DeviceFamily__include */

16
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/CMakeLists.txt
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@ -1,16 +0,0 @@
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(
.
)
zephyr_library()
zephyr_library_compile_definitions(${COMPILER})
zephyr_library_sources(
# Required for SystemTrimDevice which is not in ROM
driverlib/setup.c
driverlib/chipinfo.c
driverlib/aux_sysif.c
# Required for CPUdelay which is not in ROM
driverlib/cpu.c
)

43
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/adi.c
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@ -1,43 +0,0 @@
/******************************************************************************
* Filename: adi.c
* Revised: 2016-11-17 16:39:28 +0100 (Thu, 17 Nov 2016)
* Revision: 47706
*
* Description: Driver for the ADI interface
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "../inc/hw_types.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_aux_smph.h"
#include "adi.h"
#include "cpu.h"

791
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/adi.h
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@ -1,791 +0,0 @@
/******************************************************************************
* Filename: adi.h
* Revised: 2016-11-17 16:39:28 +0100 (Thu, 17 Nov 2016)
* Revision: 47706
*
* Description: Defines and prototypes for the ADI master interface.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup analog_group
//! @{
//! \addtogroup adi_api
//! @{
//
//*****************************************************************************
#ifndef __ADI_H__
#define __ADI_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdbool.h>
#include <stdint.h>
#include "../inc/hw_types.h"
#include "../inc/hw_uart.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_ints.h"
#include "../inc/hw_adi.h"
#include "debug.h"
#include "ddi.h"
//*****************************************************************************
//
// Number of registers in the ADI slave
//
//*****************************************************************************
#define ADI_SLAVE_REGS 16
//*****************************************************************************
//
// Defines that is used to control the ADI slave and master
//
//*****************************************************************************
#define ADI_PROTECT 0x00000080
#define ADI_ACK 0x00000001
#define ADI_SYNC 0x00000000
//*****************************************************************************
//
// API Functions and prototypes
//
//*****************************************************************************
#ifdef DRIVERLIB_DEBUG
//*****************************************************************************
//
//! \internal
//! \brief Checks an ADI base address.
//!
//! This function determines if an ADI port base address is valid.
//!
//! \param ui32Base is the base address of the ADI port.
//!
//! \return Returns \c true if the base address is valid and \c false
//! otherwise
//
//*****************************************************************************
static bool
ADIBaseValid(uint32_t ui32Base)
{
return(ui32Base == ADI2_BASE || ui32Base == ADI3_BASE ||
ui32Base == AUX_ADI4_BASE);
}
#endif
//*****************************************************************************
//
//! \brief Write an 8 bit value to a register in an ADI slave.
//!
//! This function will write a value to a single register in the analog domain.
//! The access to the registers in the analog domain is either 8, 16, or 32 bit
//! aligned. You can only do 16 bit access on registers 0-1 / 2-3, etc. Similarly
//! 32 bit accesses are always performed on register 0-3 / 4-7, etc. Addresses
//! for the registers and values being written to the registers will be
//! truncated according to this access scheme.
//!
//! \note This operation is write only for the specified register. No
//! previous value of the register will be kept (i.e. this is NOT
//! read-modify-write on the register).
//!
//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be
//! enabled before calling this function.
//!
//! \param ui32Base is ADI base address.
//! \param ui32Reg is the register to write.
//! \param ui8Val is the 8 bit value to write to the register.
//!
//! \return None
//!
//! \sa ADI16RegWrite(), ADI32RegWrite()
//
//*****************************************************************************
__STATIC_INLINE void
ADI8RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val)
{
// Check the arguments.
ASSERT(ADIBaseValid(ui32Base));
ASSERT(ui32Reg < ADI_SLAVE_REGS);
// Write the value to the register.
HWREGB(ui32Base + ui32Reg) = ui8Val;
}
//*****************************************************************************
//
//! \brief Write a 16 bit value to 2 registers in the ADI slave.
//!
//! This function will write a value to 2 consecutive registers in the analog
//! domain. The access to the registers in the analog domain is either 8, 16
//! or 32 bit aligned. You can only do 16 bit access on registers 0-1 / 2-3,
//! etc. Similarly 32 bit accesses are always performed on register 0-3 / 4-7,
//! etc. Addresses for the registers and values being written
//! to the registers will be truncated according to this access scheme.
//!
//! \note The byte addressing bit will be ignored, to ensure 16 bit access
//! to the ADI slave.
//!
//! \note This operation is write only for the specified register. No
//! previous value of the register will be kept (i.e. this is NOT
//! read-modify-write on the register).
//!
//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be
//! enabled before calling this function.
//!
//! \param ui32Base is ADI base address.
//! \param ui32Reg is the register to write.
//! \param ui16Val is the 16 bit value to write to the register.
//!
//! \return None
//!
//! \sa ADI8RegWrite(), ADI32RegWrite()
//
//*****************************************************************************
__STATIC_INLINE void
ADI16RegWrite(uint32_t ui32Base, uint32_t ui32Reg,
uint16_t ui16Val)
{
// Check the arguments.
ASSERT(ADIBaseValid(ui32Base));
ASSERT(ui32Reg < ADI_SLAVE_REGS);
// Write the value to the register.
HWREGH(ui32Base + (ui32Reg & 0xFE)) = ui16Val;
}
//*****************************************************************************
//
//! \brief Write a 32 bit value to 4 registers in the ADI slave.
//!
//! This function will write a value to 4 consecutive registers in the analog
//! domain. The access to the registers in the analog domain is either 8, 16
//! or 32 bit aligned. You can only do 16 bit access on registers 0-1 / 2-3,
//! etc. Similarly 32 bit accesses are always performed on register 0-3 / 4-7,
//! etc. Addresses for the registers and values being written
//! to the registers will be truncated according to this access scheme.
//!
//! \note The byte and half word addressing bits will be ignored, to ensure
//! 32 bit access to the ADI slave.
//!
//! \note This operation is write only for the specified register. No
//! previous value of the register will be kept (i.e. this is NOT
//! read-modify-write on the register).
//!
//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be
//! enabled before calling this function.
//!
//! \param ui32Base is ADI base address.
//! \param ui32Reg is the register to write.
//! \param ui32Val is the 32 bit value to write to the register.
//!
//! \return None
//!
//! \sa ADI8RegWrite(), ADI16RegWrite()
//
//*****************************************************************************
__STATIC_INLINE void
ADI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val)
{
// Check the arguments.
ASSERT(ADIBaseValid(ui32Base));
ASSERT(ui32Reg < ADI_SLAVE_REGS);
// Write the value to the register.
HWREG(ui32Base + (ui32Reg & 0xFC)) = ui32Val;
}
//*****************************************************************************
//
//! \brief Read the value of an 8 bit register in the ADI slave.
//!
//! This function will read an 8 bit register in the analog domain and return
//! the value as the lower 8 bits of an \c uint32_t. The access to the
//! registers in the analog domain is either 8, 16 or 32 bit aligned. You can
//! only do 16 bit access on registers 0-1 / 2-3, etc. Similarly 32 bit accesses
//! are always performed on register 0-3 / 4-7, etc. Addresses for the
//! registers and values being written to the registers will be truncated
//! according to this access scheme.
//!
//! \param ui32Base is ADI base address.
//! \param ui32Reg is the 8 bit register to read.
//!
//! \return Returns the 8 bit value of the analog register in the least
//! significant byte of the \c uint32_t.
//!
//! \sa ADI16RegRead(), ADI32RegRead()
//
//*****************************************************************************
__STATIC_INLINE uint32_t
ADI8RegRead(uint32_t ui32Base, uint32_t ui32Reg)
{
// Check the arguments.
ASSERT(ADIBaseValid(ui32Base));
ASSERT(ui32Reg < ADI_SLAVE_REGS);
// Read the register and return the value.
return(HWREGB(ui32Base + ui32Reg));
}
//*****************************************************************************
//
//! \brief Read the value in a 16 bit register.
//!
//! This function will read 2 x 8 bit registers in the analog domain and return
//! the value as the lower 16 bits of an \c uint32_t. The access to the
//! registers in the analog domain is either 8, 16 or 32 bit aligned. You can
//! only do 16 bit access on registers 0-1 / 2-3, etc. Similarly 32 bit accesses
//! are always performed on register 0-3 / 4-7, etc. Addresses for the
//! registers and values being written to the registers will be truncated
//! according to this access scheme.
//!
//! \note The byte addressing bit will be ignored, to ensure 16 bit access
//! to the ADI slave.
//!
//! \param ui32Base is ADI base address.
//! \param ui32Reg is the 16 bit register to read.
//!
//! \return Returns the 16 bit value of the 2 analog register in the 2 least
//! significant bytes of the \c uint32_t.
//!
//! \sa ADI8RegRead(), ADI32RegRead()
//
//*****************************************************************************
__STATIC_INLINE uint32_t
ADI16RegRead(uint32_t ui32Base, uint32_t ui32Reg)
{
// Check the arguments.
ASSERT(ADIBaseValid(ui32Base));
ASSERT(ui32Reg < ADI_SLAVE_REGS);
// Read the registers and return the value.
return(HWREGH(ui32Base + (ui32Reg & 0xFE)));
}
//*****************************************************************************
//
//! \brief Read the value in a 32 bit register.
//!
//! This function will read 4 x 8 bit registers in the analog domain and return
//! the value as an \c uint32_t. The access to the registers in the analog
//! domain is either 8, 16 or 32 bit aligned. You can only do 16 bit access on
//! registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always performed on
//! register 0-3 / 4-7, etc. Addresses for the registers and values being
//! written to the registers will be truncated according to this access scheme.
//!
//! \note The byte and half word addressing bits will be ignored, to ensure
//! 32 bit access to the ADI slave.
//!
//! \param ui32Base is ADI base address.
//! \param ui32Reg is the 32 bit register to read.
//!
//! \return Returns the 32 bit value of the 4 analog registers.
//!
//! \sa ADI8RegRead(), ADI16RegRead()
//
//*****************************************************************************
__STATIC_INLINE uint32_t
ADI32RegRead(uint32_t ui32Base, uint32_t ui32Reg)
{
// Check the arguments.
ASSERT(ADIBaseValid(ui32Base));
ASSERT(ui32Reg < ADI_SLAVE_REGS);
// Read the registers and return the value.
return(HWREG(ui32Base + (ui32Reg & 0xFC)));
}
//*****************************************************************************
//
//! \brief Set specific bits in a single 8 bit ADI register.
//!
//! This function will set bits in a single register in the analog domain.
//! The access to the registers in the analog domain is either 8, 16 or 32 bit
//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access
//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always
//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values
//! being written to the registers will be truncated according to this access
//! scheme.
//!
//! \note This operation is write only for the specified register.
//! This function is used to set bits in a specific 8 bit register in the
//! ADI slave. Only bits in the selected register are affected by the
//! operation.
//!
//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be
//! enabled before calling this function.
//!
//! \param ui32Base is ADI base address.
//! \param ui32Reg is the base register to assert the bits in.
//! \param ui8Val is the 8 bit one-hot encoded value specifying which
//! bits to set in the register.
//!
//! \return None
//!
//! \sa ADI16BitsSet(), ADI32BitsSet()
//
//*****************************************************************************
__STATIC_INLINE void
ADI8BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val)
{
uint32_t ui32RegOffset;
// Check the arguments.
ASSERT(ADIBaseValid(ui32Base));
ASSERT(ui32Reg < ADI_SLAVE_REGS);
// Get the correct address of the first register used for setting bits
// in the ADI slave.
ui32RegOffset = ADI_O_SET;
// Set the selected bits.
HWREGB(ui32Base + ui32RegOffset + ui32Reg) = ui8Val;
}
//*****************************************************************************
//
//! \brief Set specific bits in 2 x 8 bit ADI slave registers.
//!
//! This function will set bits in 2 registers in the analog domain.
//! The access to the registers in the analog domain is either 8, 16 or 32 bit
//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access
//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always
//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values
//! being written to the registers will be truncated according to this access
//! scheme.
//!
//! \note This operation is write only for the specified register.
//! This function is used to set bits in 2 consecutive 8 bit registers in the
//! ADI slave. Only bits in the selected registers are affected by the
//! operation.
//!
//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be
//! enabled before calling this function.
//!
//! \param ui32Base is ADI base address.
//! \param ui32Reg is the base register to assert the bits in.
//! \param ui16Val is the 16 bit one-hot encoded value specifying which
//! bits to set in the registers.
//!
//! \return None
//!
//! \sa ADI8BitsSet(), ADI32BitsSet()
//
//*****************************************************************************
__STATIC_INLINE void
ADI16BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint16_t ui16Val)
{
uint32_t ui32RegOffset;
// Check the arguments.
ASSERT(ADIBaseValid(ui32Base));
ASSERT(ui32Reg < ADI_SLAVE_REGS);
// Get the correct address of the first register used for setting bits
// in the ADI slave.
ui32RegOffset = ADI_O_SET;
// Set the selected bits.
HWREGH(ui32Base + ui32RegOffset + (ui32Reg & 0xFE)) = ui16Val;
}
//*****************************************************************************
//
//! \brief Set specific bits in 4 x 8 bit ADI slave registers.
//!
//! This function will set bits in 4 registers in the analog domain.
//! The access to the registers in the analog domain is either 8, 16 or 32 bit
//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access
//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always
//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values
//! being written to the registers will be truncated according to this access
//! scheme.
//!
//! \note This operation is write only for the specified register.
//! This function is used to set bits in 4 consecutive 8 bit registers in the
//! ADI slave. Only bits in the selected registers are affected by the
//! operation.
//!
//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be
//! enabled before calling this function.
//!
//! \param ui32Base is ADI base address.
//! \param ui32Reg is the base register to assert the bits in.
//! \param ui32Val is the 32 bit one-hot encoded value specifying which
//! bits to set in the registers.
//!
//! \return None
//!
//! \sa ADI8BitsSet(), ADI16BitsSet()
//
//*****************************************************************************
__STATIC_INLINE void
ADI32BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val)
{
uint32_t ui32RegOffset;
// Check the arguments.
ASSERT(ADIBaseValid(ui32Base));
ASSERT(ui32Reg < ADI_SLAVE_REGS);
// Get the correct address of the first register used for setting bits
// in the ADI slave.
ui32RegOffset = ADI_O_SET;
// Set the selected bits.
HWREG(ui32Base + ui32RegOffset + (ui32Reg & 0xFC)) = ui32Val;
}
//*****************************************************************************
//
//! \brief Clear specific bits in an 8 bit ADI register.
//!
//! This function will clear bits in a register in the analog domain.
//! The access to the registers in the analog domain is either 8, 16 or 32 bit
//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access
//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always
//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values
//! being written to the registers will be truncated according to this access
//! scheme.
//!
//! \note This operation is write only for the specified register.
//! This function is used to clear bits in a specific 8 bit register in
//! the ADI slave. Only bits in the selected register are affected by the
//! operation.
//!
//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be
//! enabled before calling this function.
//!
//! \param ui32Base is ADI base address.
//! \param ui32Reg is the base registers to clear the bits in.
//! \param ui8Val is the 8 bit one-hot encoded value specifying which
//! bits to clear in the register.
//!
//! \return None
//!
//! \sa ADI16BitsClear(), ADI32BitsClear()
//
//*****************************************************************************
__STATIC_INLINE void
ADI8BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val)
{
uint32_t ui32RegOffset;
// Check the arguments.
ASSERT(ADIBaseValid(ui32Base));
ASSERT(ui32Reg < ADI_SLAVE_REGS);
// Get the correct address of the first register used for setting bits
// in the ADI slave.
ui32RegOffset = ADI_O_CLR;
// Set the selected bits.
HWREGB(ui32Base + ui32RegOffset + ui32Reg) = ui8Val;
}
//*****************************************************************************
//
//! \brief Clear specific bits in two 8 bit ADI register.
//!
//! This function will clear bits in 2 registers in the analog domain.
//! The access to the registers in the analog domain is either 8, 16 or 32 bit
//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access
//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always
//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values
//! being written to the registers will be truncated according to this access
//! scheme.
//!
//! \note This operation is write only for the specified register.
//! This function is used to clear bits in 2 consecutive 8 bit registers in
//! the ADI slave. Only bits in the selected registers are affected by the
//! operation.
//!
//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be
//! enabled before calling this function.
//!
//! \param ui32Base is ADI base address.
//! \param ui32Reg is the base registers to clear the bits in.
//! \param ui16Val is the 16 bit one-hot encoded value specifying which
//! bits to clear in the registers.
//!
//! \return None
//!
//! \sa ADI8BitsClear(), ADI32BitsClear()
//
//*****************************************************************************
__STATIC_INLINE void
ADI16BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint16_t ui16Val)
{
uint32_t ui32RegOffset;
// Check the arguments.
ASSERT(ADIBaseValid(ui32Base));
ASSERT(ui32Reg < ADI_SLAVE_REGS);
// Get the correct address of the first register used for setting bits
// in the ADI slave.
ui32RegOffset = ADI_O_CLR;
// Set the selected bits.
HWREGH(ui32Base + ui32RegOffset + (ui32Reg & 0xFE)) = ui16Val;
}
//*****************************************************************************
//
//! \brief Clear specific bits in four 8 bit ADI register.
//!
//! This function will clear bits in 4 registers in the analog domain.
//! The access to the registers in the analog domain is either 8, 16 or 32 bit
//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access
//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always
//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values
//! being written to the registers will be truncated according to this access
//! scheme.
//!
//! \note This operation is write only for the specified register.
//! This function is used to clear bits in 4 consecutive 8 bit registers in
//! the ADI slave. Only bits in the selected registers are affected by the
//! operation.
//!
//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be
//! enabled before calling this function.
//!
//! \param ui32Base is ADI base address.
//! \param ui32Reg is the base registers to clear the bits in.
//! \param ui32Val is the 32 bit one-hot encoded value specifying which
//! bits to clear in the registers.
//!
//! \return None
//!
//! \sa ADI8BitsClear(), ADI16BitsClear()
//
//*****************************************************************************
__STATIC_INLINE void
ADI32BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val)
{
uint32_t ui32RegOffset;
// Check the arguments.
ASSERT(ADIBaseValid(ui32Base));
ASSERT(ui32Reg < ADI_SLAVE_REGS);
// Get the correct address of the first register used for setting bits
// in the ADI slave.
ui32RegOffset = ADI_O_CLR;
// Set the selected bits.
HWREG(ui32Base + ui32RegOffset + (ui32Reg & 0xFC)) = ui32Val;
}
//*****************************************************************************
//
//! \brief Set a value on any 4 bits inside an 8 bit register in the ADI slave.
//!
//! This function allows halfbyte (4 bit) access to the ADI slave registers.
//! The parameter \c bWriteHigh determines whether to write to the lower
//! or higher part of the 8 bit register.
//!
//! Use this function to write any value in the range 0-3 bits aligned on a
//! half byte boundary. Fx. for writing the value 0b101 to bits 1 to 3 the
//! \c ui8Val = 0xA and the \c ui8Mask = 0xE. Bit 0 will not be affected by
//! the operation, as the corresponding bit is not set in the \c ui8Mask.
//!
//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be
//! enabled before calling this function.
//!
//! \param ui32Base is the base address of the ADI port.
//! \param ui32Reg is the Least Significant Register in the ADI slave that
//! will be affected by the write operation.
//! \param bWriteHigh defines which part of the register to write in.
//! - \c true: Write upper half byte of register.
//! - \c false: Write lower half byte of register.
//! \param ui8Mask is the mask defining which of the 4 bits that should be
//! overwritten. The mask must be defined in the lower half of the 8 bits of
//! the parameter.
//! \param ui8Val is the value to write. The value must be defined in the lower
//! half of the 8 bits of the parameter.
//!
//! \return None
//!
//! \sa ADI8SetValBit(), ADI16SetValBit
//
//*****************************************************************************
__STATIC_INLINE void
ADI4SetValBit(uint32_t ui32Base, uint32_t ui32Reg, bool bWriteHigh,
uint8_t ui8Mask, uint8_t ui8Val)
{
uint32_t ui32RegOffset;
// Check the arguments.
ASSERT(ADIBaseValid(ui32Base));
ASSERT(ui32Reg < ADI_SLAVE_REGS);
ASSERT(!(ui8Val & 0xF0));
ASSERT(!(ui8Mask & 0xF0));
// Get the correct address of the first register used for setting bits
// in the ADI slave.
ui32RegOffset = ADI_O_MASK4B + (ui32Reg << 1) + (bWriteHigh ? 1 : 0);
// Set the selected bits.
HWREGB(ui32Base + ui32RegOffset) = (ui8Mask << 4) | ui8Val;
}
//*****************************************************************************
//
//! \brief Set a value on any bits inside an 8 bit register in the ADI slave.
//!
//! This function allows byte (8 bit) access to the ADI slave registers.
//!
//! Use this function to write any value in the range 0-7 bits aligned on a
//! byte boundary. Fx. for writing the value 0b101 to bits 1 and 3 the
//! \c ui16Val = 0x0A and the \c ui16Mask = 0x0E. Bits 0 and 5-7 will not be affected
//! by the operation, as the corresponding bits are not set in the
//! \c ui16Mask.
//!
//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be
//! enabled before calling this function.
//!
//! \param ui32Base is the base address of the ADI port.
//! \param ui32Reg is the Least Significant Register in the ADI slave that
//! will be affected by the write operation.
//! \param ui16Mask is the mask defining which of the 8 bit that should be
//! overwritten. The mask must be defined in the lower half of the 16 bits.
//! \param ui16Val is the value to write. The value must be defined in the lower
//! half of the 16 bits.
//!
//! \return None
//!
//! \sa ADI4SetValBit(), ADI16SetValBit()
//
//*****************************************************************************
__STATIC_INLINE void
ADI8SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint16_t ui16Mask,
uint16_t ui16Val)
{
uint32_t ui32RegOffset;
// Check the arguments.
ASSERT(ADIBaseValid(ui32Base));
ASSERT(ui32Reg < ADI_SLAVE_REGS);
ASSERT(!(ui16Val & 0xFF00));
ASSERT(!(ui16Mask & 0xFF00));
// Get the correct address of the first register used for setting bits
// in the ADI slave.
ui32RegOffset = ADI_O_MASK8B + (ui32Reg << 1);
// Set the selected bits.
HWREGH(ui32Base + ui32RegOffset) = (ui16Mask << 8) | ui16Val;
}
//*****************************************************************************
//
//! \brief Set a value on any bits inside an 2 x 8 bit register aligned on a
//! half-word (byte) boundary in the ADI slave.
//!
//! This function allows 2 byte (16 bit) access to the ADI slave registers.
//!
//! Use this function to write any value in the range 0-15 bits aligned on a
//! half-word (byte) boundary. Fx. for writing the value 0b101 to bits 1 and 3 the
//! \c ui32Val = 0x000A and the \c ui32Mask = 0x000E. Bits 0 and 5-15 will not
//! be affected by the operation, as the corresponding bits are not set
//! in the \c ui32Mask.
//!
//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be
//! enabled before calling this function.
//!
//! \param ui32Base is the base address of the ADI port.
//! \param ui32Reg is the Least Significant Register in the ADI slave that
//! will be affected by the write operation.
//! \param ui32Mask is the mask defining which of the 16 bit that should be
//! overwritten. The mask must be defined in the lower half of the 32 bits.
//! \param ui32Val is the value to write. The value must be defined in the lower
//! half of the 32 bits.
//!
//! \return None
//!
//! \sa ADI4SetValBit(), ADI8SetValBit()
//
//*****************************************************************************
__STATIC_INLINE void
ADI16SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask,
uint32_t ui32Val)
{
uint32_t ui32RegOffset;
// Check the arguments.
ASSERT(ADIBaseValid(ui32Base));
ASSERT(ui32Reg < ADI_SLAVE_REGS);
ASSERT(!(ui32Val & 0xFFFF0000));
ASSERT(!(ui32Mask & 0xFFFF0000));
// Get the correct address of the first register used for setting bits
// in the ADI slave.
ui32RegOffset = ADI_O_MASK16B + ((ui32Reg << 1) & 0xFC);
// Set the selected bits.
HWREG(ui32Base + ui32RegOffset) = (ui32Mask << 16) | ui32Val;
}
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __ADI_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

68
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/adi_doc.h
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@ -1,68 +0,0 @@
/******************************************************************************
* Filename: adi_doc.h
* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016)
* Revision: 45971
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//! \addtogroup adi_api
//! @{
//! \section sec_adi Introduction
//! \n
//!
//! \section sec_adi_api API
//!
//! The API functions can be grouped like this:
//!
//! Write:
//! - Direct (all bits):
//! - \ref ADI8RegWrite()
//! - \ref ADI16RegWrite()
//! - \ref ADI32RegWrite()
//! - Set individual bits:
//! - \ref ADI8BitsSet()
//! - \ref ADI16BitsSet()
//! - \ref ADI32BitsSet()
//! - Clear individual bits:
//! - \ref ADI8BitsClear()
//! - \ref ADI16BitsClear()
//! - \ref ADI32BitsClear()
//! - Masked:
//! - \ref ADI4SetValBit()
//! - \ref ADI8SetValBit()
//! - \ref ADI16SetValBit()
//!
//! Read:
//! - \ref ADI8RegRead()
//! - \ref ADI16RegRead()
//! - \ref ADI32RegRead()
//!
//! @}

372
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aes.c
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@ -1,372 +0,0 @@
/******************************************************************************
* Filename: crypto.c
* Revised: 2019-01-25 13:11:50 +0100 (Fri, 25 Jan 2019)
* Revision: 54285
*
* Description: Driver for the aes functions of the crypto module
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "aes.h"
//*****************************************************************************
//
// Handle support for DriverLib in ROM:
// This section will undo prototype renaming made in the header file
//
//*****************************************************************************
#if !defined(DOXYGEN)
#undef AESStartDMAOperation
#define AESStartDMAOperation NOROM_AESStartDMAOperation
#undef AESSetInitializationVector
#define AESSetInitializationVector NOROM_AESSetInitializationVector
#undef AESWriteCCMInitializationVector
#define AESWriteCCMInitializationVector NOROM_AESWriteCCMInitializationVector
#undef AESReadTag
#define AESReadTag NOROM_AESReadTag
#undef AESVerifyTag
#define AESVerifyTag NOROM_AESVerifyTag
#undef AESWriteToKeyStore
#define AESWriteToKeyStore NOROM_AESWriteToKeyStore
#undef AESReadFromKeyStore
#define AESReadFromKeyStore NOROM_AESReadFromKeyStore
#undef AESWaitForIRQFlags
#define AESWaitForIRQFlags NOROM_AESWaitForIRQFlags
#undef AESConfigureCCMCtrl
#define AESConfigureCCMCtrl NOROM_AESConfigureCCMCtrl
#endif
//*****************************************************************************
//
// Load the initialization vector.
//
//*****************************************************************************
void AESSetInitializationVector(const uint32_t *initializationVector)
{
// Write initialization vector to the aes registers
HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = initializationVector[0];
HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = initializationVector[1];
HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = initializationVector[2];
HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = initializationVector[3];
}
//*****************************************************************************
//
// Start a crypto DMA operation.
//
//*****************************************************************************
void AESStartDMAOperation(const uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length)
{
if (channel0Length && channel0Addr) {
// We actually want to perform an operation. Clear any outstanding events.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = CRYPTO_IRQCLR_RESULT_AVAIL_M | CRYPTO_IRQEN_DMA_IN_DONE_M; // This might need AES_IRQEN_DMA_IN_DONE as well
while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M));
// Configure the DMA controller - enable both DMA channels.
HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;
// Base address of the payload data in ext. memory.
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)channel0Addr;
// Payload data length in bytes, equal to the cipher text length.
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = channel0Length;
}
if (channel1Length && channel1Addr) {
// Enable DMA channel 1.
HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1;
// Base address of the output data buffer.
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)channel1Addr;
// Output data length in bytes, equal to the cipher text length.
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = channel1Length;
}
}
//*****************************************************************************
//
// Poll the IRQ status register and return.
//
//*****************************************************************************
uint32_t AESWaitForIRQFlags(uint32_t irqFlags)
{
uint32_t irqTrigger = 0;
// Wait for the DMA operation to complete. Add a delay to make sure we are
// not flooding the bus with requests too much.
do {
CPUdelay(1);
}
while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M |
CRYPTO_IRQSTAT_RESULT_AVAIL_M |
CRYPTO_IRQSTAT_DMA_BUS_ERR_M |
CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M)));
// Save the IRQ trigger source
irqTrigger = HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags;
// Clear IRQ flags
HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = irqTrigger;
return irqTrigger;
}
//*****************************************************************************
//
// Transfer a key from CM3 memory to a key store location.
//
//*****************************************************************************
uint32_t AESWriteToKeyStore(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea)
{
// Check the arguments.
ASSERT((keyStoreArea == AES_KEY_AREA_0) ||
(keyStoreArea == AES_KEY_AREA_1) ||
(keyStoreArea == AES_KEY_AREA_2) ||
(keyStoreArea == AES_KEY_AREA_3) ||
(keyStoreArea == AES_KEY_AREA_4) ||
(keyStoreArea == AES_KEY_AREA_5) ||
(keyStoreArea == AES_KEY_AREA_6) ||
(keyStoreArea == AES_KEY_AREA_7));
ASSERT((aesKeyLength == AES_128_KEY_LENGTH_BYTES) ||
(aesKeyLength == AES_192_KEY_LENGTH_BYTES) ||
(aesKeyLength == AES_256_KEY_LENGTH_BYTES));
uint32_t keySize = 0;
switch (aesKeyLength) {
case AES_128_KEY_LENGTH_BYTES:
keySize = CRYPTO_KEYSIZE_SIZE_128_BIT;
break;
case AES_192_KEY_LENGTH_BYTES:
keySize = CRYPTO_KEYSIZE_SIZE_192_BIT;
break;
case AES_256_KEY_LENGTH_BYTES:
keySize = CRYPTO_KEYSIZE_SIZE_256_BIT;
break;
}
// Clear any previously written key at the keyLocation
AESInvalidateKey(keyStoreArea);
// Disable the external interrupt to stop the interrupt form propagating
// from the module to the System CPU.
IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);
// Enable internal interrupts.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL_M;
HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE_M | CRYPTO_IRQEN_RESULT_AVAIL_M;
// Configure master control module.
HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_KEY_STORE;
// Clear any outstanding events.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | CRYPTO_IRQCLR_RESULT_AVAIL);
// Configure the size of keys contained within the key store
// Do not write to the register if the correct key size is already set.
// Writing to this register causes all current keys to be invalidated.
uint32_t keyStoreKeySize = HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE);
if (keySize != keyStoreKeySize) {
HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) = keySize;
}
// Enable key to write (e.g. Key 0).
HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITEAREA) = 1 << keyStoreArea;
// Total key length in bytes (16 for 1 x 128-bit key and 32 for 1 x 256-bit key).
AESStartDMAOperation(aesKey, aesKeyLength, 0, 0);
// Wait for the DMA operation to complete.
uint32_t irqTrigger = AESWaitForIRQFlags(CRYPTO_IRQCLR_RESULT_AVAIL | CRYPTO_IRQCLR_DMA_IN_DONE | CRYPTO_IRQSTAT_DMA_BUS_ERR | CRYPTO_IRQSTAT_KEY_ST_WR_ERR);
// Re-enable interrupts globally.
IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ);
IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ);
// If we had a bus error or the key is not in the CRYPTO_O_KEYWRITTENAREA, return an error.
if ((irqTrigger & (CRYPTO_IRQSTAT_DMA_BUS_ERR_M | CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M)) || !(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (1 << keyStoreArea))) {
// There was an error in writing to the keyStore.
return AES_KEYSTORE_ERROR;
}
else {
return AES_SUCCESS;
}
}
//*****************************************************************************
//
// Transfer a key from the keyStoreArea to the internal buffer of the module.
//
//*****************************************************************************
uint32_t AESReadFromKeyStore(uint32_t keyStoreArea)
{
// Check the arguments.
ASSERT((keyStoreArea == AES_KEY_AREA_0) ||
(keyStoreArea == AES_KEY_AREA_1) ||
(keyStoreArea == AES_KEY_AREA_2) ||
(keyStoreArea == AES_KEY_AREA_3) ||
(keyStoreArea == AES_KEY_AREA_4) ||
(keyStoreArea == AES_KEY_AREA_5) ||
(keyStoreArea == AES_KEY_AREA_6) ||
(keyStoreArea == AES_KEY_AREA_7));
// Check if there is a valid key in the specified keyStoreArea
if (!(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (1 << keyStoreArea))) {
return AES_KEYSTORE_AREA_INVALID;
}
// Enable keys to read (e.g. Key 0).
HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = keyStoreArea;
// Wait until key is loaded to the AES module.
// We cannot simply poll the IRQ status as only an error is communicated through
// the IRQ status and not the completion of the transfer.
do {
CPUdelay(1);
}
while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY_M));
// Check for keyStore read error.
if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M)) {
return AES_KEYSTORE_ERROR;
}
else {
return AES_SUCCESS;
}
}
//*****************************************************************************
//
// Read the tag after a completed CCM, GCM, or CBC-MAC operation.
//
//*****************************************************************************
uint32_t AESReadTag(uint8_t *tag, uint32_t tagLength)
{
// The intermediate array is used instead of a caller-provided one
// to enable a simple API with no unintuitive alignment or size requirements.
// This is a trade-off of stack-depth vs ease-of-use that came out on the
// ease-of-use side.
uint32_t computedTag[AES_BLOCK_SIZE / sizeof(uint32_t)];
// Wait until the computed tag is ready.
while (!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) & CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M));
// Read computed tag out from the HW registers
// Need to read out all 128 bits in four reads to correctly clear CRYPTO_AESCTL_SAVED_CONTEXT_RDY flag
computedTag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0);
computedTag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1);
computedTag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2);
computedTag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3);
memcpy(tag, computedTag, tagLength);
return AES_SUCCESS;
}
//*****************************************************************************
//
// Verify the provided tag against the computed tag after a completed CCM or
// GCM operation.
//
//*****************************************************************************
uint32_t AESVerifyTag(const uint8_t *tag, uint32_t tagLength)
{
uint32_t resultStatus;
// The intermediate array is allocated on the stack to ensure users do not
// point the tag they provide and the one computed at the same location.
// That would cause memcmp to compare an array against itself. We could add
// a check that verifies that the arrays are not the same. If we did that and
// modified AESReadTag to just copy all 128 bits into a provided array,
// we could save 16 bytes of stack space while making the API much more
// complicated.
uint8_t computedTag[AES_BLOCK_SIZE];
resultStatus = AESReadTag(computedTag, tagLength);
if (resultStatus != AES_SUCCESS) {
return resultStatus;
}
resultStatus = memcmp(computedTag, tag, tagLength);
if (resultStatus != 0) {
return AES_TAG_VERIFICATION_FAILED;
}
return AES_SUCCESS;
}
//*****************************************************************************
//
// Configure the AES module for CCM mode
//
//*****************************************************************************
void AESConfigureCCMCtrl(uint32_t nonceLength, uint32_t macLength, bool encrypt)
{
uint32_t ctrlVal = 0;
ctrlVal = ((15 - nonceLength - 1) << CRYPTO_AESCTL_CCM_L_S);
if ( macLength >= 2 ) {
ctrlVal |= ((( macLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S );
}
ctrlVal |= CRYPTO_AESCTL_CCM |
CRYPTO_AESCTL_CTR |
CRYPTO_AESCTL_SAVE_CONTEXT |
CRYPTO_AESCTL_CTR_WIDTH_128_BIT;
ctrlVal |= encrypt ? CRYPTO_AESCTL_DIR : 0;
AESSetCtrl(ctrlVal);
}
//*****************************************************************************
//
// Configure an IV for CCM mode of operation
//
//*****************************************************************************
void AESWriteCCMInitializationVector(const uint8_t *nonce, uint32_t nonceLength)
{
union {
uint32_t word[4];
uint8_t byte[16];
} initializationVector = {{0}};
initializationVector.byte[0] = 15 - nonceLength - 1;
memcpy(&(initializationVector.byte[1]), nonce, nonceLength);
AESSetInitializationVector(initializationVector.word);
}

843
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aes.h
View file

@ -1,843 +0,0 @@
/******************************************************************************
* Filename: aes.h
* Revised: 2019-01-25 14:45:16 +0100 (Fri, 25 Jan 2019)
* Revision: 54287
*
* Description: AES header file.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup peripheral_group
//! @{
//! \addtogroup aes_api
//! @{
//
//*****************************************************************************
#ifndef __AES_H__
#define __AES_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdbool.h>
#include <stdint.h>
#include <string.h>
#include "../inc/hw_types.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_ints.h"
#include "../inc/hw_crypto.h"
#include "debug.h"
#include "interrupt.h"
#include "cpu.h"
//*****************************************************************************
//
// Support for DriverLib in ROM:
// This section renames all functions that are not "static inline", so that
// calling these functions will default to implementation in flash. At the end
// of this file a second renaming will change the defaults to implementation in
// ROM for available functions.
//
// To force use of the implementation in flash, e.g. for debugging:
// - Globally: Define DRIVERLIB_NOROM at project level
// - Per function: Use prefix "NOROM_" when calling the function
//
//*****************************************************************************
#if !defined(DOXYGEN)
#define AESStartDMAOperation NOROM_AESStartDMAOperation
#define AESSetInitializationVector NOROM_AESSetInitializationVector
#define AESWriteCCMInitializationVector NOROM_AESWriteCCMInitializationVector
#define AESReadTag NOROM_AESReadTag
#define AESVerifyTag NOROM_AESVerifyTag
#define AESWriteToKeyStore NOROM_AESWriteToKeyStore
#define AESReadFromKeyStore NOROM_AESReadFromKeyStore
#define AESWaitForIRQFlags NOROM_AESWaitForIRQFlags
#define AESConfigureCCMCtrl NOROM_AESConfigureCCMCtrl
#endif
//*****************************************************************************
//
// Values that can be passed to AESIntEnable, AESIntDisable, and AESIntClear
// as the intFlags parameter, and returned from AESIntStatus.
// Only AES_DMA_IN_DONE and AES_RESULT_RDY are routed to the NVIC. Check each
// function to see if it supports other interrupt status flags.
//
//*****************************************************************************
#define AES_DMA_IN_DONE CRYPTO_IRQEN_DMA_IN_DONE_M
#define AES_RESULT_RDY CRYPTO_IRQEN_RESULT_AVAIL_M
#define AES_DMA_BUS_ERR CRYPTO_IRQCLR_DMA_BUS_ERR_M
#define AES_KEY_ST_WR_ERR CRYPTO_IRQCLR_KEY_ST_WR_ERR_M
#define AES_KEY_ST_RD_ERR CRYPTO_IRQCLR_KEY_ST_RD_ERR_M
//*****************************************************************************
//
// General constants
//
//*****************************************************************************
// AES module return codes
#define AES_SUCCESS 0
#define AES_KEYSTORE_ERROR 1
#define AES_KEYSTORE_AREA_INVALID 2
#define AES_DMA_BUSY 3
#define AES_DMA_ERROR 4
#define AES_TAG_NOT_READY 5
#define AES_TAG_VERIFICATION_FAILED 6
// Key store module defines
#define AES_IV_LENGTH_BYTES 16
#define AES_TAG_LENGTH_BYTES 16
#define AES_128_KEY_LENGTH_BYTES (128 / 8)
#define AES_192_KEY_LENGTH_BYTES (192 / 8)
#define AES_256_KEY_LENGTH_BYTES (256 / 8)
#define AES_BLOCK_SIZE 16
// DMA status codes
#define AES_DMA_CHANNEL0_ACTIVE CRYPTO_DMASTAT_CH0_ACT_M
#define AES_DMA_CHANNEL1_ACTIVE CRYPTO_DMASTAT_CH1_ACT_M
#define AES_DMA_PORT_ERROR CRYPTO_DMASTAT_PORT_ERR_M
// Crypto module operation types
#define AES_ALGSEL_AES CRYPTO_ALGSEL_AES_M
#define AES_ALGSEL_KEY_STORE CRYPTO_ALGSEL_KEY_STORE_M
#define AES_ALGSEL_TAG CRYPTO_ALGSEL_TAG_M
//*****************************************************************************
//
// For 128-bit keys, all 8 key area locations from 0 to 7 are valid.
// A 256-bit key requires two consecutive Key Area locations. The base key area
// may be odd. Do not attempt to write a 256-bit key to AES_KEY_AREA_7.
//
//*****************************************************************************
#define AES_KEY_AREA_0 0
#define AES_KEY_AREA_1 1
#define AES_KEY_AREA_2 2
#define AES_KEY_AREA_3 3
#define AES_KEY_AREA_4 4
#define AES_KEY_AREA_5 5
#define AES_KEY_AREA_6 6
#define AES_KEY_AREA_7 7
//*****************************************************************************
//
// Defines for the AES-CTR mode counter width
//
//*****************************************************************************
#define AES_CTR_WIDTH_32 0x0
#define AES_CTR_WIDTH_64 0x1
#define AES_CTR_WIDTH_96 0x2
#define AES_CTR_WIDTH_128 0x3
//*****************************************************************************
//
// API Functions and prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Start a crypto DMA operation
//!
//! Enable the crypto DMA channels, configure the channel addresses,
//! and set the length of the data transfer.
//! Setting the length of the data transfer automatically starts the
//! transfer. It is also used by the hardware module as a signal to
//! begin the encryption, decryption, or MAC operation.
//!
//! \param [in] channel0Addr A pointer to the address channel 0 shall use.
//!
//! \param [in] channel0Length Length of the data in bytes to be read from or
//! written to at channel0Addr. Set to 0 to not set up
//! this channel. Permitted ranges are mode dependent
//! and displayed below.
//! - ECB: [16]
//! - CBC: [1, sizeof(RAM)]
//! - CBC-MAC: [1, sizeof(RAM)]
//! - CCM: [1, sizeof(RAM)]
//!
//! \param [out] channel1Addr A pointer to the address channel 1 shall use.
//!
//! \param [in] channel1Length Length of the data in bytes to be read from or
//! written to at channel1Addr. Set to 0 to not set up
//! this channel.Permitted ranges are mode dependent
//! and displayed below.
//! - ECB: [16]
//! - CBC: [1, sizeof(RAM)]
//! - CBC-MAC: [1, sizeof(RAM)]
//! - CCM: [1, sizeof(RAM)]
//!
//! \return None
//
//*****************************************************************************
extern void AESStartDMAOperation(const uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length);
//*****************************************************************************
//
//! \brief Write the initialization vector (IV) to the crypto module.
//!
//! Depending on the mode of operation, the tag must be constructed
//! differently:
//! - CBC: No special care must be taken. Any 128-bit IV
//! (initialization vector) will suffice.
//! - CBC-MAC: IV's must be all 0's.
//! - CCM: Only 12 and 13 byte IV's are permitted. See code
//! below for formatting.
//! \code
//! uint8_t initVectorLength = 12; // Could also be 13
//!
//! union {
//! uint32_t word[4];
//! uint8_t byte[16];
//! } initVector;
//!
//! uint8_t initVectorUnformatted[initVectorLength];
//!
//! // This is the same field length value that is written to the ctrl register
//! initVector.byte[0] = L - 1;
//!
//! memcpy(&initVector.byte[1], initVectorUnformatted, initVectorLength);
//!
//! // Fill the remaining bytes with zeros
//! for (initVectorLength++; initVectorLength < sizeof(initVector.byte); initVectorLength++) {
//! initVector.byte[initVectorLength] = 0;
//! }
//! \endcode
//!
//! \param [in] initializationVector Pointer to an array with four 32-bit elements
//! to be used as initialization vector.
//! Elements of array must be word aligned in memory.
//!
//! \return None
//
//*****************************************************************************
extern void AESSetInitializationVector(const uint32_t *initializationVector);
//*****************************************************************************
//
//! \brief Generate and load the initialization vector for a CCM operation.
//!
//!
//! \param [in] nonce Pointer to a nonce of length \c nonceLength.
//!
//! \param [in] nonceLength Number of bytes to copy from \c nonce when creating
//! the CCM IV. The L-value is also derived from it.
//!
//! \return None
//
//*****************************************************************************
extern void AESWriteCCMInitializationVector(const uint8_t *nonce, uint32_t nonceLength);
//*****************************************************************************
//
//! \brief Read the tag out from the crypto module.
//!
//! This function copies the \c tagLength bytes from the tag calculated by the
//! crypto module in CCM, GCM, or CBC-MAC mode to \c tag.
//!
//! \param [out] tag Pointer to an array of \c tagLength bytes.
//!
//! \param [in] tagLength Number of bytes to copy to \c tag.
//!
//! \return Returns a status code depending on the result of the transfer.
//! - \ref AES_TAG_NOT_READY if the tag is not ready yet
//! - \ref AES_SUCCESS otherwise
//
//*****************************************************************************
extern uint32_t AESReadTag(uint8_t *tag, uint32_t tagLength);
//*****************************************************************************
//
//! \brief Verifies the provided \c tag against calculated one
//!
//! This function compares the provided tag against the tag calculated by the
//! crypto module during the last CCM, GCM, or CBC-MAC
//!
//! This function copies the \c tagLength bytes from the tag calculated by the
//! crypto module in CCM, GCM, or CBC-MAC mode to \c tag.
//!
//! \param [in] tag Pointer to an array of \c tagLength bytes.
//!
//! \param [in] tagLength Number of bytes to compare.
//!
//! \return Returns a status code depending on the result of the transfer.
//! - \ref AES_TAG_VERIFICATION_FAILED if the verification failed
//! - \ref AES_SUCCESS otherwise
//
//*****************************************************************************
extern uint32_t AESVerifyTag(const uint8_t *tag, uint32_t tagLength);
//*****************************************************************************
//
//! \brief Transfer a key from main memory to a key area within the key store.
//!
//! The crypto DMA transfers the key and function does not return until
//! the operation completes.
//! The keyStore can only contain valid keys of one \c aesKeyLength at
//! any one point in time. The keyStore cannot contain both 128-bit and
//! 256-bit keys simultaneously. When a key of a different \c aesKeyLength
//! from the previous \c aesKeyLength is loaded, all previous keys are
//! invalidated.
//!
//! \param [in] aesKey Pointer to key. Does not need to be word-aligned.
//!
//! \param [in] aesKeyLength The key size in bytes. Currently, 128-bit, 192-bit,
//! and 256-bit keys are supported.
//! - \ref AES_128_KEY_LENGTH_BYTES
//! - \ref AES_192_KEY_LENGTH_BYTES
//! - \ref AES_256_KEY_LENGTH_BYTES
//!
//! \param [in] keyStoreArea The key store area to transfer the key to.
//! When using 128-bit keys, only the specified key store
//! area will be occupied.
//! When using 256-bit or 192-bit keys, two consecutive key areas
//! are used to store the key.
//! - \ref AES_KEY_AREA_0
//! - \ref AES_KEY_AREA_1
//! - \ref AES_KEY_AREA_2
//! - \ref AES_KEY_AREA_3
//! - \ref AES_KEY_AREA_4
//! - \ref AES_KEY_AREA_5
//! - \ref AES_KEY_AREA_6
//! - \ref AES_KEY_AREA_7
//!
//! When using 256-bit or 192-bit keys, the 8 \c keyStoreArea's are
//! split into four sets of two. Selecting any \c keyStoreArea automatically
//! occupies the second \c keyStoreArea of the tuples below:
//!
//! - (\ref AES_KEY_AREA_0, \ref AES_KEY_AREA_1)
//! - (\ref AES_KEY_AREA_2, \ref AES_KEY_AREA_3)
//! - (\ref AES_KEY_AREA_4, \ref AES_KEY_AREA_5)
//! - (\ref AES_KEY_AREA_6, \ref AES_KEY_AREA_7)
//!
//! For example: if \c keyStoreArea == \ref AES_KEY_AREA_2,
//! both \ref AES_KEY_AREA_2 and \ref AES_KEY_AREA_3 are occupied.
//! If \c keyStoreArea == \ref AES_KEY_AREA_5, both \ref AES_KEY_AREA_4 and \ref AES_KEY_AREA_5 are occupied.
//!
//! \return Returns a status code depending on the result of the transfer.
//! If there was an error in the read process itself, an error is
//! returned.
//! Otherwise, a success code is returned.
//! - \ref AES_KEYSTORE_ERROR
//! - \ref AES_SUCCESS
//!
//! \sa AESReadFromKeyStore
//
//*****************************************************************************
extern uint32_t AESWriteToKeyStore(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea);
//*****************************************************************************
//
//! \brief Transfer a key from key store area to the internal buffers within
//! the hardware module.
//!
//! The function polls until the transfer is complete.
//!
//! \param [in] keyStoreArea The key store area to transfer the key from. When using
//! 256-bit keys, either of the occupied key areas may be
//! specified to load the key. There is no need to specify
//! the length of the key here as the key store keeps track
//! of how long a key associated with any valid key area is
//! and where is starts.
//! - \ref AES_KEY_AREA_0
//! - \ref AES_KEY_AREA_1
//! - \ref AES_KEY_AREA_2
//! - \ref AES_KEY_AREA_3
//! - \ref AES_KEY_AREA_4
//! - \ref AES_KEY_AREA_5
//! - \ref AES_KEY_AREA_6
//! - \ref AES_KEY_AREA_7
//!
//! \return Returns a status code depending on the result of the transfer.
//! When specifying a \c keyStoreArea value without a valid key in it an
//! error is returned.
//! If there was an error in the read process itself, an error is
//! returned.
//! Otherwise, a success code is returned.
//! - \ref AES_KEYSTORE_AREA_INVALID
//! - \ref AES_KEYSTORE_ERROR
//! - \ref AES_SUCCESS
//!
//! \sa AESWriteToKeyStore
//
//*****************************************************************************
extern uint32_t AESReadFromKeyStore(uint32_t keyStoreArea);
//*****************************************************************************
//
//! \brief Poll the interrupt status register and clear when done.
//!
//! This function polls until one of the bits in the \c irqFlags is
//! asserted. Only \ref AES_DMA_IN_DONE and \ref AES_RESULT_RDY can actually
//! trigger the interrupt line. That means that one of those should
//! always be included in \c irqFlags and will always be returned together
//! with any error codes.
//!
//! \param [in] irqFlags IRQ flags to poll and mask that the status register will be
//! masked with. May consist of any bitwise OR of the flags
//! below that includes at least one of
//! \ref AES_DMA_IN_DONE or \ref AES_RESULT_RDY :
//! - \ref AES_DMA_IN_DONE
//! - \ref AES_RESULT_RDY
//! - \ref AES_DMA_BUS_ERR
//! - \ref AES_KEY_ST_WR_ERR
//! - \ref AES_KEY_ST_RD_ERR
//!
//! \return Returns the IRQ status register masked with \c irqFlags. May be any
//! bitwise OR of the following masks:
//! - \ref AES_DMA_IN_DONE
//! - \ref AES_RESULT_RDY
//! - \ref AES_DMA_BUS_ERR
//! - \ref AES_KEY_ST_WR_ERR
//! - \ref AES_KEY_ST_RD_ERR
//
//*****************************************************************************
extern uint32_t AESWaitForIRQFlags(uint32_t irqFlags);
//*****************************************************************************
//
//! \brief Configure AES engine for CCM operation.
//!
//! \param [in] nonceLength Length of the nonce. Must be <= 14.
//!
//! \param [in] macLength Length of the MAC. Must be <= 16.
//!
//! \param [in] encrypt Whether to set up an encrypt or decrypt operation.
//! - true: encrypt
//! - false: decrypt
//!
//! \return None
//
//*****************************************************************************
extern void AESConfigureCCMCtrl(uint32_t nonceLength, uint32_t macLength, bool encrypt);
//*****************************************************************************
//
//! \brief Invalidate a key in the key store
//!
//! \param [in] keyStoreArea is the entry in the key store to invalidate. This
//! permanently deletes the key from the key store.
//! - \ref AES_KEY_AREA_0
//! - \ref AES_KEY_AREA_1
//! - \ref AES_KEY_AREA_2
//! - \ref AES_KEY_AREA_3
//! - \ref AES_KEY_AREA_4
//! - \ref AES_KEY_AREA_5
//! - \ref AES_KEY_AREA_6
//! - \ref AES_KEY_AREA_7
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void AESInvalidateKey(uint32_t keyStoreArea)
{
ASSERT((keyStoreArea == AES_KEY_AREA_0) ||
(keyStoreArea == AES_KEY_AREA_1) ||
(keyStoreArea == AES_KEY_AREA_2) ||
(keyStoreArea == AES_KEY_AREA_3) ||
(keyStoreArea == AES_KEY_AREA_4) ||
(keyStoreArea == AES_KEY_AREA_5) ||
(keyStoreArea == AES_KEY_AREA_6) ||
(keyStoreArea == AES_KEY_AREA_7));
// Clear any previously written key at the key location
HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) = (0x00000001 << keyStoreArea);
}
//*****************************************************************************
//
//! \brief Select type of operation
//!
//! \param [in] algorithm Flags that specify which type of operation the crypto
//! module shall perform. The flags are mutually exclusive.
//! - 0 : Reset the module
//! - \ref AES_ALGSEL_AES
//! - \ref AES_ALGSEL_TAG
//! - \ref AES_ALGSEL_KEY_STORE
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void AESSelectAlgorithm(uint32_t algorithm)
{
ASSERT((algorithm == AES_ALGSEL_AES) ||
(algorithm == AES_ALGSEL_AES | AES_ALGSEL_TAG) ||
(algorithm == AES_ALGSEL_KEY_STORE));
HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = algorithm;
}
//*****************************************************************************
//
//! \brief Set up the next crypto module operation.
//!
//! The function uses a bitwise OR of the fields within the CRYPTO_O_AESCTL
//! register. The relevant field names have the format:
//! - CRYPTO_AESCTL_[field name]
//!
//! \param [in] ctrlMask Specifies which register fields shall be set.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void AESSetCtrl(uint32_t ctrlMask)
{
HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ctrlMask;
}
//*****************************************************************************
//
//! \brief Specify length of the crypto operation.
//!
//! Despite specifying it here, the crypto DMA must still be
//! set up with the correct data length.
//!
//! \param [in] length Data length in bytes. If this
//! value is set to 0, only authentication of the AAD is
//! performed in CCM-mode and AESWriteAuthLength() must be set to
//! >0.
//! Range depends on the mode:
//! - ECB: [16]
//! - CBC: [1, sizeof(RAM)]
//! - CBC-MAC: [1, sizeof(RAM)]
//! - CCM: [0, sizeof(RAM)]
//!
//! \return None
//!
//! \sa AESWriteAuthLength
//
//*****************************************************************************
__STATIC_INLINE void AESSetDataLength(uint32_t length)
{
HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = length;
HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0;
}
//*****************************************************************************
//
//! \brief Specify the length of the additional authentication data (AAD).
//!
//! Despite specifying it here, the crypto DMA must still be set up with
//! the correct AAD length.
//!
//! \param [in] length Specifies how long the AAD is in a CCM operation. In CCM mode,
//! set this to 0 if no AAD is required. If set to 0,
//! AESWriteDataLength() must be set to >0.
//! Range depends on the mode:
//! - ECB: Do not call.
//! - CBC: [0]
//! - CBC-MAC: [0]
//! - CCM: [0, sizeof(RAM)]
//!
//! \return None
//!
//! \sa AESWriteDataLength
//
//*****************************************************************************
__STATIC_INLINE void AESSetAuthLength(uint32_t length)
{
HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = length;
}
//*****************************************************************************
//
//! \brief Reset the accelerator and cancel ongoing operations
//!
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void AESReset(void)
{
HWREG(CRYPTO_BASE + CRYPTO_O_SWRESET) = 0x00000001;
}
//*****************************************************************************
//
//! \brief Enable individual crypto interrupt sources.
//!
//! This function enables the indicated crypto interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt.
//! Disabled sources have no effect on the processor.
//!
//! \param [in] intFlags is the bitwise OR of the interrupt sources to be enabled.
//! - \ref AES_DMA_IN_DONE
//! - \ref AES_RESULT_RDY
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void AESIntEnable(uint32_t intFlags)
{
// Check the arguments.
ASSERT((intFlags & AES_DMA_IN_DONE) ||
(intFlags & AES_RESULT_RDY));
// Using level interrupt.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL_M;
// Enable the specified interrupts.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= intFlags;
}
//*****************************************************************************
//
//! \brief Disable individual crypto interrupt sources.
//!
//! This function disables the indicated crypto interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt.
//! Disabled sources have no effect on the processor.
//!
//! \param [in] intFlags is the bitwise OR of the interrupt sources to be enabled.
//! - \ref AES_DMA_IN_DONE
//! - \ref AES_RESULT_RDY
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void AESIntDisable(uint32_t intFlags)
{
// Check the arguments.
ASSERT((intFlags & AES_DMA_IN_DONE) ||
(intFlags & AES_RESULT_RDY));
// Disable the specified interrupts.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~intFlags;
}
//*****************************************************************************
//
//! \brief Get the current masked interrupt status.
//!
//! This function returns the masked interrupt status of the crypto module.
//!
//! \return Returns the status of the masked lines when enabled:
//! - \ref AES_DMA_IN_DONE
//! - \ref AES_RESULT_RDY
//
//*****************************************************************************
__STATIC_INLINE uint32_t AESIntStatusMasked(void)
{
uint32_t mask;
// Return the masked interrupt status
mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN);
return(mask & HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT));
}
//*****************************************************************************
//
//! \brief Get the current raw interrupt status.
//!
//! This function returns the raw interrupt status of the crypto module.
//! It returns both the status of the lines routed to the NVIC as well as the
//! error flags.
//!
//! \return Returns the raw interrupt status:
//! - \ref AES_DMA_IN_DONE
//! - \ref AES_RESULT_RDY
//! - \ref AES_DMA_BUS_ERR
//! - \ref AES_KEY_ST_WR_ERR
//! - \ref AES_KEY_ST_RD_ERR
//
//*****************************************************************************
__STATIC_INLINE uint32_t AESIntStatusRaw(void)
{
// Return either the raw interrupt status
return(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT));
}
//*****************************************************************************
//
//! \brief Clear crypto interrupt sources.
//!
//! The specified crypto interrupt sources are cleared, so that they no longer
//! assert. This function must be called in the interrupt handler to keep the
//! interrupt from being recognized again immediately upon exit.
//!
//! \note Due to write buffers and synchronizers in the system it may take several
//! clock cycles from a register write clearing an event in the module until the
//! event is actually cleared in the NVIC of the system CPU. It is recommended to
//! clear the event source early in the interrupt service routine (ISR) to allow
//! the event clear to propagate to the NVIC before returning from the ISR.
//!
//! \param [in] intFlags is a bit mask of the interrupt sources to be cleared.
//! - \ref AES_DMA_IN_DONE
//! - \ref AES_RESULT_RDY
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void AESIntClear(uint32_t intFlags)
{
// Check the arguments.
ASSERT((intFlags & AES_DMA_IN_DONE) ||
(intFlags & AES_RESULT_RDY));
// Clear the requested interrupt sources,
HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = intFlags;
}
//*****************************************************************************
//
//! \brief Register an interrupt handler for a crypto interrupt.
//!
//! This function does the actual registering of the interrupt handler. This
//! function enables the global interrupt in the interrupt controller; specific
//! crypto interrupts must be enabled via \ref AESIntEnable(). It is the interrupt
//! handler's responsibility to clear the interrupt source.
//!
//! \param handlerFxn is a pointer to the function to be called when the
//! crypto interrupt occurs.
//!
//! \return None
//!
//! \sa \ref IntRegister() for important information about registering interrupt
//! handlers.
//
//*****************************************************************************
__STATIC_INLINE void AESIntRegister(void (*handlerFxn)(void))
{
// Register the interrupt handler.
IntRegister(INT_CRYPTO_RESULT_AVAIL_IRQ, handlerFxn);
// Enable the crypto interrupt.
IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ);
}
//*****************************************************************************
//
//! \brief Unregister an interrupt handler for a crypto interrupt.
//!
//! This function does the actual unregistering of the interrupt handler. It
//! clears the handler called when a crypto interrupt occurs. This
//! function also masks off the interrupt in the interrupt controller so that
//! the interrupt handler no longer is called.
//!
//! \return None
//!
//! \sa \ref IntRegister() for important information about registering interrupt
//! handlers.
//
//*****************************************************************************
__STATIC_INLINE void AESIntUnregister(void)
{
//
// Disable the interrupt.
//
IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_CRYPTO_RESULT_AVAIL_IRQ);
}
//*****************************************************************************
//
// Support for DriverLib in ROM:
// Redirect to implementation in ROM when available.
//
//*****************************************************************************
#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
#include "../driverlib/rom.h"
#ifdef ROM_AESStartDMAOperation
#undef AESStartDMAOperation
#define AESStartDMAOperation ROM_AESStartDMAOperation
#endif
#ifdef ROM_AESSetInitializationVector
#undef AESSetInitializationVector
#define AESSetInitializationVector ROM_AESSetInitializationVector
#endif
#ifdef ROM_AESWriteCCMInitializationVector
#undef AESWriteCCMInitializationVector
#define AESWriteCCMInitializationVector ROM_AESWriteCCMInitializationVector
#endif
#ifdef ROM_AESReadTag
#undef AESReadTag
#define AESReadTag ROM_AESReadTag
#endif
#ifdef ROM_AESVerifyTag
#undef AESVerifyTag
#define AESVerifyTag ROM_AESVerifyTag
#endif
#ifdef ROM_AESWriteToKeyStore
#undef AESWriteToKeyStore
#define AESWriteToKeyStore ROM_AESWriteToKeyStore
#endif
#ifdef ROM_AESReadFromKeyStore
#undef AESReadFromKeyStore
#define AESReadFromKeyStore ROM_AESReadFromKeyStore
#endif
#ifdef ROM_AESWaitForIRQFlags
#undef AESWaitForIRQFlags
#define AESWaitForIRQFlags ROM_AESWaitForIRQFlags
#endif
#ifdef ROM_AESConfigureCCMCtrl
#undef AESConfigureCCMCtrl
#define AESConfigureCCMCtrl ROM_AESConfigureCCMCtrl
#endif
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __AES_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

66
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/******************************************************************************
* Filename: aes_doc.h
* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017)
* Revision: 49096
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//! \addtogroup aes_api
//! @{
//! \section sec_aes Introduction
//!
//! The AES (advanced encryption standard) API provides access to the AES and key
//! store functionality of the crypto core. The SHA2 accelerator is also
//! contained within the crypto core. Hence, only one of SHA2 and AES may be
//! used at the same time.
//! This module offers hardware acceleration for several protocols using the
//! AES block cypher. The protocols below are supported by the hardware. The
//! driverlib documentation only explicitly references the most commonly used ones.
//! - ECB
//! - CBC
//! - CCM
//! - CBC-MAC
//! - GCM
//!
//! The key store is a section of crypto memory that is only accessible to the crypto module
//! and may be written to by the application via the crypto DMA. It is not possible to
//! read from the key store to main memory. Thereby, it is not possible to
//! compromise the key should the application be hacked if the original key in main
//! memory was overwritten already.
//!
//! The crypto core does not have retention and all configuration settings and
//! keys in the keystore are lost when going into standby or shutdown.
//! The typical security advantages a key store offers are not available in these
//! low power modes as the key must be saved in regular memory to reload
//! it after going into standby or shutdown.
//! Consequently, the keystore primarily serves as an interface to the AES accelerator.
//!
//! @}

80
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/******************************************************************************
* Filename: aon_batmon.c
* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016)
* Revision: 47343
*
* Description: Driver for the AON Battery and Temperature Monitor
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "aon_batmon.h"
#include "../inc/hw_fcfg1.h"
//*****************************************************************************
//
// Handle support for DriverLib in ROM:
// This section will undo prototype renaming made in the header file
//
//*****************************************************************************
#if !defined(DOXYGEN)
#undef AONBatMonTemperatureGetDegC
#define AONBatMonTemperatureGetDegC NOROM_AONBatMonTemperatureGetDegC
#endif
//*****************************************************************************
//
// AONBatMonTemperatureGetDegC()
// Returns sign extended temperature in Deg C (-256 .. +255)
//
//*****************************************************************************
int32_t
AONBatMonTemperatureGetDegC( void )
{
int32_t signedTemp ; // Signed extended temperature with 8 fractional bits
int32_t tempCorrection ; // Voltage dependent temp correction with 8 fractional bits
int8_t voltageSlope ; // Signed byte value representing the TEMP slope with battery voltage, in degrees C/V, with 4 fractional bits.
// Shift left then right to sign extend the BATMON_TEMP field
signedTemp = ((((int32_t)HWREG( AON_BATMON_BASE + AON_BATMON_O_TEMP ))
<< ( 32 - AON_BATMON_TEMP_INT_W - AON_BATMON_TEMP_INT_S ))
>> ( 32 - AON_BATMON_TEMP_INT_W - AON_BATMON_TEMP_INT_S ));
// Typecasting voltageSlope to int8_t prior to assignment in order to make sure sign extension works properly
// Using byte read (HWREGB) in order to make more efficient code since voltageSlope is assigned to bits[7:0] of FCFG1_O_MISC_TRIM
voltageSlope = ((int8_t)HWREGB( FCFG1_BASE + FCFG1_O_MISC_TRIM ));
tempCorrection = (( voltageSlope * (((int32_t)HWREG( AON_BATMON_BASE + AON_BATMON_O_BAT )) - 0x300 )) >> 4 );
return ((( signedTemp - tempCorrection ) + 0x80 ) >> 8 );
}
// See aon_batmon.h for implementation of remaining functions

306
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@ -1,306 +0,0 @@
/******************************************************************************
* Filename: aon_batmon.h
* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016)
* Revision: 47343
*
* Description: Defines and prototypes for the AON Battery and Temperature
* Monitor
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup aon_group
//! @{
//! \addtogroup aonbatmon_api
//! @{
//
//*****************************************************************************
#ifndef __AON_BATMON_H__
#define __AON_BATMON_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdbool.h>
#include <stdint.h>
#include "../inc/hw_types.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_aon_batmon.h"
#include "debug.h"
//*****************************************************************************
//
// Support for DriverLib in ROM:
// This section renames all functions that are not "static inline", so that
// calling these functions will default to implementation in flash. At the end
// of this file a second renaming will change the defaults to implementation in
// ROM for available functions.
//
// To force use of the implementation in flash, e.g. for debugging:
// - Globally: Define DRIVERLIB_NOROM at project level
// - Per function: Use prefix "NOROM_" when calling the function
//
//*****************************************************************************
#if !defined(DOXYGEN)
#define AONBatMonTemperatureGetDegC NOROM_AONBatMonTemperatureGetDegC
#endif
//*****************************************************************************
//
// API Functions and prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Enable the temperature and battery monitoring.
//!
//! This function will enable the measurements of the temperature and the
//! battery voltage.
//!
//! To speed up the measurement of the levels the measurement can be enabled
//! before configuring the battery and temperature settings. When all of the
//! AON_BATMON registers are configured, the calculation of the voltage and
//! temperature values can be enabled (the measurement will now take
//! effect/propagate to other blocks).
//!
//! It is possible to enable both at the same time, after the AON_BATMON
//! registers are configured, but then the first values will be ready at a
//! later point compared to the scenario above.
//!
//! \note Temperature and battery voltage measurements are not done in
//! parallel. The measurement cycle is controlled by a hardware Finite State
//! Machine. First the temperature and then the battery voltage each taking
//! one cycle to complete. However, if the comparator measuring the battery
//! voltage detects a change on the reference value, a new measurement of the
//! battery voltage only is performed immediately after. This has no impact on
//! the cycle count.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
AONBatMonEnable(void)
{
// Enable the measurements.
HWREG(AON_BATMON_BASE + AON_BATMON_O_CTL) =
AON_BATMON_CTL_CALC_EN |
AON_BATMON_CTL_MEAS_EN;
}
//*****************************************************************************
//
//! \brief Disable the temperature and battery monitoring.
//!
//! This function will disable the measurements of the temperature and the
//! battery voltage.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
AONBatMonDisable(void)
{
// Disable the measurements.
HWREG(AON_BATMON_BASE + AON_BATMON_O_CTL) = 0;
}
//*****************************************************************************
//
//! \brief Get the current temperature measurement as a signed value in Deg Celsius.
//!
//! This function returns an calibrated and rounded value in degree Celsius.
//! The temperature measurements are updated every cycle.
//!
//! \note The temperature drifts slightly depending on the battery voltage.
//! This function compensates for this drift and returns a calibrated temperature.
//!
//! \note Use the function AONBatMonNewTempMeasureReady() to test for a new measurement.
//!
//! \return Returns signed integer part of temperature in Deg C (-256 .. +255)
//!
//! \sa AONBatMonNewTempMeasureReady()
//
//*****************************************************************************
extern int32_t AONBatMonTemperatureGetDegC( void );
//*****************************************************************************
//
//! \brief Get the battery monitor measurement.
//!
//! This function will return the current battery monitor measurement.
//! The battery voltage measurements are updated every cycle.
//!
//! \note The returned value is NOT sign-extended!
//!
//! \note Use the function \ref AONBatMonNewBatteryMeasureReady() to test for
//! a change in measurement.
//!
//! \return Returns the current battery monitor value of the battery voltage
//! measurement in a <int.frac> format size <3.8> in units of volt.
//!
//! \sa AONBatMonNewBatteryMeasureReady()
//
//*****************************************************************************
__STATIC_INLINE uint32_t
AONBatMonBatteryVoltageGet(void)
{
uint32_t ui32CurrentBattery;
ui32CurrentBattery = HWREG(AON_BATMON_BASE + AON_BATMON_O_BAT);
// Return the current battery voltage measurement.
return (ui32CurrentBattery >> AON_BATMON_BAT_FRAC_S);
}
//*****************************************************************************
//
//! \brief Check if battery monitor measurement has changed.
//!
//! This function checks if a new battery monitor value is available. If the
//! measurement value has \b changed since last clear the function returns \c true.
//!
//! If the measurement has changed the function will automatically clear the
//! status bit.
//!
//! \note It is always possible to read out the current value of the
//! battery level using AONBatMonBatteryVoltageGet() but this function can be
//! used to check if the measurement has changed.
//!
//! \return Returns \c true if the measurement value has changed and \c false
//! otherwise.
//!
//! \sa AONBatMonNewTempMeasureReady(), AONBatMonBatteryVoltageGet()
//
//*****************************************************************************
__STATIC_INLINE bool
AONBatMonNewBatteryMeasureReady(void)
{
bool bStatus;
// Check the status bit.
bStatus = HWREG(AON_BATMON_BASE + AON_BATMON_O_BATUPD) &
AON_BATMON_BATUPD_STAT ? true : false;
// Clear status bit if set.
if(bStatus)
{
HWREG(AON_BATMON_BASE + AON_BATMON_O_BATUPD) = 1;
}
// Return status.
return (bStatus);
}
//*****************************************************************************
//
//! \brief Check if temperature monitor measurement has changed.
//!
//! This function checks if a new temperature value is available. If the
//! measurement value has \b changed since last clear the function returns \c true.
//!
//! If the measurement has changed the function will automatically clear the
//! status bit.
//!
//! \note It is always possible to read out the current value of the
//! temperature using \ref AONBatMonTemperatureGetDegC()
//! but this function can be used to check if the measurement has changed.
//!
//! \return Returns \c true if the measurement value has changed and \c false
//! otherwise.
//!
//! \sa AONBatMonNewBatteryMeasureReady(), AONBatMonTemperatureGetDegC()
//
//*****************************************************************************
__STATIC_INLINE bool
AONBatMonNewTempMeasureReady(void)
{
bool bStatus;
// Check the status bit.
bStatus = HWREG(AON_BATMON_BASE + AON_BATMON_O_TEMPUPD) &
AON_BATMON_TEMPUPD_STAT ? true : false;
// Clear status bit if set.
if(bStatus)
{
HWREG(AON_BATMON_BASE + AON_BATMON_O_TEMPUPD) = 1;
}
// Return status.
return (bStatus);
}
//*****************************************************************************
//
// Support for DriverLib in ROM:
// Redirect to implementation in ROM when available.
//
//*****************************************************************************
#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
#include "../driverlib/rom.h"
#ifdef ROM_AONBatMonTemperatureGetDegC
#undef AONBatMonTemperatureGetDegC
#define AONBatMonTemperatureGetDegC ROM_AONBatMonTemperatureGetDegC
#endif
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __AON_BATMON_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

180
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/******************************************************************************
* Filename: aon_event.c
* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017)
* Revision: 49096
*
* Description: Driver for the AON Event fabric.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "aon_event.h"
//*****************************************************************************
//
// Handle support for DriverLib in ROM:
// This section will undo prototype renaming made in the header file
//
//*****************************************************************************
#if !defined(DOXYGEN)
#undef AONEventMcuWakeUpSet
#define AONEventMcuWakeUpSet NOROM_AONEventMcuWakeUpSet
#undef AONEventMcuWakeUpGet
#define AONEventMcuWakeUpGet NOROM_AONEventMcuWakeUpGet
#undef AONEventMcuSet
#define AONEventMcuSet NOROM_AONEventMcuSet
#undef AONEventMcuGet
#define AONEventMcuGet NOROM_AONEventMcuGet
#endif
//*****************************************************************************
//
// Select event source for the specified MCU wakeup programmable event
//
//*****************************************************************************
void
AONEventMcuWakeUpSet(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc)
{
uint32_t ui32Shift ;
uint32_t ui32Mask ;
uint32_t ui32RegAdr ;
// Check the arguments.
ASSERT(( ui32MCUWUEvent >= AON_EVENT_MCU_WU0 ) && ( ui32MCUWUEvent <= AON_EVENT_MCU_WU7 ))
ASSERT( ui32EventSrc <= AON_EVENT_NONE );
ui32Shift = (( ui32MCUWUEvent & 3 ) << 3 );
ui32Mask = ( 0x3F << ui32Shift );
ui32RegAdr = ( AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL );
if ( ui32MCUWUEvent > 3 ) {
ui32RegAdr += 4;
}
HWREG( ui32RegAdr ) = ( HWREG( ui32RegAdr ) & ( ~ui32Mask )) | ( ui32EventSrc << ui32Shift );
}
//*****************************************************************************
//
// Get event source for the specified MCU wakeup programmable event
//
//*****************************************************************************
uint32_t
AONEventMcuWakeUpGet(uint32_t ui32MCUWUEvent)
{
uint32_t ui32Shift ;
uint32_t ui32RegAdr ;
// Check the arguments.
ASSERT(( ui32MCUWUEvent >= AON_EVENT_MCU_WU0 ) && ( ui32MCUWUEvent <= AON_EVENT_MCU_WU7 ))
ui32Shift = (( ui32MCUWUEvent & 3 ) << 3 );
ui32RegAdr = ( AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL );
if ( ui32MCUWUEvent > 3 ) {
ui32RegAdr += 4;
}
return (( HWREG( ui32RegAdr ) >> ui32Shift ) & 0x3F );
}
//*****************************************************************************
//
// Select event source for the specified programmable event forwarded to the
// MCU event fabric
//
//*****************************************************************************
void
AONEventMcuSet(uint32_t ui32MCUEvent, uint32_t ui32EventSrc)
{
uint32_t ui32Ctrl;
// Check the arguments.
ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) ||
(ui32MCUEvent == AON_EVENT_MCU_EVENT1) ||
(ui32MCUEvent == AON_EVENT_MCU_EVENT2));
ASSERT(ui32EventSrc <= AON_EVENT_NONE);
ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL);
if(ui32MCUEvent == AON_EVENT_MCU_EVENT0)
{
ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M);
ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S;
}
else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1)
{
ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M);
ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S;
}
else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2)
{
ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M);
ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S;
}
HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL) = ui32Ctrl;
}
//*****************************************************************************
//
// Get source for the specified programmable event forwarded to the MCU event
// fabric.
//
//*****************************************************************************
uint32_t
AONEventMcuGet(uint32_t ui32MCUEvent)
{
uint32_t ui32EventSrc;
// Check the arguments.
ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) ||
(ui32MCUEvent == AON_EVENT_MCU_EVENT1) ||
(ui32MCUEvent == AON_EVENT_MCU_EVENT2));
ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL);
if(ui32MCUEvent == AON_EVENT_MCU_EVENT0)
{
return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M) >>
AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S);
}
else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1)
{
return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M) >>
AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S);
}
else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2)
{
return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M) >>
AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S);
}
// Should never get to this statement, but suppress warning.
ASSERT(0);
return(0);
}

564
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event.h
View file

@ -1,564 +0,0 @@
/******************************************************************************
* Filename: aon_event.h
* Revised: 2017-08-09 16:56:05 +0200 (Wed, 09 Aug 2017)
* Revision: 49506
*
* Description: Defines and prototypes for the AON Event fabric.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup aon_group
//! @{
//! \addtogroup aonevent_api
//! @{
//
//*****************************************************************************
#ifndef __AON_EVENT_H__
#define __AON_EVENT_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdbool.h>
#include <stdint.h>
#include "../inc/hw_types.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_aon_event.h"
#include "debug.h"
//*****************************************************************************
//
// Support for DriverLib in ROM:
// This section renames all functions that are not "static inline", so that
// calling these functions will default to implementation in flash. At the end
// of this file a second renaming will change the defaults to implementation in
// ROM for available functions.
//
// To force use of the implementation in flash, e.g. for debugging:
// - Globally: Define DRIVERLIB_NOROM at project level
// - Per function: Use prefix "NOROM_" when calling the function
//
//*****************************************************************************
#if !defined(DOXYGEN)
#define AONEventMcuWakeUpSet NOROM_AONEventMcuWakeUpSet
#define AONEventMcuWakeUpGet NOROM_AONEventMcuWakeUpGet
#define AONEventMcuSet NOROM_AONEventMcuSet
#define AONEventMcuGet NOROM_AONEventMcuGet
#endif
//*****************************************************************************
//
// Event sources for the event AON fabric.
// Note: Events are level-triggered active high
//
//*****************************************************************************
#define AON_EVENT_IOEV_MCU_WU 0 // Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU
#define AON_EVENT_AUX_TIMER2_EV0 1 // Event 0 from AUX Timer2
#define AON_EVENT_AUX_TIMER2_EV1 2 // Event 1 from AUX Timer2
#define AON_EVENT_AUX_TIMER2_EV2 3 // Event 2 from AUX Timer2
#define AON_EVENT_AUX_TIMER2_EV3 4 // Event 3 from AUX Timer2
#define AON_EVENT_BATMON_BATT_UL 5 // BATMON event: Battery level above upper limit
#define AON_EVENT_BATMON_BATT_LL 6 // BATMON event: Battery level below lower limit
#define AON_EVENT_BATMON_TEMP_UL 7 // BATMON event: Temperature level above upper limit
#define AON_EVENT_BATMON_TEMP_LL 8 // BATMON event: Temperature level below lower limit
#define AON_EVENT_BATMON_COMBINED 9 // Combined event from BATMON
#define AON_EVENT_IO 32 // Edge detect on any DIO. Edge detect is enabled and configured in IOC.
// Event ID 33 is reserved for future use
// Event ID 34 is reserved for future use
#define AON_EVENT_RTC_CH0 35 // RTC channel 0
#define AON_EVENT_RTC_CH1 36 // RTC channel 1
#define AON_EVENT_RTC_CH2 37 // RTC channel 2
#define AON_EVENT_RTC_CH0_DLY 38 // RTC channel 0 - delayed event
#define AON_EVENT_RTC_CH1_DLY 39 // RTC channel 1 - delayed event
#define AON_EVENT_RTC_CH2_DLY 40 // RTC channel 2 - delayed event
#define AON_EVENT_RTC_COMB_DLY 41 // RTC combined delayed event
#define AON_EVENT_RTC_UPD 42 // RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period)
#define AON_EVENT_JTAG 43 // JTAG generated event
#define AON_EVENT_AUX_SWEV0 44 // AUX Software triggered event #0
#define AON_EVENT_AUX_SWEV1 45 // AUX Software triggered event #1
#define AON_EVENT_AUX_SWEV2 46 // AUX Software triggered event #2
#define AON_EVENT_AUX_COMPA 47 // Comparator A triggered (synchronized in AUX)
#define AON_EVENT_AUX_COMPB 48 // Comparator B triggered (synchronized in AUX)
#define AON_EVENT_AUX_ADC_DONE 49 // ADC conversion completed
#define AON_EVENT_AUX_TDC_DONE 50 // TDC completed or timed out
#define AON_EVENT_AUX_TIMER0_EV 51 // Timer 0 event
#define AON_EVENT_AUX_TIMER1_EV 52 // Timer 1 event
#define AON_EVENT_BATMON_TEMP 53 // BATMON temperature update event
#define AON_EVENT_BATMON_VOLT 54 // BATMON voltage update event
#define AON_EVENT_AUX_COMPB_ASYNC 55 // Comparator B triggered. Asynchronous signal directly from the AUX Comparator B
#define AON_EVENT_AUX_COMPB_ASYNC_N 56 // Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B
// Event ID 57-62 is reserved for future use
#define AON_EVENT_NONE 63 // No event, always low
// Keeping backward compatibility until major revision number is incremented
#define AON_EVENT_RTC0 ( AON_EVENT_RTC_CH0 )
//*****************************************************************************
//
// Values that can be passed to AONEventMCUWakeUpSet() and returned
// by AONEventMCUWakeUpGet().
//
//*****************************************************************************
#define AON_EVENT_MCU_WU0 0 // Programmable MCU wake-up event 0
#define AON_EVENT_MCU_WU1 1 // Programmable MCU wake-up event 1
#define AON_EVENT_MCU_WU2 2 // Programmable MCU wake-up event 2
#define AON_EVENT_MCU_WU3 3 // Programmable MCU wake-up event 3
#define AON_EVENT_MCU_WU4 4 // Programmable MCU wake-up event 4
#define AON_EVENT_MCU_WU5 5 // Programmable MCU wake-up event 5
#define AON_EVENT_MCU_WU6 6 // Programmable MCU wake-up event 6
#define AON_EVENT_MCU_WU7 7 // Programmable MCU wake-up event 7
//*****************************************************************************
//
// Values that can be passed to AONEventMcuSet() and AONEventMcuGet()
//
//*****************************************************************************
#define AON_EVENT_MCU_EVENT0 0 // Programmable event source fed to MCU event fabric (first of 3)
#define AON_EVENT_MCU_EVENT1 1 // Programmable event source fed to MCU event fabric (second of 3)
#define AON_EVENT_MCU_EVENT2 2 // Programmable event source fed to MCU event fabric (third of 3)
//*****************************************************************************
//
// API Functions and prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Select event source for the specified MCU wake-up programmable event.
//!
//! The AON event fabric has several programmable events that can wake up the MCU.
//!
//! \note The programmable event sources are effectively OR'ed together
//! to form a single wake-up event.
//!
//! \param ui32MCUWUEvent is one of the programmable MCU wake-up event sources.
//! - \ref AON_EVENT_MCU_WU0
//! - \ref AON_EVENT_MCU_WU1
//! - \ref AON_EVENT_MCU_WU2
//! - \ref AON_EVENT_MCU_WU3
//! - \ref AON_EVENT_MCU_WU4
//! - \ref AON_EVENT_MCU_WU5
//! - \ref AON_EVENT_MCU_WU6
//! - \ref AON_EVENT_MCU_WU7
//! \param ui32EventSrc is an event source for the event AON fabric.
//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU
//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2
//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2
//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2
//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2
//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit
//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit
//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit
//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit
//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON
//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC.
//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0
//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1
//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2
//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event
//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event
//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event
//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event
//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period)
//! - \ref AON_EVENT_JTAG : JTAG generated event
//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0
//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1
//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2
//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX)
//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX)
//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed
//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out
//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event
//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event
//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event
//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event
//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B
//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B
//! - \ref AON_EVENT_NONE : No event, always low
//!
//! \return None
//!
//! \sa AONEventMcuWakeUpGet()
//
//*****************************************************************************
extern void AONEventMcuWakeUpSet(uint32_t ui32MCUWUEvent,
uint32_t ui32EventSrc);
//*****************************************************************************
//
//! \brief Get event source for the specified MCU wake-up programmable event.
//!
//! \param ui32MCUWUEvent is one of the programmable MCU wake-up event sources.
//! - \ref AON_EVENT_MCU_WU0
//! - \ref AON_EVENT_MCU_WU1
//! - \ref AON_EVENT_MCU_WU2
//! - \ref AON_EVENT_MCU_WU3
//! - \ref AON_EVENT_MCU_WU4
//! - \ref AON_EVENT_MCU_WU5
//! - \ref AON_EVENT_MCU_WU6
//! - \ref AON_EVENT_MCU_WU7
//!
//! \return Returns the event source for the event AON fabric.
//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU
//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2
//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2
//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2
//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2
//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit
//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit
//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit
//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit
//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON
//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC.
//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0
//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1
//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2
//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event
//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event
//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event
//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event
//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period)
//! - \ref AON_EVENT_JTAG : JTAG generated event
//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0
//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1
//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2
//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX)
//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX)
//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed
//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out
//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event
//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event
//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event
//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event
//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B
//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B
//! - \ref AON_EVENT_NONE : No event, always low
//!
//! \sa AONEventMcuWakeUpSet()
//
//*****************************************************************************
extern uint32_t AONEventMcuWakeUpGet(uint32_t ui32MCUWUEvent);
//*****************************************************************************
//
//! \brief Select event source for the specified programmable event forwarded to the
//! MCU event fabric.
//!
//! The AON event fabric has a total of three programmable events that can
//! be forwarded to the MCU event fabric.
//!
//! \note The three programmable event sources are forwarded to the MCU Event
//! Fabric as:
//! - AON_PROG0
//! - AON_PROG1
//! - AON_PROG2
//!
//! \param ui32MCUEvent is one of three programmable events forwarded to the
//! MCU event fabric.
//! - \ref AON_EVENT_MCU_EVENT0
//! - \ref AON_EVENT_MCU_EVENT1
//! - \ref AON_EVENT_MCU_EVENT2
//! \param ui32EventSrc is an event source for the event AON fabric.
//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU
//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2
//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2
//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2
//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2
//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit
//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit
//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit
//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit
//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON
//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC.
//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0
//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1
//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2
//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event
//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event
//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event
//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event
//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period)
//! - \ref AON_EVENT_JTAG : JTAG generated event
//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0
//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1
//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2
//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX)
//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX)
//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed
//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out
//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event
//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event
//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event
//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event
//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B
//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B
//! - \ref AON_EVENT_NONE : No event, always low
//!
//! \return None
//!
//! \sa AONEventMcuGet()
//
//*****************************************************************************
extern void AONEventMcuSet(uint32_t ui32MCUEvent, uint32_t ui32EventSrc);
//*****************************************************************************
//
//! \brief Get source for the specified programmable event forwarded to the MCU event
//! fabric.
//!
//! The AON event fabric has a total of three programmable events that can
//! be forwarded to the MCU event fabric.
//!
//! \param ui32MCUEvent is one of three programmable events forwarded to the
//! MCU event fabric.
//! - \ref AON_EVENT_MCU_EVENT0
//! - \ref AON_EVENT_MCU_EVENT1
//! - \ref AON_EVENT_MCU_EVENT2
//!
//! \return Returns the event source for the event AON fabric.
//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU
//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2
//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2
//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2
//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2
//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit
//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit
//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit
//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit
//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON
//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC.
//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0
//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1
//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2
//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event
//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event
//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event
//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event
//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period)
//! - \ref AON_EVENT_JTAG : JTAG generated event
//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0
//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1
//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2
//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX)
//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX)
//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed
//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out
//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event
//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event
//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event
//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event
//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B
//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B
//! - \ref AON_EVENT_NONE : No event, always low
//!
//! \sa AONEventMcuSet()
//
//*****************************************************************************
extern uint32_t AONEventMcuGet(uint32_t ui32MCUEvent);
//*****************************************************************************
//
//! \brief Select event source forwarded to AON Real Time Clock (RTC).
//!
//! A programmable event can be forwarded to the AON real time clock
//! for triggering a capture event on RTC channel 1.
//!
//! \param ui32EventSrc is an event source for the event AON fabric.
//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU
//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2
//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2
//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2
//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2
//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit
//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit
//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit
//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit
//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON
//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC.
//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0
//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1
//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2
//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event
//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event
//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event
//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event
//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period)
//! - \ref AON_EVENT_JTAG : JTAG generated event
//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0
//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1
//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2
//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX)
//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX)
//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed
//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out
//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event
//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event
//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event
//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event
//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B
//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B
//! - \ref AON_EVENT_NONE : No event, always low
//!
//! \return None
//!
//! \sa AONEventRtcGet()
//
//*****************************************************************************
__STATIC_INLINE void
AONEventRtcSet(uint32_t ui32EventSrc)
{
uint32_t ui32Ctrl;
// Check the arguments.
ASSERT(ui32EventSrc <= AON_EVENT_NONE);
ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_RTCSEL);
ui32Ctrl &= ~(AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M);
ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S;
HWREG(AON_EVENT_BASE + AON_EVENT_O_RTCSEL) = ui32Ctrl;
}
//*****************************************************************************
//
//! \brief Get event source forwarded to AON Real Time Clock (RTC).
//!
//! A programmable event can be forwarded to the AON real time clock
//! for triggering a capture event on RTC channel 1.
//!
//! \return Returns the event source to the event AON fabric.
//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU
//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2
//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2
//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2
//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2
//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit
//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit
//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit
//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit
//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON
//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC.
//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0
//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1
//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2
//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event
//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event
//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event
//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event
//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period)
//! - \ref AON_EVENT_JTAG : JTAG generated event
//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0
//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1
//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2
//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX)
//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX)
//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed
//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out
//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event
//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event
//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event
//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event
//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B
//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B
//! - \ref AON_EVENT_NONE : No event, always low
//!
//! \sa AONEventRtcSet()
//
//*****************************************************************************
__STATIC_INLINE uint32_t
AONEventRtcGet(void)
{
uint32_t ui32EventSrc;
// Return the active event.
ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_RTCSEL);
return ((ui32EventSrc & AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M) >>
AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S);
}
//*****************************************************************************
//
// Support for DriverLib in ROM:
// Redirect to implementation in ROM when available.
//
//*****************************************************************************
#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
#include "../driverlib/rom.h"
#ifdef ROM_AONEventMcuWakeUpSet
#undef AONEventMcuWakeUpSet
#define AONEventMcuWakeUpSet ROM_AONEventMcuWakeUpSet
#endif
#ifdef ROM_AONEventMcuWakeUpGet
#undef AONEventMcuWakeUpGet
#define AONEventMcuWakeUpGet ROM_AONEventMcuWakeUpGet
#endif
#ifdef ROM_AONEventMcuSet
#undef AONEventMcuSet
#define AONEventMcuSet ROM_AONEventMcuSet
#endif
#ifdef ROM_AONEventMcuGet
#undef AONEventMcuGet
#define AONEventMcuGet ROM_AONEventMcuGet
#endif
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __AON_EVENT_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

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/******************************************************************************
* Filename: aon_event_doc.h
* Revised: 2017-08-09 16:56:05 +0200 (Wed, 09 Aug 2017)
* Revision: 49506
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//! \addtogroup aonevent_api
//! @{
//! \section sec_aonevent Introduction
//!
//! The event fabric consists of two event modules. One in the MCU power domain (MCU event fabric) and
//! the other in the AON power domain (AON event fabric). The MCU event fabric is one of the subscribers
//! to the AON event fabric. For more information on MCU event fabric, see [MCU event API](@ref event_api).
//!
//! The AON event fabric is a configurable combinatorial router between AON event sources and event
//! subscribers in both AON and MCU domains. The API to control the AON event fabric configuration
//! can be grouped based on the event subscriber to configure:
//!
//! - Wake-up events.
//! - MCU wake-up event
//! - @ref AONEventMcuWakeUpSet()
//! - @ref AONEventMcuWakeUpGet()
//! - AON RTC receives a single programmable event line from the AON event fabric. For more information, see [AON RTC API](@ref aonrtc_api).
//! - @ref AONEventRtcSet()
//! - @ref AONEventRtcGet()
//! - MCU event fabric receives a number of programmable event lines from the AON event fabric. For more information, see [MCU event API](@ref event_api).
//! - @ref AONEventMcuSet()
//! - @ref AONEventMcuGet()
//! @}

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/******************************************************************************
* Filename: aon_ioc.c
* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016)
* Revision: 47343
*
* Description: Driver for the AON IO Controller
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "aon_ioc.h"

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/******************************************************************************
* Filename: aon_ioc.h
* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016)
* Revision: 47343
*
* Description: Defines and prototypes for the AON IO Controller
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup aon_group
//! @{
//! \addtogroup aonioc_api
//! @{
//
//*****************************************************************************
#ifndef __AON_IOC_H__
#define __AON_IOC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdbool.h>
#include <stdint.h>
#include "../inc/hw_types.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_aon_ioc.h"
#include "debug.h"
//*****************************************************************************
//
// Defines for the drive strength
//
//*****************************************************************************
#define AONIOC_DRV_STR_1 0x00000000 // Lowest drive strength
#define AONIOC_DRV_STR_2 0x00000001
#define AONIOC_DRV_STR_3 0x00000003
#define AONIOC_DRV_STR_4 0x00000002
#define AONIOC_DRV_STR_5 0x00000006
#define AONIOC_DRV_STR_6 0x00000007
#define AONIOC_DRV_STR_7 0x00000005
#define AONIOC_DRV_STR_8 0x00000004 // Highest drive strength
#define AONIOC_DRV_LVL_MIN (AON_IOC_O_IOSTRMIN)
#define AONIOC_DRV_LVL_MED (AON_IOC_O_IOSTRMED)
#define AONIOC_DRV_LVL_MAX (AON_IOC_O_IOSTRMAX)
//*****************************************************************************
//
// API Functions and prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Configure drive strength values for the manual drive strength options.
//!
//! This function defines the general drive strength settings for the non-AUTO
//! drive strength options in the MCU IOC. Consequently, if all IOs are using the
//! automatic drive strength option this function has no effect.
//!
//! Changing the drive strength values affects all current modes (Low-Current,
//! High-Current, and Extended-Current). Current mode for individual IOs is set in
//! MCU IOC by \ref IOCIODrvStrengthSet().
//!
//! \note Values are Gray encoded. Simply incrementing values to increase drive
//! strength will not work.
//!
//! \param ui32DriveLevel
//! - \ref AONIOC_DRV_LVL_MIN : Minimum drive strength option. Default value is selected
//! to give minimum 2/4/8 mA @3.3V for Low-Current mode, High-Current mode,
//! and Extended-Current mode respectively.
//! - \ref AONIOC_DRV_LVL_MED : Medium drive strength option. Default value is selected
//! to give minimum 2/4/8 mA @2.5V for Low-Current mode, High-Current mode,
//! and Extended-Current mode respectively.
//! - \ref AONIOC_DRV_LVL_MAX : Maximum drive strength option. Default value is selected
//! to give minimum 2/4/8 mA @1.8V for Low-Current mode, High-Current mode,
//! and Extended-Current mode respectively.
//! \param ui32DriveStrength sets the value used by IOs configured as non-AUTO drive strength in MCU IOC.
//! - \ref AONIOC_DRV_STR_1 : Lowest drive strength
//! - \ref AONIOC_DRV_STR_2
//! - \ref AONIOC_DRV_STR_3
//! - \ref AONIOC_DRV_STR_4
//! - \ref AONIOC_DRV_STR_5
//! - \ref AONIOC_DRV_STR_6
//! - \ref AONIOC_DRV_STR_7
//! - \ref AONIOC_DRV_STR_8 : Highest drive strength
//!
//! \return None
//!
//! \sa \ref AONIOCDriveStrengthGet(), \ref IOCIODrvStrengthSet()
//
//*****************************************************************************
__STATIC_INLINE void
AONIOCDriveStrengthSet(uint32_t ui32DriveLevel, uint32_t ui32DriveStrength)
{
ASSERT((ui32DriveLevel == AONIOC_DRV_LVL_MIN) ||
(ui32DriveLevel == AONIOC_DRV_LVL_MED) ||
(ui32DriveLevel == AONIOC_DRV_LVL_MAX));
ASSERT((ui32DriveStrength == AONIOC_DRV_STR_1) ||
(ui32DriveStrength == AONIOC_DRV_STR_2) ||
(ui32DriveStrength == AONIOC_DRV_STR_3) ||
(ui32DriveStrength == AONIOC_DRV_STR_4) ||
(ui32DriveStrength == AONIOC_DRV_STR_5) ||
(ui32DriveStrength == AONIOC_DRV_STR_6) ||
(ui32DriveStrength == AONIOC_DRV_STR_7) ||
(ui32DriveStrength == AONIOC_DRV_STR_8));
// Set the drive strength.
HWREG(AON_IOC_BASE + ui32DriveLevel) = ui32DriveStrength;
}
//*****************************************************************************
//
//! \brief Get a specific drive level setting for all IOs.
//!
//! Use this function to read the drive strength setting for a specific
//! IO drive level.
//!
//! \note Values are Gray encoded.
//!
//! \param ui32DriveLevel is the specific drive level to get the setting for.
//! - \ref AONIOC_DRV_LVL_MIN : Minimum drive strength option.
//! - \ref AONIOC_DRV_LVL_MED : Medium drive strength option.
//! - \ref AONIOC_DRV_LVL_MAX : Maximum drive strength option.
//!
//! \return Returns the requested drive strength level setting for all IOs.
//! Possible values are:
//! - \ref AONIOC_DRV_STR_1 : Lowest drive strength
//! - \ref AONIOC_DRV_STR_2
//! - \ref AONIOC_DRV_STR_3
//! - \ref AONIOC_DRV_STR_4
//! - \ref AONIOC_DRV_STR_5
//! - \ref AONIOC_DRV_STR_6
//! - \ref AONIOC_DRV_STR_7
//! - \ref AONIOC_DRV_STR_8 : Highest drive strength
//!
//! \sa AONIOCDriveStrengthSet()
//
//*****************************************************************************
__STATIC_INLINE uint32_t
AONIOCDriveStrengthGet(uint32_t ui32DriveLevel)
{
// Check the arguments.
ASSERT((ui32DriveLevel == AONIOC_DRV_LVL_MIN) ||
(ui32DriveLevel == AONIOC_DRV_LVL_MED) ||
(ui32DriveLevel == AONIOC_DRV_LVL_MAX));
// Return the drive strength value.
return( HWREG(AON_IOC_BASE + ui32DriveLevel) );
}
//*****************************************************************************
//
//! \brief Freeze the IOs.
//!
//! To retain the values of the output IOs during a powerdown/shutdown of the
//! device all IO latches in the AON domain should be frozen in their current
//! state. This ensures that software can regain control of the IOs after a
//! reboot without the IOs first falling back to the default values (i.e. input
//! and no pull).
//!
//! \return None
//!
//! \sa AONIOCFreezeDisable()
//
//*****************************************************************************
__STATIC_INLINE void
AONIOCFreezeEnable(void)
{
// Set the AON IO latches as static.
HWREG(AON_IOC_BASE + AON_IOC_O_IOCLATCH) = 0x0;
}
//*****************************************************************************
//
//! \brief Un-freeze the IOs.
//!
//! When rebooting the chip after it has entered powerdown/shutdown mode, the
//! software can regain control of the IOs by setting the IO latches as
//! transparent. The IOs should not be unfrozen before software has restored
//! the functionality of the IO.
//!
//! \return None
//!
//! \sa AONIOCFreezeEnable()
//
//*****************************************************************************
__STATIC_INLINE void
AONIOCFreezeDisable(void)
{
// Set the AON IOC latches as transparent.
HWREG(AON_IOC_BASE + AON_IOC_O_IOCLATCH) = AON_IOC_IOCLATCH_EN;
}
//*****************************************************************************
//
//! \brief Disable the 32kHz clock output.
//!
//! When outputting a 32 kHz clock on an IO, the output enable/disable functionality
//! in the IOC is bypassed. Therefore, the programmer needs to call this
//! function to disable the clock output.
//!
//! \return None
//!
//! \sa AONIOC32kHzOutputEnable()
//
//*****************************************************************************
__STATIC_INLINE void
AONIOC32kHzOutputDisable(void)
{
// Disable the LF clock output.
HWREG(AON_IOC_BASE + AON_IOC_O_CLK32KCTL) = AON_IOC_CLK32KCTL_OE_N;
}
//*****************************************************************************
//
//! \brief Enable the 32kHz clock output.
//!
//! When outputting a 32 kHz clock on an IO, the output enable/disable functionality
//! in the IOC is bypassed. Therefore, the programmer needs to call this
//! function to enable the clock output.
//!
//! \return None
//!
//! \sa AONIOC32kHzOutputDisable()
//
//*****************************************************************************
__STATIC_INLINE void
AONIOC32kHzOutputEnable(void)
{
// Enable the LF clock output.
HWREG(AON_IOC_BASE + AON_IOC_O_CLK32KCTL) = 0x0;
}
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __AON_IOC_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

65
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/******************************************************************************
* Filename: aon_ioc_doc.h
* Revised: 2016-03-30 11:01:30 +0200 (Wed, 30 Mar 2016)
* Revision: 45969
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//! \addtogroup aonioc_api
//! @{
//! \section sec_aonioc Introduction
//!
//! The Input/Output Controller (IOC) controls the functionality of the pins (called DIO).
//! The IOC consists of two APIs:
//! - MCU IOC API selects which peripheral module is connected to the individual DIO and thus allowed to control it.
//! It also controls individual drive strength, slew rate, pull-up/pull-down, edge detection, etc.
//! - AON IOC API controls the general drive strength definitions, IO latches, and if the LF clock is
//! routed to a DIO for external use.
//!
//! For more information on the MCU IOC see the [IOC API](\ref ioc_api).
//!
//! \section sec_aonioc_api API
//!
//! The API functions can be grouped like this:
//!
//! Freeze IOs while MCU domain is powered down:
//! - \ref AONIOCFreezeEnable()
//! - \ref AONIOCFreezeDisable()
//!
//! Output LF clock to a DIO:
//! - \ref AONIOC32kHzOutputEnable()
//! - \ref AONIOC32kHzOutputDisable()
//!
//! Configure the value of drive strength for the three manual MCU IOC settings (MIN, MED, MAX):
//! - \ref AONIOCDriveStrengthSet()
//! - \ref AONIOCDriveStrengthGet()
//!
//! @}

41
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/******************************************************************************
* Filename: aon_pmctl.c
* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017)
* Revision: 49096
*
* Description: Driver for the AON Power-Management Controller.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "aon_pmctl.h"
// See aon_pmctl.h for implementation

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/******************************************************************************
* Filename: aon_pmctl.h
* Revised: 2017-11-02 14:16:14 +0100 (Thu, 02 Nov 2017)
* Revision: 50156
*
* Description: Defines and prototypes for the AON Power-Management Controller
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup aon_group
//! @{
//! \addtogroup aonpmctl_api
//! @{
//
//*****************************************************************************
#ifndef __AON_PMCTL_H__
#define __AON_PMCTL_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdbool.h>
#include <stdint.h>
#include "../inc/hw_types.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_aon_pmctl.h"
#include "debug.h"
//*****************************************************************************
//
// Defines that can be be used to enable/disable the retention on the SRAM
// banks during power off of the MCU BUS domain. The defines can be passed to
// AONPMCTLMcuSRamConfig) .
//
//*****************************************************************************
#define MCU_RAM_RET_NONE AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_NONE
#define MCU_RAM_RET_LVL1 AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL1
#define MCU_RAM_RET_LVL2 AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL2
#define MCU_RAM_RET_LVL3 AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL3
#define MCU_RAM_RET_FULL AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_FULL
//*****************************************************************************
//
// Defines for all the different power modes available through
// AONPMCTLPowerStatusGet() .
//
//*****************************************************************************
#define AONPMCTL_JTAG_POWER_ON AON_PMCTL_PWRSTAT_JTAG_PD_ON
//*****************************************************************************
//
// API Functions and prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Configure the retention on the block SRAM in the MCU BUS domain.
//!
//! MCU SRAM is partitioned into 5 banks of 16 KB each. The SRAM supports
//! retention on all 5 banks during MCU BUS domain power off. The retention
//! on the SRAM can be turned on and off. Use this function to enable the
//! retention on the banks.
//!
//! If a group of banks is not represented in the parameter \c ui32Retention
//! then the retention will be disabled for that bank group during MCU BUS
//! domain power off.
//!
//! \note Retention on all SRAM banks is enabled by default. Configuration of
//! individual SRAM banks is not supported. Configuration is only supported
//! on bank group level.
//!
//! \param ui32Retention defines which groups of SRAM banks to enable/disable
//! retention on:
//! - \ref MCU_RAM_RET_NONE Retention is disabled
//! - \ref MCU_RAM_RET_LVL1 Retention on for banks 0 and 1
//! - \ref MCU_RAM_RET_LVL2 Retention on for banks 0, 1 and 2
//! - \ref MCU_RAM_RET_LVL3 Retention on for banks 0, 1, 2 and 3
//! - \ref MCU_RAM_RET_FULL Retention on for all five banks
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
AONPMCTLMcuSRamRetConfig(uint32_t ui32Retention)
{
uint32_t ui32Reg;
// Check the arguments.
ASSERT((ui32Retention == MCU_RAM_RET_NONE) ||
(ui32Retention == MCU_RAM_RET_LVL1) ||
(ui32Retention == MCU_RAM_RET_LVL2) ||
(ui32Retention == MCU_RAM_RET_LVL3) ||
(ui32Retention == MCU_RAM_RET_FULL));
// Configure the retention.
ui32Reg = HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RAMCFG) & ~AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_M;
ui32Reg |= ui32Retention;
HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RAMCFG) = ui32Reg;
}
//*****************************************************************************
//
//! \brief Get the power status of the Always On (AON) domain.
//!
//! This function reports the power management status in AON.
//!
//! \return Returns the current power status of the device as a bitwise OR'ed
//! combination of these values:
//! - \ref AONPMCTL_JTAG_POWER_ON
//
//*****************************************************************************
__STATIC_INLINE uint32_t
AONPMCTLPowerStatusGet(void)
{
// Return the power status.
return (HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRSTAT));
}
//*****************************************************************************
//
//! \brief Request power off of the JTAG domain.
//!
//! The JTAG domain is automatically powered up on if a debugger is connected.
//! If a debugger is not connected this function can be used to power off the
//! JTAG domain.
//!
//! \note Achieving the lowest power modes (shutdown/powerdown) requires the
//! JTAG domain to be turned off. In general the JTAG domain should never be
//! powered in production code.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
AONPMCTLJtagPowerOff(void)
{
// Request the power off of the JTAG domain
HWREG(AON_PMCTL_BASE + AON_PMCTL_O_JTAGCFG) = 0;
}
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __AON_PMCTL_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

99
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@ -1,99 +0,0 @@
/******************************************************************************
* Filename: aon_pmctl_doc.h
* Revised: 2017-11-02 15:41:14 +0100 (Thu, 02 Nov 2017)
* Revision: 50165
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//! \addtogroup aonpmctl_api
//! @{
//! \section sec_aonpmctl Introduction
//!
//! This API provides a set of functions for using the AON Power Management
//! Controller module (AON_PMCTL).
//!
//! The AON_PMCTL module contains the following functional options:
//! - Selection of voltage regulator for the digital domain.
//! - Control of retention of MCU SRAM banks during power off of the BUS power domain.
//! - Control of power and retention of AUX SRAM.
//! - Control of power, reset, and clock for the following domains:
//! - MCU_VD
//! - JTAG_PD
//! - AUX
//! - Control of the recharging of VDDR while in uLDO state.
//! - Control of the generation of a periodic request to the OSCDIG to initiate
//! an XOSC_HF amplitude calibration sequence.
//!
//! The main clock for the AON_PMCTL module is the 2 MHz SCLK MF clock.
//!
//! AON_PMCTL supports the MCU_voltage domain with a 48 MHz clock (SCLK_HF) that is divided
//! and gated by the PRCM module before being distributed to all modules in the
//! MCU voltage domain.
//!
//! The AON_PMCTL controls the SCLK_HF clock to ensure that it is available in the
//! Active and Idle power modes, and disabled for all other modes. SCLK_HF is not
//! allowed in uLDO state since it uses too much power.
//! The SCLK_HF clock is also available for the AUX module in the Active and Idle
//! power modes.
//!
//! The AON_PMCTL selects the clock source for the AUX domain in the different
//! power modes.
//!
//! Main functionality to control power management of the JTAG power domain is
//! supported. Note that no clock control is supported, as the JTAG is clocked
//! on the TCK clock.
//!
//!
//! \section sec_aonpmctl_api API
//!
//! The API functions can be grouped like this:
//!
//! Functions to perform status report:
//! - \ref AONPMCTLPowerStatusGet()
//!
//!
//! Functions to perform device configuration:
//! - \ref AONPMCTLJtagPowerOff()
//! - \ref AONPMCTLMcuSRamRetConfig()
//!
//! Please note that due to legacy software compatibility some functionalities controlled
//! by the AON Power Management Controller module are supported through the APIs of
//! the [System Controller](@ref sysctrl_api) and [Power Controller](@ref pwrctrl_api). Relevant functions are:
//! - \ref PowerCtrlSourceGet()
//! - \ref PowerCtrlSourceSet()
//! - \ref PowerCtrlResetSourceGet()
//! - \ref SysCtrl_DCDC_VoltageConditionalControl()
//! - \ref SysCtrlClockLossResetDisable()
//! - \ref SysCtrlClockLossResetEnable()
//! - \ref SysCtrlSystemReset()
//! - \ref SysCtrlResetSourceGet()
//!
//! @}

77
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@ -1,77 +0,0 @@
/******************************************************************************
* Filename: aon_rtc.c
* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017)
* Revision: 49096
*
* Description: Driver for the AON RTC.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "aon_rtc.h"
#include "cpu.h"
//*****************************************************************************
//
// Handle support for DriverLib in ROM:
// This section will undo prototype renaming made in the header file
//
//*****************************************************************************
#if !defined(DOXYGEN)
#undef AONRTCCurrent64BitValueGet
#define AONRTCCurrent64BitValueGet NOROM_AONRTCCurrent64BitValueGet
#endif
//*****************************************************************************
//
// Get the current 64-bit value of the RTC counter.
//
//*****************************************************************************
uint64_t
AONRTCCurrent64BitValueGet( void )
{
union {
uint64_t returnValue ;
uint32_t secAndSubSec[ 2 ] ;
} currentRtc ;
uint32_t ui32SecondSecRead ;
// Reading SEC both before and after SUBSEC in order to detect if SEC incremented while reading SUBSEC
// If SEC incremented, we can't be sure which SEC the SUBSEC belongs to, so repeating the sequence then.
do {
currentRtc.secAndSubSec[ 1 ] = HWREG( AON_RTC_BASE + AON_RTC_O_SEC );
currentRtc.secAndSubSec[ 0 ] = HWREG( AON_RTC_BASE + AON_RTC_O_SUBSEC );
ui32SecondSecRead = HWREG( AON_RTC_BASE + AON_RTC_O_SEC );
} while ( currentRtc.secAndSubSec[ 1 ] != ui32SecondSecRead );
return ( currentRtc.returnValue );
}

931
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@ -1,931 +0,0 @@
/******************************************************************************
* Filename: aon_rtc.h
* Revised: 2017-08-16 15:13:43 +0200 (Wed, 16 Aug 2017)
* Revision: 49593
*
* Description: Defines and prototypes for the AON RTC
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup aon_group
//! @{
//! \addtogroup aonrtc_api
//! @{
//
//*****************************************************************************
#ifndef __AON_RTC_H__
#define __AON_RTC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdbool.h>
#include <stdint.h>
#include "../inc/hw_types.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_aon_rtc.h"
#include "debug.h"
//*****************************************************************************
//
// Support for DriverLib in ROM:
// This section renames all functions that are not "static inline", so that
// calling these functions will default to implementation in flash. At the end
// of this file a second renaming will change the defaults to implementation in
// ROM for available functions.
//
// To force use of the implementation in flash, e.g. for debugging:
// - Globally: Define DRIVERLIB_NOROM at project level
// - Per function: Use prefix "NOROM_" when calling the function
//
//*****************************************************************************
#if !defined(DOXYGEN)
#define AONRTCCurrent64BitValueGet NOROM_AONRTCCurrent64BitValueGet
#endif
//*****************************************************************************
//
// Values that can be passed to most of the AON_RTC APIs as the ui32Channel
// parameter.
//
//*****************************************************************************
#define AON_RTC_CH_NONE 0x0 // RTC No channel
#define AON_RTC_CH0 0x1 // RTC Channel 0
#define AON_RTC_CH1 0x2 // RTC Channel 1
#define AON_RTC_CH2 0x4 // RTC Channel 2
#define AON_RTC_ACTIVE 0x8 // RTC Active
//*****************************************************************************
//
// Values that can be passed to AONRTCConfigDelay as the ui32Delay parameter.
//
//*****************************************************************************
#define AON_RTC_CONFIG_DELAY_NODELAY 0 // NO DELAY
#define AON_RTC_CONFIG_DELAY_1 1 // Delay of 1 clk cycle
#define AON_RTC_CONFIG_DELAY_2 2 // Delay of 2 clk cycles
#define AON_RTC_CONFIG_DELAY_4 3 // Delay of 4 clk cycles
#define AON_RTC_CONFIG_DELAY_8 4 // Delay of 8 clk cycles
#define AON_RTC_CONFIG_DELAY_16 5 // Delay of 16 clk cycles
#define AON_RTC_CONFIG_DELAY_32 6 // Delay of 32 clk cycles
#define AON_RTC_CONFIG_DELAY_48 7 // Delay of 48 clk cycles
#define AON_RTC_CONFIG_DELAY_64 8 // Delay of 64 clk cycles
#define AON_RTC_CONFIG_DELAY_80 9 // Delay of 80 clk cycles
#define AON_RTC_CONFIG_DELAY_96 10 // Delay of 96 clk cycles
#define AON_RTC_CONFIG_DELAY_112 11 // Delay of 112 clk cycles
#define AON_RTC_CONFIG_DELAY_128 12 // Delay of 128 clk cycles
#define AON_RTC_CONFIG_DELAY_144 13 // Delay of 144 clk cycles
//*****************************************************************************
//
// Values that can be passed to AONRTCSetModeCH1 as the ui32Mode
// parameter.
//
//*****************************************************************************
#define AON_RTC_MODE_CH1_CAPTURE 1 // Capture mode
#define AON_RTC_MODE_CH1_COMPARE 0 // Compare Mode
//*****************************************************************************
//
// Values that can be passed to AONRTCSetModeCH2 as the ui32Mode
// parameter.
//
//*****************************************************************************
#define AON_RTC_MODE_CH2_CONTINUOUS 1 // Continuous mode
#define AON_RTC_MODE_CH2_NORMALCOMPARE 0 // Normal compare mode
//*****************************************************************************
//
// Mutliplication factor for converting from seconds to corresponding time in
// the "CompareValue" format.
// The factor correspond to the compare value format described in the registers
// \ref AON_RTC_O_CH0CMP, \ref AON_RTC_O_CH1CMP and \ref AON_RTC_O_CH2CMP.
// Example1:
// 4 milliseconds in CompareValue format can be written like this:
// ((uint32_t)( 0.004 * FACTOR_SEC_TO_COMP_VAL_FORMAT ))
// Example2:
// 4 seconds in CompareValue format can be written like this:
// ( 4 * FACTOR_SEC_TO_COMP_VAL_FORMAT )
//
//*****************************************************************************
#define FACTOR_SEC_TO_COMP_VAL_FORMAT 0x00010000
//*****************************************************************************
//
// API Functions and prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Enable the RTC.
//!
//! Enable the AON Real Time Clock.
//!
//! \note Event generation for each of the three channels must also be enabled
//! using the function AONRTCChannelEnable().
//!
//! \return None
//!
//! \sa AONRTCChannelEnable()
//
//*****************************************************************************
__STATIC_INLINE void
AONRTCEnable(void)
{
// Enable RTC.
HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN) = 1;
}
//*****************************************************************************
//
//! \brief Disable the RTC.
//!
//! Disable the AON Real Time Clock.
//!
//! \note Event generation for each of the three channels can also be disabled
//! using the function AONRTCChannelDisable().
//!
//! \return None
//!
//! \sa AONRTCChannelDisable()
//
//*****************************************************************************
__STATIC_INLINE void
AONRTCDisable(void)
{
// Disable RTC
HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN) = 0;
}
//*****************************************************************************
//
//! \brief Reset the RTC.
//!
//! Reset the AON Real Time Clock.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
AONRTCReset(void)
{
// Reset RTC.
HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_RESET_BITN) = 1;
}
//*****************************************************************************
//
//! \brief Check if the RTC is active (enabled).
//!
//! \return Returns the status of the RTC.
//! - false : RTC is disabled
//! - true : RTC is enabled
//
//*****************************************************************************
__STATIC_INLINE bool
AONRTCActive(void)
{
// Read if RTC is enabled
return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN));
}
//*****************************************************************************
//
//! \brief Check if an RTC channel is active (enabled).
//!
//! \param ui32Channel specifies the RTC channel to check status of.
//! Parameter must be one (and only one) of the following:
//! - \ref AON_RTC_CH0
//! - \ref AON_RTC_CH1
//! - \ref AON_RTC_CH2
//!
//! \return Returns the status of the requested channel:
//! - false : Channel is disabled
//! - true : Channel is enabled
//
//*****************************************************************************
__STATIC_INLINE bool
AONRTCChannelActive(uint32_t ui32Channel)
{
uint32_t uint32Status = 0;
if(ui32Channel & AON_RTC_CH0)
{
uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN);
}
if(ui32Channel & AON_RTC_CH1)
{
uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN);
}
if(ui32Channel & AON_RTC_CH2)
{
uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN);
}
return(uint32Status);
}
//*****************************************************************************
//
//! \brief Configure Event Delay for the RTC.
//!
//! Each event from the three individual channels can generate a delayed
//! event. The delay time for these events is set using this function.
//! The delay is measured in clock cycles.
//!
//! \note There is only one delay setting shared for all three channels.
//!
//! \param ui32Delay specifies the delay time for delayed events.
//! Parameter must be one of the following:
//! - \ref AON_RTC_CONFIG_DELAY_NODELAY
//! - \ref AON_RTC_CONFIG_DELAY_1
//! - \ref AON_RTC_CONFIG_DELAY_2
//! - \ref AON_RTC_CONFIG_DELAY_4
//! - \ref AON_RTC_CONFIG_DELAY_8
//! - \ref AON_RTC_CONFIG_DELAY_16
//! - \ref AON_RTC_CONFIG_DELAY_32
//! - \ref AON_RTC_CONFIG_DELAY_48
//! - \ref AON_RTC_CONFIG_DELAY_64
//! - \ref AON_RTC_CONFIG_DELAY_80
//! - \ref AON_RTC_CONFIG_DELAY_96
//! - \ref AON_RTC_CONFIG_DELAY_112
//! - \ref AON_RTC_CONFIG_DELAY_128
//! - \ref AON_RTC_CONFIG_DELAY_144
//!
//! \return None.
//
//*****************************************************************************
__STATIC_INLINE void
AONRTCDelayConfig(uint32_t ui32Delay)
{
uint32_t ui32Cfg;
// Check the arguments.
ASSERT(ui32Delay <= AON_RTC_CONFIG_DELAY_144);
ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL);
ui32Cfg &= ~(AON_RTC_CTL_EV_DELAY_M);
ui32Cfg |= (ui32Delay << AON_RTC_CTL_EV_DELAY_S);
HWREG(AON_RTC_BASE + AON_RTC_O_CTL) = ui32Cfg;
}
//*****************************************************************************
//
//! \brief Configure the source of the combined event.
//!
//! A combined delayed event can be generated from a combination of the three
//! delayed events. Delayed events form the specified channels are OR'ed
//! together to generate the combined event.
//!
//! \param ui32Channels specifies the channels that are to be used for
//! generating the combined event.
//! The parameter must be the bitwise OR of any of the following:
//! - \ref AON_RTC_CH0
//! - \ref AON_RTC_CH1
//! - \ref AON_RTC_CH2
//! - \ref AON_RTC_CH_NONE
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
AONRTCCombinedEventConfig(uint32_t ui32Channels)
{
uint32_t ui32Cfg;
// Check the arguments.
ASSERT( (ui32Channels & (AON_RTC_CH0 | AON_RTC_CH1 | AON_RTC_CH2)) ||
(ui32Channels == AON_RTC_CH_NONE) );
ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL);
ui32Cfg &= ~(AON_RTC_CTL_COMB_EV_MASK_M);
ui32Cfg |= (ui32Channels << AON_RTC_CTL_COMB_EV_MASK_S);
HWREG(AON_RTC_BASE + AON_RTC_O_CTL) = ui32Cfg;
}
//*****************************************************************************
//
//! \brief Clear event from a specified channel.
//!
//! In case of an active event from the specified channel, the event
//! will be cleared (de-asserted).
//!
//! \param ui32Channel clears the event from one or more RTC channels:
//! - \ref AON_RTC_CH0
//! - \ref AON_RTC_CH1
//! - \ref AON_RTC_CH2
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
AONRTCEventClear(uint32_t ui32Channel)
{
// Check the arguments.
ASSERT((ui32Channel == AON_RTC_CH0) ||
(ui32Channel == AON_RTC_CH1) ||
(ui32Channel == AON_RTC_CH2));
if(ui32Channel & AON_RTC_CH0)
{
HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH0;
}
if(ui32Channel & AON_RTC_CH1)
{
HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH1;
}
if(ui32Channel & AON_RTC_CH2)
{
HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH2;
}
}
//*****************************************************************************
//
//! \brief Get event status for a specified channel.
//!
//! In case of an active event from the specified channel,
//! this call will return \c true otherwise \c false.
//!
//! \param ui32Channel specifies the channel from which to query the event state.
//! The parameter must be one (and only one) of the following:
//! - \ref AON_RTC_CH0
//! - \ref AON_RTC_CH1
//! - \ref AON_RTC_CH2
//!
//! \return Returns \c true if an event has occurred for the given channel,
//! otherwise \c false.
//
//*****************************************************************************
__STATIC_INLINE bool
AONRTCEventGet(uint32_t ui32Channel)
{
uint32_t uint32Event = 0;
// Check the arguments.
ASSERT((ui32Channel == AON_RTC_CH0) ||
(ui32Channel == AON_RTC_CH1) ||
(ui32Channel == AON_RTC_CH2));
if(ui32Channel & AON_RTC_CH0)
{
uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH0_BITN);
}
if(ui32Channel & AON_RTC_CH1)
{
uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH1_BITN);
}
if(ui32Channel & AON_RTC_CH2)
{
uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH2_BITN);
}
return(uint32Event);
}
//*****************************************************************************
//
//! \brief Get integer part (seconds) of RTC free-running timer.
//!
//! Get the value in seconds of RTC free-running timer, i.e. the integer part.
//! The fractional part is returned from a call to AONRTCFractionGet().
//!
//! \note It is recommended to use \ref AONRTCCurrentCompareValueGet() instead
//! of this function if the <16.16> format is sufficient.
//!
//! \note To read a consistent pair of integer and fractional parts,
//! \ref AONRTCSecGet() must be called first to trigger latching of the
//! fractional part, which is then read by \ref AONRTCFractionGet(). Interrupts
//! must be disabled to ensure that these operations are performed atomically.
//!
//! \return Returns the integer part of RTC free running timer.
//!
//! \sa \ref AONRTCFractionGet() \ref AONRTCCurrentCompareValueGet()
//
//*****************************************************************************
__STATIC_INLINE uint32_t
AONRTCSecGet(void)
{
// The following read gets the seconds, but also latches the fractional
// part.
return(HWREG(AON_RTC_BASE + AON_RTC_O_SEC));
}
//*****************************************************************************
//
//! \brief Get fractional part (sub-seconds) of RTC free-running timer.
//!
//! Get the value of the fractional part of RTC free-running timer, i.e. the
//! sub-second part.
//!
//! \note It is recommended to use \ref AONRTCCurrentCompareValueGet() instead
//! of this function if the <16.16> format is sufficient.
//!
//! \note To read a consistent pair of integer and fractional parts,
//! \ref AONRTCSecGet() must be called first to trigger latching of the
//! fractional part, which is then read by \ref AONRTCFractionGet(). Interrupts
//! must be disabled to ensure that these operations are performed atomically.
//!
//! \return Returns the fractional part of RTC free running timer.
//!
//! \sa \ref AONRTCSecGet() \ref AONRTCCurrentCompareValueGet()
//
//*****************************************************************************
__STATIC_INLINE uint32_t
AONRTCFractionGet(void)
{
// Note1: It is recommended to use AON RTCCurrentCompareValueGet() instead
// of this function if the <16.16> format is sufficient.
// Note2: AONRTCSecGet() must be called before this function to get a
// consistent reading.
// Note3: Interrupts must be disabled between the call to AONRTCSecGet() and this
// call since there are interrupt functions that reads AON_RTC_O_SEC
return(HWREG(AON_RTC_BASE + AON_RTC_O_SUBSEC));
}
//*****************************************************************************
//
//! \brief Get the sub second increment of the RTC.
//!
//! Get the value of the sub-second increment which is added to the RTC
//! absolute time on every clock tick.
//!
//! \note For a precise and temperature independent LF clock (e.g. an LF XTAL)
//! this value would stay the same across temperature. For temperatue
//! dependent clock sources like an RC oscillator, this value will change
//! over time if the application includes functionality for doing temperature
//! compensation of the RTC clock source. The default value corresponds to a
//! LF clock frequency of exactly 32.768 kHz.
//!
//! \return Returns the sub-second increment of the RTC added to the overall
//! value on every RTC clock tick.
//
//*****************************************************************************
__STATIC_INLINE uint32_t
AONRTCSubSecIncrGet(void)
{
return(HWREG(AON_RTC_BASE + AON_RTC_O_SUBSECINC));
}
//*****************************************************************************
//
//! \brief Set operational mode of channel 1.
//!
//! Set the operational mode of channel 1. It can be capture or compare mode.
//! In capture mode, an external event causes the value of the free running
//! counter to be stored, to remember the time of the event.
//!
//! \note The default mode is compare.
//!
//! \param ui32Mode specifies the mode for channel 1.
//! The parameter must be one of the following:
//! - \ref AON_RTC_MODE_CH1_CAPTURE
//! - \ref AON_RTC_MODE_CH1_COMPARE
//!
//! \return None
//!
//! \sa AONRTCModeCh1Get()
//
//*****************************************************************************
__STATIC_INLINE void
AONRTCModeCh1Set(uint32_t ui32Mode)
{
// Check the arguments.
ASSERT((ui32Mode == AON_RTC_MODE_CH1_CAPTURE) ||
(ui32Mode == AON_RTC_MODE_CH1_COMPARE));
HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_CAPT_EN_BITN) = ui32Mode;
}
//*****************************************************************************
//
//! \brief Get operational mode of channel 1.
//!
//! Get the operational mode of channel 1. It can be capture or compare mode.
//! In capture mode, an external event causes the value of the free running
//! counter to be stored, to remember the time of the event.
//!
//! \return Returns the operational mode of channel 1, one of:
//! - \ref AON_RTC_MODE_CH1_CAPTURE
//! - \ref AON_RTC_MODE_CH1_COMPARE
//!
//! \sa AONRTCModeCh1Set()
//
//*****************************************************************************
__STATIC_INLINE uint32_t
AONRTCModeCh1Get(void)
{
return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_CAPT_EN_BITN));
}
//*****************************************************************************
//
//! \brief Set operational mode of channel 2.
//!
//! Set the operational mode of channel 2. It can be in continuous compare
//! mode or normal compare mode.
//! In continuous mode, a value is automatically incremented to the channel 2
//! compare register, upon a channel 2 compare event. This allows channel 2 to
//! generate a series of completely equidistant events.
//! The increment value is set by the AONRTCIncValueCh2Set() call.
//!
//! \note The default mode is normal compare.
//!
//! \param ui32Mode specifies the mode for channel 2.
//! The parameter must be one of the following:
//! - \ref AON_RTC_MODE_CH2_CONTINUOUS
//! - \ref AON_RTC_MODE_CH2_NORMALCOMPARE
//!
//! \return None
//!
//! \sa AONRTCIncValueCh2Set(), AONRTCIncValueCh2Get()
//
//*****************************************************************************
__STATIC_INLINE void
AONRTCModeCh2Set(uint32_t ui32Mode)
{
// Check the arguments.
ASSERT((ui32Mode == AON_RTC_MODE_CH2_CONTINUOUS) ||
(ui32Mode == AON_RTC_MODE_CH2_NORMALCOMPARE));
HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_CONT_EN_BITN) = ui32Mode;
}
//*****************************************************************************
//
//! \brief Get operational mode of channel 2.
//!
//! Get the operational mode of channel 2. It can be in continuous compare
//! mode or normal compare mode.
//! In continuous mode, a value is automatically incremented to the channel 2
//! compare register, upon a channel 2 compare event. This allows channel 2 to
//! generate a series of completely equidistant events.
//! The increment value is set by the AONRTCIncValueCh2Set() call.
//!
//! \return Returns the operational mode of channel 2, i.e. one of:
//! - \ref AON_RTC_MODE_CH2_CONTINUOUS
//! - \ref AON_RTC_MODE_CH2_NORMALCOMPARE
//!
//! \sa AONRTCIncValueCh2Set(), AONRTCIncValueCh2Get()
//
//*****************************************************************************
__STATIC_INLINE uint32_t
AONRTCModeCh2Get(void)
{
return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_CONT_EN_BITN));
}
//*****************************************************************************
//
//! \brief Enable event operation for the specified channel.
//!
//! Enable the event generation for the specified channel.
//!
//! \note The RTC free running clock must also be enabled globally using the
//! AONRTCEnable() call.
//!
//! \param ui32Channel specifies one or more channels to enable:
//! - \ref AON_RTC_CH0
//! - \ref AON_RTC_CH1
//! - \ref AON_RTC_CH2
//!
//! \return None
//!
//! \sa AONRTCEnable()
//
//*****************************************************************************
__STATIC_INLINE void
AONRTCChannelEnable(uint32_t ui32Channel)
{
// Check the arguments.
ASSERT((ui32Channel == AON_RTC_CH0) ||
(ui32Channel == AON_RTC_CH1) ||
(ui32Channel == AON_RTC_CH2));
if(ui32Channel & AON_RTC_CH0)
{
HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN) = 1;
}
if(ui32Channel & AON_RTC_CH1)
{
HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN) = 1;
}
if(ui32Channel & AON_RTC_CH2)
{
HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN) = 1;
}
}
//*****************************************************************************
//
//! \brief Disable event operation for the specified channel.
//!
//! Disable the event generation for the specified channel.
//!
//! \note The RTC free running clock can also be disabled globally using the
//! AONRTCDisable() call.
//!
//! \param ui32Channel specifies one or more channels to disable:
//! - \ref AON_RTC_CH0
//! - \ref AON_RTC_CH1
//! - \ref AON_RTC_CH2
//!
//! \return None
//!
//! \sa AONRTCDisable()
//
//*****************************************************************************
__STATIC_INLINE void
AONRTCChannelDisable(uint32_t ui32Channel)
{
// Check the arguments.
ASSERT((ui32Channel == AON_RTC_CH0) ||
(ui32Channel == AON_RTC_CH1) ||
(ui32Channel == AON_RTC_CH2));
if(ui32Channel & AON_RTC_CH0)
{
HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN) = 0;
}
if(ui32Channel & AON_RTC_CH1)
{
HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN) = 0;
}
if(ui32Channel & AON_RTC_CH2)
{
HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN) = 0;
}
}
//*****************************************************************************
//
//! \brief Set the compare value for the given channel.
//!
//! Set compare value for the specified channel.
//!
//! The format of the compare value is a 16 bit integer and 16 bit fractional
//! format <16 sec.16 subsec>. The current value of the RTC counter
//! can be retrieved in a format compatible to the compare register using
//! \ref AONRTCCurrentCompareValueGet()
//!
//! \param ui32Channel specifies one or more channels to set compare value for:
//! - \ref AON_RTC_CH0
//! - \ref AON_RTC_CH1
//! - \ref AON_RTC_CH2
//! \param ui32CompValue is the compare value to set for the specified channel.
//! - Format: <16 sec.16 subsec>
//!
//! \return None
//!
//! \sa AONRTCCurrentCompareValueGet()
//
//*****************************************************************************
__STATIC_INLINE void
AONRTCCompareValueSet(uint32_t ui32Channel, uint32_t ui32CompValue)
{
// Check the arguments.
ASSERT((ui32Channel == AON_RTC_CH0) ||
(ui32Channel == AON_RTC_CH1) ||
(ui32Channel == AON_RTC_CH2));
if(ui32Channel & AON_RTC_CH0)
{
HWREG(AON_RTC_BASE + AON_RTC_O_CH0CMP) = ui32CompValue;
}
if(ui32Channel & AON_RTC_CH1)
{
HWREG(AON_RTC_BASE + AON_RTC_O_CH1CMP) = ui32CompValue;
}
if(ui32Channel & AON_RTC_CH2)
{
HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMP) = ui32CompValue;
}
}
//*****************************************************************************
//
//! \brief Get the compare value for the given channel.
//!
//! Get compare value for the specified channel.
//!
//! \param ui32Channel specifies a channel.
//! The parameter must be one (and only one) of the following:
//! - \ref AON_RTC_CH0
//! - \ref AON_RTC_CH1
//! - \ref AON_RTC_CH2
//!
//! \return Returns the stored compare value for the given channel.
//
//*****************************************************************************
__STATIC_INLINE uint32_t
AONRTCCompareValueGet(uint32_t ui32Channel)
{
uint32_t ui32Value = 0;
// Check the arguments
ASSERT((ui32Channel == AON_RTC_CH0) ||
(ui32Channel == AON_RTC_CH1) ||
(ui32Channel == AON_RTC_CH2));
if(ui32Channel & AON_RTC_CH0)
{
ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH0CMP);
}
if(ui32Channel & AON_RTC_CH1)
{
ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH1CMP);
}
if(ui32Channel & AON_RTC_CH2)
{
ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMP);
}
return(ui32Value);
}
//*****************************************************************************
//
//! \brief Get the current value of the RTC counter in a format that matches
//! RTC compare values.
//!
//! The compare value registers contains 16 integer and 16 fractional bits.
//! This function will return the current value of the RTC counter in an
//! identical format.
//!
//! \return Returns the current value of the RTC counter in a <16.16> format
//! (SEC[15:0].SUBSEC[31:16]).
//!
//! \sa \ref AONRTCCompareValueSet()
//
//*****************************************************************************
__STATIC_INLINE uint32_t
AONRTCCurrentCompareValueGet( void )
{
return ( HWREG( AON_RTC_BASE + AON_RTC_O_TIME ));
}
//*****************************************************************************
//
//! \brief Get the current 64-bit value of the RTC counter.
//!
//! \note Reading SEC both before and after SUBSEC in order to detect if SEC
//! incremented while reading SUBSEC. If SEC incremented, we can't be sure
//! which SEC the SUBSEC belongs to, so repeating the sequence then.
//!
//! \return Returns the current value of the RTC counter in a 64-bits format
//! (SEC[31:0].SUBSEC[31:0]).
//
//*****************************************************************************
extern uint64_t AONRTCCurrent64BitValueGet(void);
//*****************************************************************************
//
//! \brief Set the channel 2 increment value when operating in continuous mode.
//!
//! Set the channel 2 increment value when operating in continuous mode.
//! The specified value is automatically incremented to the channel 2 compare
//! register, upon a channel 2 compare event. This allows channel 2 to generate
//! a series of completely equidistant events.
//!
//! \param ui32IncValue is the increment value when operating in continuous mode.
//!
//! \return None
//!
//! \sa AONRTCIncValueCh2Get()
//
//*****************************************************************************
__STATIC_INLINE void
AONRTCIncValueCh2Set(uint32_t ui32IncValue)
{
HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMPINC) = ui32IncValue;
}
//*****************************************************************************
//
//! \brief Get the channel2 increment value when operating in continuous mode.
//!
//! Get the channel 2 increment value, when channel 2 is operating in
//! continuous mode.
//! This value is automatically incremented to the channel 2 compare
//! register, upon a channel 2 compare event. This allows channel 2 to
//! generate a series of completely equidistant events.
//!
//! \return Returns the channel 2 increment value when operating in continuous
//! mode.
//!
//! \sa AONRTCIncValueCh2Set()
//
//*****************************************************************************
__STATIC_INLINE uint32_t
AONRTCIncValueCh2Get(void)
{
return(HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMPINC));
}
//*****************************************************************************
//
//! \brief Get the channel 1 capture value.
//!
//! Get the channel 1 capture value.
//! The upper 16 bits of the returned value is the lower 16 bits of the
//! integer part of the RTC timer. The lower 16 bits of the returned part
//! is the upper 16 bits of the fractional part.
//!
//! \return Returns the channel 1 capture value.
//
//*****************************************************************************
__STATIC_INLINE uint32_t
AONRTCCaptureValueCh1Get(void)
{
return(HWREG(AON_RTC_BASE + AON_RTC_O_CH1CAPT));
}
//*****************************************************************************
//
// Support for DriverLib in ROM:
// Redirect to implementation in ROM when available.
//
//*****************************************************************************
#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
#include "../driverlib/rom.h"
#ifdef ROM_AONRTCCurrent64BitValueGet
#undef AONRTCCurrent64BitValueGet
#define AONRTCCurrent64BitValueGet ROM_AONRTCCurrent64BitValueGet
#endif
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __AON_RTC_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

41
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc_doc.h
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@ -1,41 +0,0 @@
/******************************************************************************
* Filename: aon_rtc_doc.h
* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016)
* Revision: 45971
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//! \addtogroup aonrtc_api
//! @{
//! \section sec_aonrtc Introduction
//!
//! \note If using TI-RTOS then only TI-RTOS is allowed to configure the RTC timer!
//! @}

337
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_adc.c
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@ -1,337 +0,0 @@
/******************************************************************************
* Filename: aux_adc.c
* Revised: 2017-11-20 14:31:35 +0100 (Mon, 20 Nov 2017)
* Revision: 50315
*
* Description: Driver for the AUX Time to Digital Converter interface.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "aux_adc.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_aux_sysif.h"
#include "../inc/hw_fcfg1.h"
#include "adi.h"
#include "event.h"
//*****************************************************************************
//
// Handle support for DriverLib in ROM:
// This section will undo prototype renaming made in the header file
//
//*****************************************************************************
#if !defined(DOXYGEN)
#undef AUXADCDisable
#define AUXADCDisable NOROM_AUXADCDisable
#undef AUXADCEnableAsync
#define AUXADCEnableAsync NOROM_AUXADCEnableAsync
#undef AUXADCEnableSync
#define AUXADCEnableSync NOROM_AUXADCEnableSync
#undef AUXADCDisableInputScaling
#define AUXADCDisableInputScaling NOROM_AUXADCDisableInputScaling
#undef AUXADCFlushFifo
#define AUXADCFlushFifo NOROM_AUXADCFlushFifo
#undef AUXADCReadFifo
#define AUXADCReadFifo NOROM_AUXADCReadFifo
#undef AUXADCPopFifo
#define AUXADCPopFifo NOROM_AUXADCPopFifo
#undef AUXADCGetAdjustmentGain
#define AUXADCGetAdjustmentGain NOROM_AUXADCGetAdjustmentGain
#undef AUXADCGetAdjustmentOffset
#define AUXADCGetAdjustmentOffset NOROM_AUXADCGetAdjustmentOffset
#undef AUXADCValueToMicrovolts
#define AUXADCValueToMicrovolts NOROM_AUXADCValueToMicrovolts
#undef AUXADCMicrovoltsToValue
#define AUXADCMicrovoltsToValue NOROM_AUXADCMicrovoltsToValue
#undef AUXADCAdjustValueForGainAndOffset
#define AUXADCAdjustValueForGainAndOffset NOROM_AUXADCAdjustValueForGainAndOffset
#undef AUXADCUnadjustValueForGainAndOffset
#define AUXADCUnadjustValueForGainAndOffset NOROM_AUXADCUnadjustValueForGainAndOffset
#endif
//*****************************************************************************
//
// Disables the ADC
//
//*****************************************************************************
void
AUXADCDisable(void)
{
// Disable the ADC reference
ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, ADI_4_AUX_ADCREF0_EN_M | ADI_4_AUX_ADCREF0_REF_ON_IDLE_M | ADI_4_AUX_ADCREF0_SRC_M);
// Assert reset and disable the ADC
ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M | ADI_4_AUX_ADC0_SMPL_MODE_M | ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M);
// Ensure that scaling is enabled by default before next use of the ADC
ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADC1, ADI_4_AUX_ADC1_SCALE_DIS_M);
// Flush the FIFO before disabling the clocks
HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3)
HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1)
// Disable the ADC clock (no need to wait since IOB_WUC_ADCCLKCTL_ACK goes low immediately)
HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) = 0;
// Disable the ADC data interface
HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = 0;
}
//*****************************************************************************
//
// Enables the ADC for asynchronous operation
//
//*****************************************************************************
void
AUXADCEnableAsync(uint32_t refSource, uint32_t trigger)
{
// Enable the ADC reference, with the following options:
// - SRC: Set when using relative reference
// - REF_ON_IDLE: Always cleared since there is no idle state in asynchronous operation
ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, refSource | ADI_4_AUX_ADCREF0_EN_M);
// Enable the ADC clock
HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) = AUX_SYSIF_ADCCLKCTL_REQ_M;
while (!(HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) & AUX_SYSIF_ADCCLKCTL_ACK_M));
// Enable the ADC data interface
if (trigger == AUXADC_TRIGGER_MANUAL) {
// Manual trigger: No need to configure event routing from GPT
HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT | AUX_ANAIF_ADCCTL_CMD_EN;
} else {
// GPT trigger: Configure event routing via MCU_EV to the AUX domain
HWREG(EVENT_BASE + EVENT_O_AUXSEL0) = trigger;
HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_MCU_EV | AUX_ANAIF_ADCCTL_CMD_EN;
}
// Configure the ADC
ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_SMPL_MODE_M);
// Release reset and enable the ADC
ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M);
}
//*****************************************************************************
//
// Enables the ADC for synchronous operation
//
//*****************************************************************************
void
AUXADCEnableSync(uint32_t refSource, uint32_t sampleTime, uint32_t trigger)
{
// Enable the ADC reference, with the following options:
// - SRC: Set when using relative reference
// - REF_ON_IDLE: Set when using fixed reference and sample time < 21.3 us
uint8_t adcref0 = refSource | ADI_4_AUX_ADCREF0_EN_M;
if (!refSource && (sampleTime < AUXADC_SAMPLE_TIME_21P3_US)) {
adcref0 |= ADI_4_AUX_ADCREF0_REF_ON_IDLE_M;
}
ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, adcref0);
// Enable the ADC clock
HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) = AUX_SYSIF_ADCCLKCTL_REQ_M;
while (!(HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) & AUX_SYSIF_ADCCLKCTL_ACK_M));
// Enable the ADC data interface
if (trigger == AUXADC_TRIGGER_MANUAL) {
// Manual trigger: No need to configure event routing from GPT
HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT | AUX_ANAIF_ADCCTL_CMD_EN;
} else {
// GPT trigger: Configure event routing via MCU_EV to the AUX domain
HWREG(EVENT_BASE + EVENT_O_AUXSEL0) = trigger;
HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_MCU_EV | AUX_ANAIF_ADCCTL_CMD_EN;
}
// Configure the ADC
ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, sampleTime << ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S);
// Release reset and enable the ADC
ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M);
}
//*****************************************************************************
//
// Disables scaling of the ADC input
//
//*****************************************************************************
void
AUXADCDisableInputScaling(void)
{
ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC1, ADI_4_AUX_ADC1_SCALE_DIS_M);
}
//*****************************************************************************
//
// Flushes the ADC FIFO
//
//*****************************************************************************
void
AUXADCFlushFifo(void)
{
HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3)
HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1)
}
//*****************************************************************************
//
// Waits for and returns the first sample in the ADC FIFO
//
//*****************************************************************************
uint32_t
AUXADCReadFifo(void) {
// Wait until there is at least one sample in the FIFO
while (HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFOSTAT) & AUX_ANAIF_ADCFIFOSTAT_EMPTY_M);
// Return the first sample from the FIFO
return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO);
}
//*****************************************************************************
//
// Returns the first sample in the ADC FIFO, without waiting
//
//*****************************************************************************
uint32_t
AUXADCPopFifo(void) {
// Return the first sample from the FIFO. If the FIFO is empty, this
// generates ADC FIFO underflow
return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO);
}
//*****************************************************************************
//
// Returns the gain value used when adjusting for ADC gain/offset
//
//*****************************************************************************
int32_t
AUXADCGetAdjustmentGain(uint32_t refSource)
{
int32_t gain;
if (refSource == AUXADC_REF_FIXED) {
// AUXADC_REF_FIXED ==> ABS_GAIN
gain = (HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_ABS_GAIN) & FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M) >> FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S;
} else {
// AUXADC_REF_VDDS_REL ==> REL_GAIN
gain = (HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_REL_GAIN) & FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M) >> FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S;
}
return gain;
}
//*****************************************************************************
//
// Returns the offset value used when adjusting for ADC gain/offset
//
//*****************************************************************************
int32_t
AUXADCGetAdjustmentOffset(uint32_t refSource)
{
int8_t offset;
if ( refSource == AUXADC_REF_FIXED ) {
// AUXADC_REF_FIXED ==> ABS_OFFSET
offset = HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_OFFSET_INT) >> FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S;
} else {
// AUXADC_REF_VDDS_REL ==> REL_OFFSET
offset = HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_OFFSET_INT) >> FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S;
}
return offset;
}
//*****************************************************************************
//
// Converts an "ideal" ADC value to microvolts
//
//*****************************************************************************
int32_t
AUXADCValueToMicrovolts(int32_t fixedRefVoltage, int32_t adcValue)
{
// Chop off 4 bits during calculations to avoid 32-bit overflow
fixedRefVoltage >>= 4;
return (((adcValue * fixedRefVoltage) + 2047) / 4095) << 4;
}
//*****************************************************************************
//
// Converts a number of microvolts to corresponding "ideal" ADC value
//
//*****************************************************************************
int32_t
AUXADCMicrovoltsToValue(int32_t fixedRefVoltage, int32_t microvolts)
{
// Chop off 4 bits during calculations to avoid 32-bit overflow
fixedRefVoltage >>= 4;
microvolts >>= 4;
return ((microvolts * 4095) + (fixedRefVoltage / 2)) / fixedRefVoltage;
}
//*****************************************************************************
//
// Performs ADC value gain and offset adjustment
//
//*****************************************************************************
int32_t
AUXADCAdjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset)
{
// Apply gain and offset adjustment
adcValue = (((adcValue + offset) * gain) + 16384) / 32768;
// Saturate
if (adcValue < 0) {
return 0;
} else if (adcValue > 4095) {
return 4095;
} else {
return adcValue;
}
}
//*****************************************************************************
//
// Performs the inverse of the ADC value gain and offset adjustment
//
//*****************************************************************************
int32_t
AUXADCUnadjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset)
{
// Apply inverse gain and offset adjustment
adcValue = (((adcValue * 32768) + (gain / 2)) / gain) - offset;
// Saturate
if (adcValue < 0) {
return 0;
} else if (adcValue > 4095) {
return 4095;
} else {
return adcValue;
}
}

599
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_adc.h
View file

@ -1,599 +0,0 @@
/******************************************************************************
* Filename: aux_adc.h
* Revised: 2018-02-07 09:45:39 +0100 (Wed, 07 Feb 2018)
* Revision: 51437
*
* Description: Defines and prototypes for the AUX Analog-to-Digital
* Converter
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup aux_group
//! @{
//! \addtogroup auxadc_api
//! @{
//
//*****************************************************************************
#ifndef __AUX_ADC_H__
#define __AUX_ADC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdbool.h>
#include <stdint.h>
#include "../inc/hw_types.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_event.h"
#include "../inc/hw_adi.h"
#include "../inc/hw_adi_4_aux.h"
#include "../inc/hw_aux_anaif.h"
#include "rom.h"
//*****************************************************************************
//
// Support for DriverLib in ROM:
// This section renames all functions that are not "static inline", so that
// calling these functions will default to implementation in flash. At the end
// of this file a second renaming will change the defaults to implementation in
// ROM for available functions.
//
// To force use of the implementation in flash, e.g. for debugging:
// - Globally: Define DRIVERLIB_NOROM at project level
// - Per function: Use prefix "NOROM_" when calling the function
//
//*****************************************************************************
#if !defined(DOXYGEN)
#define AUXADCDisable NOROM_AUXADCDisable
#define AUXADCEnableAsync NOROM_AUXADCEnableAsync
#define AUXADCEnableSync NOROM_AUXADCEnableSync
#define AUXADCDisableInputScaling NOROM_AUXADCDisableInputScaling
#define AUXADCFlushFifo NOROM_AUXADCFlushFifo
#define AUXADCReadFifo NOROM_AUXADCReadFifo
#define AUXADCPopFifo NOROM_AUXADCPopFifo
#define AUXADCGetAdjustmentGain NOROM_AUXADCGetAdjustmentGain
#define AUXADCGetAdjustmentOffset NOROM_AUXADCGetAdjustmentOffset
#define AUXADCValueToMicrovolts NOROM_AUXADCValueToMicrovolts
#define AUXADCMicrovoltsToValue NOROM_AUXADCMicrovoltsToValue
#define AUXADCAdjustValueForGainAndOffset NOROM_AUXADCAdjustValueForGainAndOffset
#define AUXADCUnadjustValueForGainAndOffset NOROM_AUXADCUnadjustValueForGainAndOffset
#endif
//*****************************************************************************
//
// Defines for ADC reference sources.
//
//*****************************************************************************
#define AUXADC_REF_FIXED (0 << ADI_4_AUX_ADCREF0_SRC_S)
#define AUXADC_REF_VDDS_REL (1 << ADI_4_AUX_ADCREF0_SRC_S)
//*****************************************************************************
//
// Defines for the ADC FIFO status bits.
//
//*****************************************************************************
#define AUXADC_FIFO_EMPTY_M (AUX_ANAIF_ADCFIFOSTAT_EMPTY_M)
#define AUXADC_FIFO_ALMOST_FULL_M (AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M)
#define AUXADC_FIFO_FULL_M (AUX_ANAIF_ADCFIFOSTAT_FULL_M)
#define AUXADC_FIFO_UNDERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M)
#define AUXADC_FIFO_OVERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M)
//*****************************************************************************
//
// Defines for supported ADC triggers.
//
//*****************************************************************************
#define AUXADC_TRIGGER_MANUAL (EVENT_AUXSEL0_EV_NONE)
#define AUXADC_TRIGGER_GPT0A (EVENT_AUXSEL0_EV_GPT0A)
#define AUXADC_TRIGGER_GPT0B (EVENT_AUXSEL0_EV_GPT0B)
#define AUXADC_TRIGGER_GPT1A (EVENT_AUXSEL0_EV_GPT1A)
#define AUXADC_TRIGGER_GPT1B (EVENT_AUXSEL0_EV_GPT1B)
#define AUXADC_TRIGGER_GPT2A (EVENT_AUXSEL0_EV_GPT2A)
#define AUXADC_TRIGGER_GPT2B (EVENT_AUXSEL0_EV_GPT2B)
#define AUXADC_TRIGGER_GPT3A (EVENT_AUXSEL0_EV_GPT3A)
#define AUXADC_TRIGGER_GPT3B (EVENT_AUXSEL0_EV_GPT3B)
// Additional triggers specific for cc26x2 and cc13x2 devices
#define AUXADC_TRIGGER_GPT0A_CMP (EVENT_AUXSEL0_EV_GPT0A_CMP)
#define AUXADC_TRIGGER_GPT0B_CMP (EVENT_AUXSEL0_EV_GPT0B_CMP)
#define AUXADC_TRIGGER_GPT1A_CMP (EVENT_AUXSEL0_EV_GPT1A_CMP)
#define AUXADC_TRIGGER_GPT1B_CMP (EVENT_AUXSEL0_EV_GPT1B_CMP)
#define AUXADC_TRIGGER_GPT2A_CMP (EVENT_AUXSEL0_EV_GPT2A_CMP)
#define AUXADC_TRIGGER_GPT2B_CMP (EVENT_AUXSEL0_EV_GPT2B_CMP)
#define AUXADC_TRIGGER_GPT3A_CMP (EVENT_AUXSEL0_EV_GPT3A_CMP)
#define AUXADC_TRIGGER_GPT3B_CMP (EVENT_AUXSEL0_EV_GPT3B_CMP)
//*****************************************************************************
//
// Defines for ADC sampling type for synchronous operation.
//
//*****************************************************************************
#define AUXADC_SAMPLE_TIME_2P7_US 3
#define AUXADC_SAMPLE_TIME_5P3_US 4
#define AUXADC_SAMPLE_TIME_10P6_US 5
#define AUXADC_SAMPLE_TIME_21P3_US 6
#define AUXADC_SAMPLE_TIME_42P6_US 7
#define AUXADC_SAMPLE_TIME_85P3_US 8
#define AUXADC_SAMPLE_TIME_170_US 9
#define AUXADC_SAMPLE_TIME_341_US 10
#define AUXADC_SAMPLE_TIME_682_US 11
#define AUXADC_SAMPLE_TIME_1P37_MS 12
#define AUXADC_SAMPLE_TIME_2P73_MS 13
#define AUXADC_SAMPLE_TIME_5P46_MS 14
#define AUXADC_SAMPLE_TIME_10P9_MS 15
//*****************************************************************************
//
// Equivalent voltages for fixed ADC reference, in microvolts.
//
//*****************************************************************************
#define AUXADC_FIXED_REF_VOLTAGE_NORMAL 4300000
#define AUXADC_FIXED_REF_VOLTAGE_UNSCALED 1478500
//*****************************************************************************
//
// API Functions and prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Disables the ADC.
//!
//! This function must be called:
//! - Before re-enabling the ADC using \ref AUXADCEnableAsync() or
//! \ref AUXADCEnableSync()
//! - Before entering system standby
//
//*****************************************************************************
extern void AUXADCDisable(void);
//*****************************************************************************
//
//! \brief Enables the ADC for asynchronous operation.
//!
//! In asynchronous operation, the ADC samples continuously between
//! conversions.
//!
//! The ADC trigger starts the conversion. Note that the first conversion may
//! be invalid if the sampling period is too short.
//!
//! ADC input scaling is enabled by default after device reset, and is also re-
//! enabled by \ref AUXADCDisable(). To disable input scaling, call
//! \ref AUXADCDisableInputScaling() before calling \ref AUXADCEnableAsync().
//!
//! \param refSource
//! ADC reference source:
//! - \ref AUXADC_REF_FIXED (nominally 4.3 V)
//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS)
//! \param trigger
//! ADC conversion trigger:
//! - \ref AUXADC_TRIGGER_MANUAL
//! - \ref AUXADC_TRIGGER_GPT0A
//! - \ref AUXADC_TRIGGER_GPT0B
//! - \ref AUXADC_TRIGGER_GPT1A
//! - \ref AUXADC_TRIGGER_GPT1B
//! - \ref AUXADC_TRIGGER_GPT2A
//! - \ref AUXADC_TRIGGER_GPT2B
//! - \ref AUXADC_TRIGGER_GPT3A
//! - \ref AUXADC_TRIGGER_GPT3B
//
//*****************************************************************************
extern void AUXADCEnableAsync(uint32_t refSource, uint32_t trigger);
//*****************************************************************************
//
//! \brief Enables the ADC for synchronous operation.
//!
//! In synchronous operation, the ADC is idle between a conversion and
//! subsequent samplings.
//!
//! The ADC trigger starts sampling with specified duration, followed by the
//! conversion. Note that the first conversion may be invalid if the initial
//! sampling period is too short.
//!
//! ADC input scaling is enabled by default after device reset, and is also re-
//! enabled by \ref AUXADCDisable(). To disable input scaling, call
//! \ref AUXADCDisableInputScaling() before calling \ref AUXADCEnableSync().
//!
//! \param refSource
//! ADC reference source:
//! - \ref AUXADC_REF_FIXED (nominally 4.3 V)
//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS)
//! \param sampleTime
//! ADC sampling time:
//! - \ref AUXADC_SAMPLE_TIME_2P7_US
//! - \ref AUXADC_SAMPLE_TIME_5P3_US
//! - \ref AUXADC_SAMPLE_TIME_10P6_US
//! - \ref AUXADC_SAMPLE_TIME_21P3_US
//! - \ref AUXADC_SAMPLE_TIME_42P6_US
//! - \ref AUXADC_SAMPLE_TIME_85P3_US
//! - \ref AUXADC_SAMPLE_TIME_170_US
//! - \ref AUXADC_SAMPLE_TIME_341_US
//! - \ref AUXADC_SAMPLE_TIME_682_US
//! - \ref AUXADC_SAMPLE_TIME_1P37_MS
//! - \ref AUXADC_SAMPLE_TIME_2P73_MS
//! - \ref AUXADC_SAMPLE_TIME_5P46_MS
//! - \ref AUXADC_SAMPLE_TIME_10P9_MS
//! \param trigger
//! ADC conversion trigger:
//! - \ref AUXADC_TRIGGER_MANUAL
//! - \ref AUXADC_TRIGGER_GPT0A
//! - \ref AUXADC_TRIGGER_GPT0B
//! - \ref AUXADC_TRIGGER_GPT1A
//! - \ref AUXADC_TRIGGER_GPT1B
//! - \ref AUXADC_TRIGGER_GPT2A
//! - \ref AUXADC_TRIGGER_GPT2B
//! - \ref AUXADC_TRIGGER_GPT3A
//! - \ref AUXADC_TRIGGER_GPT3B
//
//*****************************************************************************
extern void AUXADCEnableSync(uint32_t refSource, uint32_t sampleTime, uint32_t trigger);
//*****************************************************************************
//
//! \brief Disables scaling of the ADC input.
//!
//! By default, the ADC operates internally on a version of the input signal
//! that has been scaled down by a factor <tt>1408 / 4095</tt>. This function
//! disables that scaling, allowing for a trade-off between dynamic range and
//! and resolution.
//!
//! \note This function must only be called while the ADC is disabled, before
//! calling \ref AUXADCEnableSync() or \ref AUXADCEnableAsync().
//! \note Different input maximum ratings apply when input scaling is disabled.
//! Violating these may damage the device.
//
//*****************************************************************************
extern void AUXADCDisableInputScaling(void);
//*****************************************************************************
//
//! \brief Flushes the ADC FIFO.
//!
//! This empties the FIFO and clears the underflow/overflow flags.
//!
//! Note: This function must only be called while the ADC is enabled.
//
//*****************************************************************************
extern void AUXADCFlushFifo(void);
//*****************************************************************************
//
//! \brief Generates a single manual ADC trigger.
//!
//! For synchronous mode, the trigger starts sampling followed by conversion.
//! For asynchronous mode, the trigger starts conversion.
//
//*****************************************************************************
__STATIC_INLINE void
AUXADCGenManualTrigger(void)
{
HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCTRIG) = 0;
}
//*****************************************************************************
//
//! \brief Returns flags indicating the status of the ADC FIFO.
//!
//! The flags indicate FIFO empty, full and almost full, and whether
//! overflow/underflow has occurred.
//!
//! \return
//! A combination (bitwise OR) of the following flags:
//! - \ref AUXADC_FIFO_EMPTY_M
//! - \ref AUXADC_FIFO_ALMOST_FULL_M
//! - \ref AUXADC_FIFO_FULL_M
//! - \ref AUXADC_FIFO_UNDERFLOW_M
//! - \ref AUXADC_FIFO_OVERFLOW_M
//
//*****************************************************************************
__STATIC_INLINE uint32_t
AUXADCGetFifoStatus(void)
{
return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFOSTAT);
}
//*****************************************************************************
//
//! \brief Waits for and returns the first sample in the ADC FIFO.
//!
//! This function waits until there is at least one sample in the ADC FIFO. It
//! then pops and returns the first sample from the FIFO.
//!
//! \note This procedure will deadlock if called without setting up ADC trigger
//! generation in advance. The trigger can either be manual or periodical
//! (using a GPT).
//!
//! \return The first (12-bit) sample from the ADC FIFO
//
//*****************************************************************************
extern uint32_t AUXADCReadFifo(void);
//*****************************************************************************
//
//! \brief Returns the first sample in the ADC FIFO, without waiting.
//!
//! This function does not wait, and must only be called when there is at least
//! one sample in the ADC FIFO. Otherwise the call will generate FIFO underflow
//! (\ref AUXADC_FIFO_UNDERFLOW_M).
//!
//! \return The first (12-bit) sample from the ADC FIFO, or an undefined value
//! if the FIFO is empty
//
//*****************************************************************************
extern uint32_t AUXADCPopFifo(void);
//*****************************************************************************
//
//! \brief Selects internal or external input for the ADC.
//!
//! Note that calling this function also selects the same input for AUX_COMPB.
//!
//! \param input
//! Internal/external input selection:
//! - \ref ADC_COMPB_IN_DCOUPL
//! - \ref ADC_COMPB_IN_VSS
//! - \ref ADC_COMPB_IN_VDDS
//! - \ref ADC_COMPB_IN_AUXIO7
//! - \ref ADC_COMPB_IN_AUXIO6
//! - \ref ADC_COMPB_IN_AUXIO5
//! - \ref ADC_COMPB_IN_AUXIO4
//! - \ref ADC_COMPB_IN_AUXIO3
//! - \ref ADC_COMPB_IN_AUXIO2
//! - \ref ADC_COMPB_IN_AUXIO1
//! - \ref ADC_COMPB_IN_AUXIO0
//
//*****************************************************************************
__STATIC_INLINE void
AUXADCSelectInput(uint32_t input)
{
HapiSelectADCCompBInput(input);
}
//*****************************************************************************
//
//! \brief Returns the gain value used when adjusting for ADC gain/offset.
//!
//! The function returns the gain value to be used with
//! \ref AUXADCAdjustValueForGainAndOffset() or
//! \ref AUXADCUnadjustValueForGainAndOffset(). The gain value is found during
//! chip manufacturing and is stored in the factory configuration, FCFG1.
//!
//! \param refSource
//! ADC reference source:
//! - \ref AUXADC_REF_FIXED (nominally 4.3 V)
//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS)
//!
//! \return
//! The gain value to be used in adjustments
//
//*****************************************************************************
extern int32_t AUXADCGetAdjustmentGain(uint32_t refSource);
//*****************************************************************************
//
//! \brief Returns the offset value used when adjusting for ADC gain/offset.
//!
//! The function returns the offset value to be used with
//! \ref AUXADCAdjustValueForGainAndOffset() or
//! \ref AUXADCUnadjustValueForGainAndOffset(). The offset value is found
//! during chip manufacturing and is stored in the factory configuration,
//! FCFG1.
//!
//! \param refSource
//! ADC reference source:
//! - \ref AUXADC_REF_FIXED (nominally 4.3 V)
//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS)
//!
//! \return
//! The offset value to be used in adjustments
//
//*****************************************************************************
extern int32_t AUXADCGetAdjustmentOffset(uint32_t refSource);
//*****************************************************************************
//
//! \brief Converts an "adjusted" ADC value to microvolts.
//!
//! This function can only be used when measuring with fixed ADC reference
//! (\ref AUXADC_REF_FIXED). The specified reference voltage accounts for
//! whether the sampled ADC input is scaled down before conversion or not.
//!
//! \param fixedRefVoltage
//! Fixed reference voltage, in microvolts
//! - \ref AUXADC_FIXED_REF_VOLTAGE_NORMAL when using scaled input (normal)
//! - \ref AUXADC_FIXED_REF_VOLTAGE_UNSCALED when using unscaled input
//! \param adcValue
//! The ADC value
//!
//! \return
//! The corresponding number of microvolts
//
//*****************************************************************************
extern int32_t AUXADCValueToMicrovolts(int32_t fixedRefVoltage, int32_t adcValue);
//*****************************************************************************
//
//! \brief Converts a number of microvolts to corresponding "adjusted" ADC value.
//!
//! This function can only be used when measuring with fixed ADC reference
//! (\ref AUXADC_REF_FIXED). The specified reference voltage accounts for
//! whether the sampled ADC input is scaled down before conversion or not.
//!
//! \param fixedRefVoltage
//! Fixed reference voltage, in microvolts
//! - \ref AUXADC_FIXED_REF_VOLTAGE_NORMAL when using scaled input (normal)
//! - \ref AUXADC_FIXED_REF_VOLTAGE_UNSCALED when using unscaled input
//! \param microvolts
//! The number of microvolts
//!
//! \return
//! The corresponding expected ADC value (adjusted for ADC gain/offset)
//
//*****************************************************************************
extern int32_t AUXADCMicrovoltsToValue(int32_t fixedRefVoltage, int32_t microvolts);
//*****************************************************************************
//
//! \brief Performs ADC value gain and offset adjustment.
//!
//! This function takes a measured ADC value compensates for the internal gain
//! and offset in the ADC.
//!
//! \param adcValue
//! 12-bit ADC unadjusted value
//! \param gain
//! Gain adjustment value provided by \ref AUXADCGetAdjustmentGain()
//! \param offset
//! Offset adjustment value provided by \ref AUXADCGetAdjustmentOffset()
//!
//! \return
//! 12-bit ADC adjusted value
//
//*****************************************************************************
extern int32_t AUXADCAdjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset);
//*****************************************************************************
//
//! \brief Performs the inverse of the ADC value gain and offset adjustment.
//!
//! This function finds the expected measured ADC value, without gain and
//! offset compensation, for a given "ideal" ADC value. The function can for
//! example be used to find ADC value thresholds to be used in Sensor
//! Controller task configurations.
//!
//! \param adcValue
//! 12-bit ADC adjusted value
//! \param gain
//! Gain adjustment value provided by \ref AUXADCGetAdjustmentGain()
//! \param offset
//! Offset adjustment value provided by \ref AUXADCGetAdjustmentOffset()
//!
//! \return
//! 12-bit ADC unadjusted value
//
//*****************************************************************************
extern int32_t AUXADCUnadjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset);
//*****************************************************************************
//
// Support for DriverLib in ROM:
// Redirect to implementation in ROM when available.
//
//*****************************************************************************
#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
#include "../driverlib/rom.h"
#ifdef ROM_AUXADCDisable
#undef AUXADCDisable
#define AUXADCDisable ROM_AUXADCDisable
#endif
#ifdef ROM_AUXADCEnableAsync
#undef AUXADCEnableAsync
#define AUXADCEnableAsync ROM_AUXADCEnableAsync
#endif
#ifdef ROM_AUXADCEnableSync
#undef AUXADCEnableSync
#define AUXADCEnableSync ROM_AUXADCEnableSync
#endif
#ifdef ROM_AUXADCDisableInputScaling
#undef AUXADCDisableInputScaling
#define AUXADCDisableInputScaling ROM_AUXADCDisableInputScaling
#endif
#ifdef ROM_AUXADCFlushFifo
#undef AUXADCFlushFifo
#define AUXADCFlushFifo ROM_AUXADCFlushFifo
#endif
#ifdef ROM_AUXADCReadFifo
#undef AUXADCReadFifo
#define AUXADCReadFifo ROM_AUXADCReadFifo
#endif
#ifdef ROM_AUXADCPopFifo
#undef AUXADCPopFifo
#define AUXADCPopFifo ROM_AUXADCPopFifo
#endif
#ifdef ROM_AUXADCGetAdjustmentGain
#undef AUXADCGetAdjustmentGain
#define AUXADCGetAdjustmentGain ROM_AUXADCGetAdjustmentGain
#endif
#ifdef ROM_AUXADCGetAdjustmentOffset
#undef AUXADCGetAdjustmentOffset
#define AUXADCGetAdjustmentOffset ROM_AUXADCGetAdjustmentOffset
#endif
#ifdef ROM_AUXADCValueToMicrovolts
#undef AUXADCValueToMicrovolts
#define AUXADCValueToMicrovolts ROM_AUXADCValueToMicrovolts
#endif
#ifdef ROM_AUXADCMicrovoltsToValue
#undef AUXADCMicrovoltsToValue
#define AUXADCMicrovoltsToValue ROM_AUXADCMicrovoltsToValue
#endif
#ifdef ROM_AUXADCAdjustValueForGainAndOffset
#undef AUXADCAdjustValueForGainAndOffset
#define AUXADCAdjustValueForGainAndOffset ROM_AUXADCAdjustValueForGainAndOffset
#endif
#ifdef ROM_AUXADCUnadjustValueForGainAndOffset
#undef AUXADCUnadjustValueForGainAndOffset
#define AUXADCUnadjustValueForGainAndOffset ROM_AUXADCUnadjustValueForGainAndOffset
#endif
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __AUX_ADC_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

41
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@ -1,41 +0,0 @@
/******************************************************************************
* Filename: aux_smph.c
* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016)
* Revision: 47179
*
* Description: Driver for the AUX Semaphore.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "aux_smph.h"
// See aux_smph.h for implementation

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/******************************************************************************
* Filename: aux_smph.h
* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016)
* Revision: 47343
*
* Description: Defines and prototypes for the AUX Semaphore
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup aux_group
//! @{
//! \addtogroup auxsmph_api
//! @{
//
//*****************************************************************************
#ifndef __AUX_SMPH_H__
#define __AUX_SMPH_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdbool.h>
#include <stdint.h>
#include "../inc/hw_types.h"
#include "../inc/hw_aux_smph.h"
#include "../inc/hw_memmap.h"
#include "debug.h"
//*****************************************************************************
//
// General constants and defines
//
//*****************************************************************************
#define AUX_SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed
#define AUX_SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed
//*****************************************************************************
//
// Values that can be passed to AUXSMPHAcquire and AUXSMPHRelease
// as the ui32Semaphore parameter.
//
//*****************************************************************************
#define AUX_SMPH_0 0 // AUX Semaphore 0
#define AUX_SMPH_1 1 // AUX Semaphore 1
#define AUX_SMPH_2 2 // AUX Semaphore 2
#define AUX_SMPH_3 3 // AUX Semaphore 3
#define AUX_SMPH_4 4 // AUX Semaphore 4
#define AUX_SMPH_5 5 // AUX Semaphore 5
#define AUX_SMPH_6 6 // AUX Semaphore 6
#define AUX_SMPH_7 7 // AUX Semaphore 7
//*****************************************************************************
//
// API Functions and prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Acquire an AUX semaphore.
//!
//! This function acquires the given AUX semaphore, blocking the call until
//! the semaphore is available.
//!
//! \note The semaphore can also be acquired by the dedicated Sensor Controller.
//! The System CPU master can thus be competing for the shared resource, i.e.
//! the specified semaphore.
//!
//! \param ui32Semaphore is the semaphore number.
//! - \ref AUX_SMPH_0
//! - \ref AUX_SMPH_1
//! - \ref AUX_SMPH_2
//! - \ref AUX_SMPH_3
//! - \ref AUX_SMPH_4
//! - \ref AUX_SMPH_5
//! - \ref AUX_SMPH_6
//! - \ref AUX_SMPH_7
//!
//! \return None
//!
//! \sa AUXSMPHTryAcquire(), AUXSMPHRelease()
//
//*****************************************************************************
__STATIC_INLINE void
AUXSMPHAcquire(uint32_t ui32Semaphore)
{
// Check the arguments.
ASSERT((ui32Semaphore == AUX_SMPH_0) ||
(ui32Semaphore == AUX_SMPH_1) ||
(ui32Semaphore == AUX_SMPH_2) ||
(ui32Semaphore == AUX_SMPH_3) ||
(ui32Semaphore == AUX_SMPH_4) ||
(ui32Semaphore == AUX_SMPH_5) ||
(ui32Semaphore == AUX_SMPH_6) ||
(ui32Semaphore == AUX_SMPH_7));
// Wait for semaphore to be released such that it can be claimed
// Semaphore register reads 1 when lock was acquired otherwise 0
// (i.e. AUX_SMPH_CLAIMED).
while(HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore) ==
AUX_SMPH_CLAIMED)
{
}
}
//*****************************************************************************
//
//! \brief Try to acquire an AUX semaphore.
//!
//! This function tries to acquire the given AUX semaphore, if the semaphore
//! could not be claimed the function returns false.
//!
//! \note The semaphore can also be acquired by the dedicated Sensor Controller.
//! The System CPU master can thus be competing for the shared resource, i.e.
//! the specified semaphore.
//!
//! \param ui32Semaphore is the semaphore number.
//! - \ref AUX_SMPH_0
//! - \ref AUX_SMPH_1
//! - \ref AUX_SMPH_2
//! - \ref AUX_SMPH_3
//! - \ref AUX_SMPH_4
//! - \ref AUX_SMPH_5
//! - \ref AUX_SMPH_6
//! - \ref AUX_SMPH_7
//!
//! \return Returns true if semaphore was acquired, false otherwise
//!
//! \sa AUXSMPHAcquire(), AUXSMPHRelease()
//
//*****************************************************************************
__STATIC_INLINE bool
AUXSMPHTryAcquire(uint32_t ui32Semaphore)
{
uint32_t ui32SemaReg;
// Check the arguments.
ASSERT((ui32Semaphore == AUX_SMPH_0) ||
(ui32Semaphore == AUX_SMPH_1) ||
(ui32Semaphore == AUX_SMPH_2) ||
(ui32Semaphore == AUX_SMPH_3) ||
(ui32Semaphore == AUX_SMPH_4) ||
(ui32Semaphore == AUX_SMPH_5) ||
(ui32Semaphore == AUX_SMPH_6) ||
(ui32Semaphore == AUX_SMPH_7));
// AUX Semaphore register reads 1 if lock was acquired
// (i.e. SMPH_FREE when read) but subsequent reads will read 0.
ui32SemaReg = HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore);
return (ui32SemaReg == AUX_SMPH_FREE);
}
//*****************************************************************************
//
//! \brief Release an AUX semaphore by System CPU master.
//!
//! This function releases the given AUX semaphore.
//!
//! \note It is up to the application to provide the convention for clearing
//! semaphore.
//!
//! \note The semaphore can also be acquired by the dedicated Sensor Controller.
//! The System CPU master can thus be competing for the shared resource, i.e.
//! the specified semaphore.
//!
//! \param ui32Semaphore is the semaphore number.
//! - \ref AUX_SMPH_0
//! - \ref AUX_SMPH_1
//! - \ref AUX_SMPH_2
//! - \ref AUX_SMPH_3
//! - \ref AUX_SMPH_4
//! - \ref AUX_SMPH_5
//! - \ref AUX_SMPH_6
//! - \ref AUX_SMPH_7
//!
//! \return None
//!
//! \sa AUXSMPHAcquire(), AUXSMPHTryAcquire()
//
//*****************************************************************************
__STATIC_INLINE void
AUXSMPHRelease(uint32_t ui32Semaphore)
{
// Check the arguments.
ASSERT((ui32Semaphore == AUX_SMPH_0) ||
(ui32Semaphore == AUX_SMPH_1) ||
(ui32Semaphore == AUX_SMPH_2) ||
(ui32Semaphore == AUX_SMPH_3) ||
(ui32Semaphore == AUX_SMPH_4) ||
(ui32Semaphore == AUX_SMPH_5) ||
(ui32Semaphore == AUX_SMPH_6) ||
(ui32Semaphore == AUX_SMPH_7));
// No check before release. It is up to the application to provide the
// conventions for who and when a semaphore can be released.
HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore) =
AUX_SMPH_FREE;
}
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __AUX_SMPH_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

96
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@ -1,96 +0,0 @@
/******************************************************************************
* Filename: aux_sysif.c
* Revised: 2018-04-17 14:54:06 +0200 (Tue, 17 Apr 2018)
* Revision: 51890
*
* Description: Driver for the AUX System Interface
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "aux_sysif.h"
//*****************************************************************************
//
// Handle support for DriverLib in ROM:
// This section will undo prototype renaming made in the header file
//
//*****************************************************************************
#if !defined(DOXYGEN)
#undef AUXSYSIFOpModeChange
#define AUXSYSIFOpModeChange NOROM_AUXSYSIFOpModeChange
#endif
//*****************************************************************************
//
// Used in AUXSYSIFOpModeChange() to control the change of the operational mode.
//
//*****************************************************************************
static const uint8_t g_OpMode_to_order[4] = {1,2,0,3};
static const uint8_t g_Order_to_OpMode[4] = {2,0,1,3};
//*****************************************************************************
//
// Controls AUX operational mode change
//
//*****************************************************************************
void
AUXSYSIFOpModeChange(uint32_t targetOpMode)
{
uint32_t currentOpMode;
uint32_t currentOrder;
uint32_t nextMode;
// Check the argument
ASSERT((targetOpMode == AUX_SYSIF_OPMODEREQ_REQ_PDLP)||
(targetOpMode == AUX_SYSIF_OPMODEREQ_REQ_PDA) ||
(targetOpMode == AUX_SYSIF_OPMODEREQ_REQ_LP) ||
(targetOpMode == AUX_SYSIF_OPMODEREQ_REQ_A));
do {
currentOpMode = HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_OPMODEREQ);
while ( currentOpMode != HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_OPMODEACK));
if (currentOpMode != targetOpMode)
{
currentOrder = g_OpMode_to_order[currentOpMode];
if ( currentOrder < g_OpMode_to_order[targetOpMode])
{
nextMode = g_Order_to_OpMode[currentOrder + 1];
}
else
{
nextMode = g_Order_to_OpMode[currentOrder - 1];
}
HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_OPMODEREQ) = nextMode;
}
} while ( currentOpMode != targetOpMode );
}

154
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@ -1,154 +0,0 @@
/******************************************************************************
* Filename: aux_sysif.h
* Revised: 2017-06-27 08:41:49 +0200 (Tue, 27 Jun 2017)
* Revision: 49245
*
* Description: Defines and prototypes for the AUX System Interface
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup aux_group
//! @{
//! \addtogroup auxsysif_api
//! @{
//
//*****************************************************************************
#ifndef __AUX_SYSIF_H__
#define __AUX_SYSIF_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdbool.h>
#include <stdint.h>
#include "../inc/hw_types.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_aux_sysif.h"
#include "debug.h"
//*****************************************************************************
//
// Support for DriverLib in ROM:
// This section renames all functions that are not "static inline", so that
// calling these functions will default to implementation in flash. At the end
// of this file a second renaming will change the defaults to implementation in
// ROM for available functions.
//
// To force use of the implementation in flash, e.g. for debugging:
// - Globally: Define DRIVERLIB_NOROM at project level
// - Per function: Use prefix "NOROM_" when calling the function
//
//*****************************************************************************
#if !defined(DOXYGEN)
#define AUXSYSIFOpModeChange NOROM_AUXSYSIFOpModeChange
#endif
//*****************************************************************************
//
// API Functions and prototypes
//
//*****************************************************************************
//*****************************************************************************
//
// Defines for AUX operational modes.
//
//*****************************************************************************
#define AUX_SYSIF_OPMODE_TARGET_PDLP (AUX_SYSIF_OPMODEREQ_REQ_PDLP)
#define AUX_SYSIF_OPMODE_TARGET_PDA (AUX_SYSIF_OPMODEREQ_REQ_PDA)
#define AUX_SYSIF_OPMODE_TARGET_LP (AUX_SYSIF_OPMODEREQ_REQ_LP)
#define AUX_SYSIF_OPMODE_TARGET_A (AUX_SYSIF_OPMODEREQ_REQ_A)
//*****************************************************************************
//
//! \brief Changes the AUX operational mode to the requested target mode.
//!
//! This function controls the change of the AUX operational mode.
//! The function controls the change of the current operational mode to the
//! operational mode target by adhering to rules specified by HW.
//!
//! \param targetOpMode
//! AUX operational mode:
//! - \ref AUX_SYSIF_OPMODE_TARGET_PDLP (Powerdown operational mode with wakeup to lowpower mode)
//! - \ref AUX_SYSIF_OPMODE_TARGET_PDA (Powerdown operational mode with wakeup to active mode)
//! - \ref AUX_SYSIF_OPMODE_TARGET_LP (Lowpower operational mode)
//! - \ref AUX_SYSIF_OPMODE_TARGET_A (Active operational mode)
//!
//! \return None
//
//*****************************************************************************
extern void AUXSYSIFOpModeChange(uint32_t targetOpMode);
//*****************************************************************************
//
// Support for DriverLib in ROM:
// Redirect to implementation in ROM when available.
//
//*****************************************************************************
#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
#include "../driverlib/rom.h"
#ifdef ROM_AUXSYSIFOpModeChange
#undef AUXSYSIFOpModeChange
#define AUXSYSIFOpModeChange ROM_AUXSYSIFOpModeChange
#endif
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __AUX_SYSIF_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

111
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@ -1,111 +0,0 @@
/******************************************************************************
* Filename: aux_tdc.c
* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017)
* Revision: 48852
*
* Description: Driver for the AUX Time to Digital Converter interface.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "aux_tdc.h"
//*****************************************************************************
//
// Handle support for DriverLib in ROM:
// This section will undo prototype renaming made in the header file
//
//*****************************************************************************
#if !defined(DOXYGEN)
#undef AUXTDCConfigSet
#define AUXTDCConfigSet NOROM_AUXTDCConfigSet
#undef AUXTDCMeasurementDone
#define AUXTDCMeasurementDone NOROM_AUXTDCMeasurementDone
#endif
//*****************************************************************************
//
// Configure the operation of the AUX TDC
//
//*****************************************************************************
void
AUXTDCConfigSet(uint32_t ui32Base, uint32_t ui32StartCondition,
uint32_t ui32StopCondition)
{
// Check the arguments.
ASSERT(AUXTDCBaseValid(ui32Base));
// Make sure the AUX TDC is in the idle state before changing the
// configuration.
while(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) ==
AUX_TDC_STAT_STATE_IDLE))
{
}
// Clear previous results.
HWREG(ui32Base + AUX_TDC_O_CTL) = 0x0;
// Change the configuration.
HWREG(ui32Base + AUX_TDC_O_TRIGSRC) = ui32StartCondition | ui32StopCondition;
}
//*****************************************************************************
//
// Check if the AUX TDC is done measuring
//
//*****************************************************************************
uint32_t
AUXTDCMeasurementDone(uint32_t ui32Base)
{
uint32_t ui32Reg;
uint32_t ui32Status;
// Check the arguments.
ASSERT(AUXTDCBaseValid(ui32Base));
// Check if the AUX TDC is done measuring.
ui32Reg = HWREG(ui32Base + AUX_TDC_O_STAT);
if(ui32Reg & AUX_TDC_STAT_DONE)
{
ui32Status = AUX_TDC_DONE;
}
else if(ui32Reg & AUX_TDC_STAT_SAT)
{
ui32Status = AUX_TDC_TIMEOUT;
}
else
{
ui32Status = AUX_TDC_BUSY;
}
// Return the status.
return (ui32Status);
}

904
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_tdc.h
View file

@ -1,904 +0,0 @@
/******************************************************************************
* Filename: aux_tdc.h
* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017)
* Revision: 49096
*
* Description: Defines and prototypes for the AUX Time-to-Digital Converter
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup aux_group
//! @{
//! \addtogroup auxtdc_api
//! @{
//
//*****************************************************************************
#ifndef __AUX_TDC_H__
#define __AUX_TDC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdbool.h>
#include <stdint.h>
#include "../inc/hw_types.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_ints.h"
#include "../inc/hw_aux_tdc.h"
#include "debug.h"
//*****************************************************************************
//
// Support for DriverLib in ROM:
// This section renames all functions that are not "static inline", so that
// calling these functions will default to implementation in flash. At the end
// of this file a second renaming will change the defaults to implementation in
// ROM for available functions.
//
// To force use of the implementation in flash, e.g. for debugging:
// - Globally: Define DRIVERLIB_NOROM at project level
// - Per function: Use prefix "NOROM_" when calling the function
//
//*****************************************************************************
#if !defined(DOXYGEN)
#define AUXTDCConfigSet NOROM_AUXTDCConfigSet
#define AUXTDCMeasurementDone NOROM_AUXTDCMeasurementDone
#endif
//*****************************************************************************
//
// Defines for the status of a AUX TDC measurement.
//
//*****************************************************************************
#define AUX_TDC_BUSY 0x00000001
#define AUX_TDC_TIMEOUT 0x00000002
#define AUX_TDC_DONE 0x00000004
//*****************************************************************************
//
// Defines for the control of a AUX TDC.
//
//*****************************************************************************
#define AUX_TDC_RUNSYNC 0x00000001
#define AUX_TDC_RUN 0x00000002
#define AUX_TDC_ABORT 0x00000003
//*****************************************************************************
//
// Defines for possible states of the TDC internal state machine.
//
//*****************************************************************************
#define AUXTDC_WAIT_START (AUX_TDC_STAT_STATE_WAIT_START)
#define AUXTDC_WAIT_START_CNTEN (AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN)
#define AUXTDC_IDLE (AUX_TDC_STAT_STATE_IDLE)
#define AUXTDC_CLRCNT (AUX_TDC_STAT_STATE_CLR_CNT)
#define AUXTDC_WAIT_STOP (AUX_TDC_STAT_STATE_WAIT_STOP)
#define AUXTDC_WAIT_STOP_CNTDOWN (AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN)
#define AUXTDC_GETRESULTS (AUX_TDC_STAT_STATE_GET_RESULT)
#define AUXTDC_POR (AUX_TDC_STAT_STATE_POR)
#define AUXTDC_WAIT_CLRCNT_DONE (AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE)
#define AUXTDC_START_FALL (AUX_TDC_STAT_STATE_START_FALL)
#define AUXTDC_FORCE_STOP (AUX_TDC_STAT_STATE_FORCE_STOP)
//*****************************************************************************
//
// Defines for controlling the AUX TDC. Values can be passed to AUXTDCConfigSet().
//
//*****************************************************************************
#define AUXTDC_STOPPOL_RIS (AUX_TDC_TRIGSRC_STOP_POL_HIGH) // Rising edge polarity for stop event
#define AUXTDC_STOPPOL_FALL (AUX_TDC_TRIGSRC_STOP_POL_LOW) // Falling edge polarity for stop event
#define AUXTDC_STOP_AUXIO0 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0)
#define AUXTDC_STOP_AUXIO1 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1)
#define AUXTDC_STOP_AUXIO2 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2)
#define AUXTDC_STOP_AUXIO3 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3)
#define AUXTDC_STOP_AUXIO4 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4)
#define AUXTDC_STOP_AUXIO5 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5)
#define AUXTDC_STOP_AUXIO6 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6)
#define AUXTDC_STOP_AUXIO7 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7)
#define AUXTDC_STOP_AUXIO8 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8)
#define AUXTDC_STOP_AUXIO9 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9)
#define AUXTDC_STOP_AUXIO10 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10)
#define AUXTDC_STOP_AUXIO11 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11)
#define AUXTDC_STOP_AUXIO12 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12)
#define AUXTDC_STOP_AUXIO13 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13)
#define AUXTDC_STOP_AUXIO14 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14)
#define AUXTDC_STOP_AUXIO15 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15)
#define AUXTDC_STOP_AUXIO16 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO16)
#define AUXTDC_STOP_AUXIO17 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO17)
#define AUXTDC_STOP_AUXIO18 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO18)
#define AUXTDC_STOP_AUXIO19 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO19)
#define AUXTDC_STOP_AUXIO20 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO20)
#define AUXTDC_STOP_AUXIO21 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO21)
#define AUXTDC_STOP_AUXIO22 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO22)
#define AUXTDC_STOP_AUXIO23 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO23)
#define AUXTDC_STOP_AUXIO24 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO24)
#define AUXTDC_STOP_AUXIO25 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO25)
#define AUXTDC_STOP_AUXIO26 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO26)
#define AUXTDC_STOP_AUXIO27 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO27)
#define AUXTDC_STOP_AUXIO28 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO28)
#define AUXTDC_STOP_AUXIO29 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO29)
#define AUXTDC_STOP_AUXIO30 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO30)
#define AUXTDC_STOP_AUXIO31 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO31)
#define AUXTDC_STOP_MANUAL_EV (AUX_TDC_TRIGSRC_STOP_SRC_MANUAL_EV)
#define AUXTDC_STOP_AON_RTC_CH2_DLY (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2_DLY)
#define AUXTDC_STOP_AON_RTC_4KHZ (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_4KHZ)
#define AUXTDC_STOP_AON_BATMON_BAT_UPD (AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_BAT_UPD)
#define AUXTDC_STOP_AON_BATMON_TEMP_UPD (AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_TEMP_UPD)
#define AUXTDC_STOP_SCLK_LF (AUX_TDC_TRIGSRC_STOP_SRC_SCLK_LF)
#define AUXTDC_STOP_PWR_DWN (AUX_TDC_TRIGSRC_STOP_SRC_PWR_DWN)
#define AUXTDC_STOP_MCU_ACTIVE (AUX_TDC_TRIGSRC_STOP_SRC_MCU_ACTIVE)
#define AUXTDC_STOP_VDDR_RECHARGE (AUX_TDC_TRIGSRC_STOP_SRC_VDDR_RECHARGE)
#define AUXTDC_STOP_TIMER2_EV0 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV0)
#define AUXTDC_STOP_TIMER2_EV1 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV1)
#define AUXTDC_STOP_TIMER2_EV2 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV2)
#define AUXTDC_STOP_TIMER2_EV3 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV3)
#define AUXTDC_STOP_TIMER2_PULSE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_PULSE)
#define AUXTDC_STOP_TDC_DONE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_DONE)
#define AUXTDC_STOP_ADC_IRQ (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_IRQ)
#define AUXTDC_STOP_ADC_FIFO_NOT_EMPTY (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_NOT_EMPTY)
#define AUXTDC_STOP_NO_EVENT (AUX_TDC_TRIGSRC_STOP_SRC_NO_EVENT)
#define AUXTDC_STOP_ADC_DONE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_DONE)
#define AUXTDC_STOP_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_ALMOST_FULL)
#define AUXTDC_STOP_ISRC_RESET (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ISRC_RESET_N)
#define AUXTDC_STOP_OBSMUX0 (AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX0)
#define AUXTDC_STOP_OBSMUX1 (AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX1)
#define AUXTDC_STOP_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_SMPH_AUTOTAKE_DONE)
#define AUXTDC_STOP_TDC_PRE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_PRE)
#define AUXTDC_STOP_TIMER0_EV (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER0_EV)
#define AUXTDC_STOP_TIMER1_EV (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER1_EV)
#define AUXTDC_STOP_AON_RTC_CH2 (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2)
#define AUXTDC_STOP_AUX_COMPA (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA)
#define AUXTDC_STOP_AUX_COMPB (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB)
#define AUXTDC_STOP_ACLK_REF (AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF)
#define AUXTDC_STOP_MCU_EV (AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV)
#define AUXTDC_STARTPOL_RIS (AUX_TDC_TRIGSRC_START_POL_HIGH) // Rising edge polarity for start event
#define AUXTDC_STARTPOL_FALL (AUX_TDC_TRIGSRC_START_POL_LOW) // Falling edge polarity for start event
#define AUXTDC_START_AUXIO0 (AUX_TDC_TRIGSRC_START_SRC_AUXIO0)
#define AUXTDC_START_AUXIO1 (AUX_TDC_TRIGSRC_START_SRC_AUXIO1)
#define AUXTDC_START_AUXIO2 (AUX_TDC_TRIGSRC_START_SRC_AUXIO2)
#define AUXTDC_START_AUXIO3 (AUX_TDC_TRIGSRC_START_SRC_AUXIO3)
#define AUXTDC_START_AUXIO4 (AUX_TDC_TRIGSRC_START_SRC_AUXIO4)
#define AUXTDC_START_AUXIO5 (AUX_TDC_TRIGSRC_START_SRC_AUXIO5)
#define AUXTDC_START_AUXIO6 (AUX_TDC_TRIGSRC_START_SRC_AUXIO6)
#define AUXTDC_START_AUXIO7 (AUX_TDC_TRIGSRC_START_SRC_AUXIO7)
#define AUXTDC_START_AUXIO8 (AUX_TDC_TRIGSRC_START_SRC_AUXIO8)
#define AUXTDC_START_AUXIO9 (AUX_TDC_TRIGSRC_START_SRC_AUXIO9)
#define AUXTDC_START_AUXIO10 (AUX_TDC_TRIGSRC_START_SRC_AUXIO10)
#define AUXTDC_START_AUXIO11 (AUX_TDC_TRIGSRC_START_SRC_AUXIO11)
#define AUXTDC_START_AUXIO12 (AUX_TDC_TRIGSRC_START_SRC_AUXIO12)
#define AUXTDC_START_AUXIO13 (AUX_TDC_TRIGSRC_START_SRC_AUXIO13)
#define AUXTDC_START_AUXIO14 (AUX_TDC_TRIGSRC_START_SRC_AUXIO14)
#define AUXTDC_START_AUXIO15 (AUX_TDC_TRIGSRC_START_SRC_AUXIO15)
#define AUXTDC_START_AUXIO16 (AUX_TDC_TRIGSRC_START_SRC_AUXIO16)
#define AUXTDC_START_AUXIO17 (AUX_TDC_TRIGSRC_START_SRC_AUXIO17)
#define AUXTDC_START_AUXIO18 (AUX_TDC_TRIGSRC_START_SRC_AUXIO18)
#define AUXTDC_START_AUXIO19 (AUX_TDC_TRIGSRC_START_SRC_AUXIO19)
#define AUXTDC_START_AUXIO20 (AUX_TDC_TRIGSRC_START_SRC_AUXIO20)
#define AUXTDC_START_AUXIO21 (AUX_TDC_TRIGSRC_START_SRC_AUXIO21)
#define AUXTDC_START_AUXIO22 (AUX_TDC_TRIGSRC_START_SRC_AUXIO22)
#define AUXTDC_START_AUXIO23 (AUX_TDC_TRIGSRC_START_SRC_AUXIO23)
#define AUXTDC_START_AUXIO24 (AUX_TDC_TRIGSRC_START_SRC_AUXIO24)
#define AUXTDC_START_AUXIO25 (AUX_TDC_TRIGSRC_START_SRC_AUXIO25)
#define AUXTDC_START_AUXIO26 (AUX_TDC_TRIGSRC_START_SRC_AUXIO26)
#define AUXTDC_START_AUXIO27 (AUX_TDC_TRIGSRC_START_SRC_AUXIO27)
#define AUXTDC_START_AUXIO28 (AUX_TDC_TRIGSRC_START_SRC_AUXIO28)
#define AUXTDC_START_AUXIO29 (AUX_TDC_TRIGSRC_START_SRC_AUXIO29)
#define AUXTDC_START_AUXIO30 (AUX_TDC_TRIGSRC_START_SRC_AUXIO30)
#define AUXTDC_START_AUXIO31 (AUX_TDC_TRIGSRC_START_SRC_AUXIO31)
#define AUXTDC_START_MANUAL_EV (AUX_TDC_TRIGSRC_START_SRC_MANUAL_EV)
#define AUXTDC_START_AON_RTC_CH2_DLY (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2_DLY)
#define AUXTDC_START_AON_RTC_4KHZ (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_4KHZ)
#define AUXTDC_START_AON_BATMON_BAT_UPD (AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_BAT_UPD)
#define AUXTDC_START_AON_BATMON_TEMP_UPD (AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_TEMP_UPD)
#define AUXTDC_START_SCLK_LF (AUX_TDC_TRIGSRC_START_SRC_SCLK_LF)
#define AUXTDC_START_PWR_DWN (AUX_TDC_TRIGSRC_START_SRC_PWR_DWN)
#define AUXTDC_START_MCU_ACTIVE (AUX_TDC_TRIGSRC_START_SRC_MCU_ACTIVE)
#define AUXTDC_START_VDDR_RECHARGE (AUX_TDC_TRIGSRC_START_SRC_VDDR_RECHARGE)
#define AUXTDC_START_TIMER2_EV0 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV0)
#define AUXTDC_START_TIMER2_EV1 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV1)
#define AUXTDC_START_TIMER2_EV2 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV2)
#define AUXTDC_START_TIMER2_EV3 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV3)
#define AUXTDC_START_TIMER2_PULSE (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_PULSE)
#define AUXTDC_START_TDC_DONE (AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_DONE)
#define AUXTDC_START_ADC_IRQ (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_IRQ)
#define AUXTDC_START_ADC_FIFO_NOT_EMPTY (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_NOT_EMPTY)
#define AUXTDC_START_NO_EVENT (AUX_TDC_TRIGSRC_START_SRC_NO_EVENT)
#define AUXTDC_START_ADC_DONE (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_DONE)
#define AUXTDC_START_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_ALMOST_FULL)
#define AUXTDC_START_ISRC_RESET (AUX_TDC_TRIGSRC_START_SRC_AUX_ISRC_RESET_N)
#define AUXTDC_START_OBSMUX0 (AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX0)
#define AUXTDC_START_OBSMUX1 (AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX1)
#define AUXTDC_START_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_START_SRC_AUX_SMPH_AUTOTAKE_DONE)
#define AUXTDC_START_TDC_PRE (AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_PRE)
#define AUXTDC_START_TIMER0_EV (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER0_EV)
#define AUXTDC_START_TIMER1_EV (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER1_EV)
#define AUXTDC_START_AON_RTC_CH2 (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2)
#define AUXTDC_START_AUX_COMPA (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA)
#define AUXTDC_START_AUX_COMPB (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB)
#define AUXTDC_START_ACLK_REF (AUX_TDC_TRIGSRC_START_SRC_ACLK_REF)
#define AUXTDC_START_MCU_EV (AUX_TDC_TRIGSRC_START_SRC_MCU_EV)
//*****************************************************************************
//
// Defines for the possible saturation values set using AUXTDCLimitSet().
//
//*****************************************************************************
#define AUXTDC_SAT_4096 (AUX_TDC_SATCFG_LIMIT_R12)
#define AUXTDC_SAT_8192 (AUX_TDC_SATCFG_LIMIT_R13)
#define AUXTDC_SAT_16384 (AUX_TDC_SATCFG_LIMIT_R14)
#define AUXTDC_SAT_32768 (AUX_TDC_SATCFG_LIMIT_R15)
#define AUXTDC_SAT_65536 (AUX_TDC_SATCFG_LIMIT_R16)
#define AUXTDC_SAT_131072 (AUX_TDC_SATCFG_LIMIT_R17)
#define AUXTDC_SAT_262144 (AUX_TDC_SATCFG_LIMIT_R18)
#define AUXTDC_SAT_524288 (AUX_TDC_SATCFG_LIMIT_R19)
#define AUXTDC_SAT_1048576 (AUX_TDC_SATCFG_LIMIT_R20)
#define AUXTDC_SAT_2097152 (AUX_TDC_SATCFG_LIMIT_R21)
#define AUXTDC_SAT_4194304 (AUX_TDC_SATCFG_LIMIT_R22)
#define AUXTDC_SAT_8388608 (AUX_TDC_SATCFG_LIMIT_R23)
#define AUXTDC_SAT_16777216 (AUX_TDC_SATCFG_LIMIT_R24)
#define AUXTDC_NUM_SAT_VALS 16
//*****************************************************************************
//
// API Functions and prototypes
//
//*****************************************************************************
#ifdef DRIVERLIB_DEBUG
//*****************************************************************************
//
//! \internal
//! \brief Checks an AUX TDC base address.
//!
//! This function determines if a AUX TDC port base address is valid.
//!
//! \param ui32Base is the base address of the AUX TDC port.
//!
//! \return Returns \c true if the base address is valid and \c false
//! otherwise.
//
//*****************************************************************************
static bool
AUXTDCBaseValid(uint32_t ui32Base)
{
return(ui32Base == AUX_TDC_BASE);
}
#endif
//*****************************************************************************
//
//! \brief Get the status of the AUX TDC internal state machine.
//!
//! This function will return the current state of the AUX TDC internal state
//! machine.
//! \param ui32Base is base address of the AUX TDC
//!
//! \return Returns the current state of the state machine.
//! Possible states for the state machine are:
//! - \ref AUXTDC_WAIT_START
//! - \ref AUXTDC_WAIT_START_CNTEN
//! - \ref AUXTDC_IDLE
//! - \ref AUXTDC_CLRCNT
//! - \ref AUXTDC_WAIT_STOP
//! - \ref AUXTDC_WAIT_STOP_CNTDOWN
//! - \ref AUXTDC_GETRESULTS
//! - \ref AUXTDC_POR
//! - \ref AUXTDC_WAIT_CLRCNT_DONE
//! - \ref AUXTDC_START_FALL
//! - \ref AUXTDC_FORCE_STOP.
//
//*****************************************************************************
__STATIC_INLINE uint32_t
AUXTDCStatusGet(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(AUXTDCBaseValid(ui32Base));
// Return the status value for the correct ADI Slave.
return((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) >>
AUX_TDC_STAT_STATE_S);
}
//*****************************************************************************
//
//! \brief Configure the operation of the AUX TDC.
//!
//! Use this function to configure the start and stop event for the AUX TDC.
//!
//! The \c ui32StartCondition must be a bitwise OR of the start event and the
//! polarity of the start event. The start events are:
//! - \ref AUXTDC_START_AUXIO0
//! - \ref AUXTDC_START_AUXIO1
//! - \ref AUXTDC_START_AUXIO2
//! - \ref AUXTDC_START_AUXIO3
//! - \ref AUXTDC_START_AUXIO4
//! - \ref AUXTDC_START_AUXIO5
//! - \ref AUXTDC_START_AUXIO6
//! - \ref AUXTDC_START_AUXIO7
//! - \ref AUXTDC_START_AUXIO8
//! - \ref AUXTDC_START_AUXIO9
//! - \ref AUXTDC_START_AUXIO10
//! - \ref AUXTDC_START_AUXIO11
//! - \ref AUXTDC_START_AUXIO12
//! - \ref AUXTDC_START_AUXIO13
//! - \ref AUXTDC_START_AUXIO14
//! - \ref AUXTDC_START_AUXIO15
//! - \ref AUXTDC_START_AUXIO16
//! - \ref AUXTDC_START_AUXIO17
//! - \ref AUXTDC_START_AUXIO18
//! - \ref AUXTDC_START_AUXIO19
//! - \ref AUXTDC_START_AUXIO20
//! - \ref AUXTDC_START_AUXIO21
//! - \ref AUXTDC_START_AUXIO22
//! - \ref AUXTDC_START_AUXIO23
//! - \ref AUXTDC_START_AUXIO24
//! - \ref AUXTDC_START_AUXIO25
//! - \ref AUXTDC_START_AUXIO26
//! - \ref AUXTDC_START_AUXIO27
//! - \ref AUXTDC_START_AUXIO28
//! - \ref AUXTDC_START_AUXIO29
//! - \ref AUXTDC_START_AUXIO30
//! - \ref AUXTDC_START_AUXIO31
//! - \ref AUXTDC_START_MANUAL_EV
//! - \ref AUXTDC_START_AON_RTC_CH2_DLY
//! - \ref AUXTDC_START_AON_RTC_4KHZ
//! - \ref AUXTDC_START_AON_BATMON_BAT_UPD
//! - \ref AUXTDC_START_AON_BATMON_TEMP_UPD
//! - \ref AUXTDC_START_SCLK_LF
//! - \ref AUXTDC_START_PWR_DWN
//! - \ref AUXTDC_START_MCU_ACTIVE
//! - \ref AUXTDC_START_VDDR_RECHARGE
//! - \ref AUXTDC_START_TIMER2_EV0
//! - \ref AUXTDC_START_TIMER2_EV1
//! - \ref AUXTDC_START_TIMER2_EV2
//! - \ref AUXTDC_START_TIMER2_EV3
//! - \ref AUXTDC_START_TIMER2_PULSE
//! - \ref AUXTDC_START_TDC_DONE
//! - \ref AUXTDC_START_ADC_IRQ
//! - \ref AUXTDC_START_ADC_FIFO_NOT_EMPTY
//! - \ref AUXTDC_START_NO_EVENT
//! - \ref AUXTDC_START_ADC_DONE
//! - \ref AUXTDC_START_ADC_FIFO_ALMOST_FULL
//! - \ref AUXTDC_START_ISRC_RESET
//! - \ref AUXTDC_START_OBSMUX0
//! - \ref AUXTDC_START_OBSMUX1
//! - \ref AUXTDC_START_SMPH_AUTOTAKE_DONE
//! - \ref AUXTDC_START_TDC_PRE
//! - \ref AUXTDC_START_TIMER0_EV
//! - \ref AUXTDC_START_TIMER1_EV
//! - \ref AUXTDC_START_AON_RTC_CH2
//! - \ref AUXTDC_START_AUX_COMPA
//! - \ref AUXTDC_START_AUX_COMPB
//! - \ref AUXTDC_START_ACLK_REF
//! - \ref AUXTDC_START_MCU_EV
//!
//! The polarity of the start event is either rising \ref AUXTDC_STARTPOL_RIS
//! or falling \ref AUXTDC_STARTPOL_FALL.
//!
//! The \c ui32StopCondition must be a bitwise OR of the stop event and the
//! polarity of the stop event. The stop events are:
//! - \ref AUXTDC_STOP_AUXIO0
//! - \ref AUXTDC_STOP_AUXIO1
//! - \ref AUXTDC_STOP_AUXIO2
//! - \ref AUXTDC_STOP_AUXIO3
//! - \ref AUXTDC_STOP_AUXIO4
//! - \ref AUXTDC_STOP_AUXIO5
//! - \ref AUXTDC_STOP_AUXIO6
//! - \ref AUXTDC_STOP_AUXIO7
//! - \ref AUXTDC_STOP_AUXIO8
//! - \ref AUXTDC_STOP_AUXIO9
//! - \ref AUXTDC_STOP_AUXIO10
//! - \ref AUXTDC_STOP_AUXIO11
//! - \ref AUXTDC_STOP_AUXIO12
//! - \ref AUXTDC_STOP_AUXIO13
//! - \ref AUXTDC_STOP_AUXIO14
//! - \ref AUXTDC_STOP_AUXIO15
//! - \ref AUXTDC_STOP_AUXIO16
//! - \ref AUXTDC_STOP_AUXIO17
//! - \ref AUXTDC_STOP_AUXIO18
//! - \ref AUXTDC_STOP_AUXIO19
//! - \ref AUXTDC_STOP_AUXIO20
//! - \ref AUXTDC_STOP_AUXIO21
//! - \ref AUXTDC_STOP_AUXIO22
//! - \ref AUXTDC_STOP_AUXIO23
//! - \ref AUXTDC_STOP_AUXIO24
//! - \ref AUXTDC_STOP_AUXIO25
//! - \ref AUXTDC_STOP_AUXIO26
//! - \ref AUXTDC_STOP_AUXIO27
//! - \ref AUXTDC_STOP_AUXIO28
//! - \ref AUXTDC_STOP_AUXIO29
//! - \ref AUXTDC_STOP_AUXIO30
//! - \ref AUXTDC_STOP_AUXIO31
//! - \ref AUXTDC_STOP_MANUAL_EV
//! - \ref AUXTDC_STOP_AON_RTC_CH2_DLY
//! - \ref AUXTDC_STOP_AON_RTC_4KHZ
//! - \ref AUXTDC_STOP_AON_BATMON_BAT_UPD
//! - \ref AUXTDC_STOP_AON_BATMON_TEMP_UPD
//! - \ref AUXTDC_STOP_SCLK_LF
//! - \ref AUXTDC_STOP_PWR_DWN
//! - \ref AUXTDC_STOP_MCU_ACTIVE
//! - \ref AUXTDC_STOP_VDDR_RECHARGE
//! - \ref AUXTDC_STOP_TIMER2_EV0
//! - \ref AUXTDC_STOP_TIMER2_EV1
//! - \ref AUXTDC_STOP_TIMER2_EV2
//! - \ref AUXTDC_STOP_TIMER2_EV3
//! - \ref AUXTDC_STOP_TIMER2_PULSE
//! - \ref AUXTDC_STOP_TDC_DONE
//! - \ref AUXTDC_STOP_ADC_IRQ
//! - \ref AUXTDC_STOP_ADC_FIFO_NOT_EMPTY
//! - \ref AUXTDC_STOP_NO_EVENT
//! - \ref AUXTDC_STOP_ADC_DONE
//! - \ref AUXTDC_STOP_ADC_FIFO_ALMOST_FULL
//! - \ref AUXTDC_STOP_ISRC_RESET
//! - \ref AUXTDC_STOP_OBSMUX0
//! - \ref AUXTDC_STOP_OBSMUX1
//! - \ref AUXTDC_STOP_SMPH_AUTOTAKE_DONE
//! - \ref AUXTDC_STOP_TDC_PRE
//! - \ref AUXTDC_STOP_TIMER0_EV
//! - \ref AUXTDC_STOP_TIMER1_EV
//! - \ref AUXTDC_STOP_AON_RTC_CH2
//! - \ref AUXTDC_STOP_AUX_COMPA
//! - \ref AUXTDC_STOP_AUX_COMPB
//! - \ref AUXTDC_STOP_ACLK_REF
//! - \ref AUXTDC_STOP_MCU_EV
//!
//! The polarity of the stop event is either rising \ref AUXTDC_STOPPOL_RIS
//! or falling \ref AUXTDC_STOPPOL_FALL.
//!
//! \note The AUX TDC should only be configured when the AUX TDC is in the Idle
//! state. To ensure that software does not lock up, it is recommended to
//! ensure that the AUX TDC is actually in idle when calling \ref AUXTDCConfigSet().
//! This can be tested using \ref AUXTDCIdle().
//!
//! \param ui32Base is base address of the AUX TDC.
//! \param ui32StartCondition is AUX TDC a bitwise OR of a start event and polarity.
//! \param ui32StopCondition is AUX TDC a bitwise OR of a stop event and polarity.
//!
//! \return None
//!
//! \sa \ref AUXTDCConfigSet(), \ref AUXTDCIdle()
//
//*****************************************************************************
extern void AUXTDCConfigSet(uint32_t ui32Base, uint32_t ui32StartCondition,
uint32_t ui32StopCondition);
//*****************************************************************************
//
//! \brief Check if the AUX TDC is in idle mode.
//!
//! This function can be used to check whether the AUX TDC internal state
//! machine is in idle mode. This is required before setting the polarity
//! of the start and stop event.
//!
//! \param ui32Base is the base address of the AUX TDC.
//!
//! \return Returns \c true if state machine is in idle and returns \c false
//! if the state machine is in any other state.
//
//*****************************************************************************
__STATIC_INLINE bool
AUXTDCIdle(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(AUXTDCBaseValid(ui32Base));
// Check if the AUX TDC is in the Idle state.
return (((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) ==
AUX_TDC_STAT_STATE_IDLE) ? true : false);
}
//*****************************************************************************
//
//! \brief Enable the AUX TDC for a measurement.
//!
//! This function is used for arming the AUX TDC to begin a measurement as
//! soon as the start condition is met. There are two run modes:
//! - \ref AUX_TDC_RUNSYNC will wait for a falling event of the start pulse before
//! starting measurement on next rising edge of start. This guarantees an edge
//! triggered start and is recommended for frequency measurements. If the
//! first falling edge is close to the start command it may be missed, but
//! the TDC shall catch later falling edges and in any case guarantee a
//! measurement start synchronous to the rising edge of the start event.
//! - The \ref AUX_TDC_RUN is asynchronous start and asynchronous stop mode. Using
//! this a TDC measurement may start immediately if start is high and hence it
//! may not give precise edge to edge measurements. This mode is only
//! recommended when start pulse is guaranteed to arrive at least 7 clock
//! periods after command.
//!
//! \note The AUX TDC should be configured and in Idle mode before calling this
//! function.
//!
//! \param ui32Base is the base address of the AUX TDC.
//! \param ui32RunMode is the run mode for the AUX TDC.
//! - \ref AUX_TDC_RUNSYNC : Synchronous run mode.
//! - \ref AUX_TDC_RUN : Asynchronous run mode.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
AUXTDCEnable(uint32_t ui32Base, uint32_t ui32RunMode)
{
// Check the arguments.
ASSERT(AUXTDCBaseValid(ui32Base));
ASSERT((ui32RunMode == AUX_TDC_RUN) ||
(ui32RunMode == AUX_TDC_RUNSYNC));
// Enable the AUX TDC.
HWREG(ui32Base + AUX_TDC_O_CTL) = ui32RunMode;
}
//*****************************************************************************
//
//! \brief Force the AUX TDC back to Idle mode.
//!
//! This function will force the AUX TDC in Idle mode. The internal state
//! machine will not go directly to Idle mode, so it is left to the programmer to
//! ensure that the state machine is in Idle mode before doing any new
//! configuration. This can be checked using \ref AUXTDCIdle().
//!
//! \param ui32Base is the base address of the AUX TDC.
//!
//! \return None
//!
//! \sa \ref AUXTDCIdle()
//
//*****************************************************************************
__STATIC_INLINE void
AUXTDCIdleForce(uint32_t ui32Base)
{
// Check the arguments
ASSERT(AUXTDCBaseValid(ui32Base));
// Abort operation of AUX TDC and force into Idle mode.
HWREG(ui32Base + AUX_TDC_O_CTL) = AUX_TDC_CTL_CMD_ABORT;
}
//*****************************************************************************
//
//! \brief Check if the AUX TDC is done measuring.
//!
//! This function can be used to check whether the AUX TDC has finished a
//! measurement. The AUX TDC may have completed a measurement for two reasons.
//! Either it finish successfully \ref AUX_TDC_DONE or it failed due to a timeout
//! \ref AUX_TDC_TIMEOUT. If the AUX TDC is still measuring it this function
//! will return \ref AUX_TDC_BUSY.
//!
//! \param ui32Base is the base address of the AUX TDC.
//!
//! \return Returns the current status of a measurement:
//! - \ref AUX_TDC_DONE : An AUX TDC measurement finished successfully.
//! - \ref AUX_TDC_TIMEOUT : An AUX TDC measurement failed due to timeout.
//! - \ref AUX_TDC_BUSY : An AUX TDC measurement is being performed.
//
//*****************************************************************************
extern uint32_t AUXTDCMeasurementDone(uint32_t ui32Base);
//*****************************************************************************
//
//! \brief Get the value of the latest measurement.
//!
//! This function is used for retrieving the value of the latest measurement
//! performed by the AUX TDC.
//!
//! \param ui32Base is the base address of the AUX TDC.
//!
//! \return Returns the result of the latest measurement.
//
//*****************************************************************************
__STATIC_INLINE uint32_t
AUXTDCMeasurementGet(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(AUXTDCBaseValid(ui32Base));
// Return the measurement.
return (HWREG(ui32Base + AUX_TDC_O_RESULT));
}
//*****************************************************************************
//
//! \brief Set the saturation limit of the measurement.
//!
//! This function is used to set a saturation limit for the event accumulation
//! register. The saturation limit is defined as a bit width of the
//! accumulation register and therefore increases in power of 2.
//!
//! \param ui32Base is base address of the AUX TDC.
//! \param ui32Limit is the saturation limit.
//! - \ref AUXTDC_SAT_4096
//! - \ref AUXTDC_SAT_8192
//! - \ref AUXTDC_SAT_16384
//! - \ref AUXTDC_SAT_32768
//! - \ref AUXTDC_SAT_65536
//! - \ref AUXTDC_SAT_131072
//! - \ref AUXTDC_SAT_262144
//! - \ref AUXTDC_SAT_524288
//! - \ref AUXTDC_SAT_1048576
//! - \ref AUXTDC_SAT_2097152
//! - \ref AUXTDC_SAT_4194304
//! - \ref AUXTDC_SAT_8388608
//! - \ref AUXTDC_SAT_16777216 (default)
//!
//! \return None
//!
//! \note The actual value of the accumulation register might increase slightly beyond
//! the saturation value before the saturation takes effect.
//!
//! \sa \ref AUXTDCLimitGet()
//
//*****************************************************************************
__STATIC_INLINE void
AUXTDCLimitSet(uint32_t ui32Base, uint32_t ui32Limit)
{
// Check the arguments.
ASSERT(AUXTDCBaseValid(ui32Base));
ASSERT(ui32Limit < AUXTDC_NUM_SAT_VALS);
// Set the saturation limit.
HWREG(ui32Base + AUX_TDC_O_SATCFG) = ui32Limit;
}
//*****************************************************************************
//
//! \brief Get the saturation limit of the measurement.
//!
//! This function is used to retrieve the current saturation for the
//! accumulator register.
//!
//! \param ui32Base is base address of the AUX TDC.
//!
//! \return Returns the saturation limit.
//! - \ref AUXTDC_SAT_4096
//! - \ref AUXTDC_SAT_8192
//! - \ref AUXTDC_SAT_16384
//! - \ref AUXTDC_SAT_32768
//! - \ref AUXTDC_SAT_65536
//! - \ref AUXTDC_SAT_131072
//! - \ref AUXTDC_SAT_262144
//! - \ref AUXTDC_SAT_524288
//! - \ref AUXTDC_SAT_1048576
//! - \ref AUXTDC_SAT_2097152
//! - \ref AUXTDC_SAT_4194304
//! - \ref AUXTDC_SAT_8388608
//! - \ref AUXTDC_SAT_16777216
//!
//! \sa \ref AUXTDCLimitSet()
//
//*****************************************************************************
__STATIC_INLINE uint32_t
AUXTDCLimitGet(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(AUXTDCBaseValid(ui32Base));
// Return the saturation limit.
return (HWREG(ui32Base + AUX_TDC_O_SATCFG));
}
//*****************************************************************************
//
//! \brief Enables the counter if possible.
//!
//! This function can be used to enable the AUX TDC stop/compare event counter.
//! The counter can be used to measure multiple periods of a clock signal.
//! For each stop/compare event the counter will be decremented by one and
//! the measurement will continue running until the value of the counter
//! reaches 0. The current value of the counter can be read using
//! \ref AUXTDCCounterGet(). The reset value of the counter can be set using
//! \ref AUXTDCCounterSet().
//!
//! \param ui32Base is base address of the AUX TDC.
//!
//! \return Returns \c true if the counter was successfully enabled. If the
//! AUX TDC is not in Idle mode, the counter can not be enabled, and the
//! return value will be \c false.
//!
//! \sa \ref AUXTDCCounterGet(), \ref AUXTDCCounterSet()
//
//*****************************************************************************
__STATIC_INLINE bool
AUXTDCCounterEnable(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(AUXTDCBaseValid(ui32Base));
// Check if the AUX TDC is in idle mode. If not in Idle mode, the counter
// will not be enabled.
if(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) ==
AUX_TDC_STAT_STATE_IDLE))
{
return false;
}
// Enable the counter.
HWREG(ui32Base + AUX_TDC_O_TRIGCNTCFG) = AUX_TDC_TRIGCNTCFG_EN;
// Counter successfully enabled.
return true;
}
//*****************************************************************************
//
//! \brief Disables the counter if possible.
//!
//! This function can be used to disable the AUX TDC stop/compare event counter.
//!
//! \param ui32Base is base address of the AUX TDC.
//!
//! \return Returns \c true if the counter was successfully disabled. If the
//! AUX TDC is not in Idle mode, the counter can not be disabled, and the
//! return value will be \c false.
//!
//! \sa \ref AUXTDCCounterEnable() for more information on how to use the counter.
//
//*****************************************************************************
__STATIC_INLINE bool
AUXTDCCounterDisable(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(AUXTDCBaseValid(ui32Base));
// Check if the AUX TDC is in Idle mode. If not in Idle mode, the counter
// will not be disabled.
if(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) ==
AUX_TDC_STAT_STATE_IDLE))
{
return false;
}
// Disable the counter.
HWREG(ui32Base + AUX_TDC_O_TRIGCNTCFG) = 0;
// Counter successfully disabled.
return true;
}
//*****************************************************************************
//
//! \brief Set the reset number of counter compare/stop event to ignore before taking
//! a measurement.
//!
//! This function loads the reset value of the counter with the specified
//! number of events to ignore. A reset in this context means the counter
//! has been disabled and then enabled.
//!
//! \param ui32Base is base address of the AUX TDC.
//! \param ui32Events is the number of compare/stop events to load into the
//! counter.
//!
//! \return Returns \c true if the counter was successfully updated. If the
//! AUX TDC is not in Idle mode, the counter can not be updated, and the
//! return value will be \c false.
//!
//! \sa \ref AUXTDCCounterEnable()
//
//*****************************************************************************
__STATIC_INLINE bool
AUXTDCCounterSet(uint32_t ui32Base, uint32_t ui32Events)
{
// Check the arguments.
ASSERT(AUXTDCBaseValid(ui32Base));
// Check if the AUX TDC is in idle mode. If not in idle mode, the counter
// will not be disabled.
if(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) ==
AUX_TDC_STAT_STATE_IDLE))
{
return false;
}
// Update the reset counter value.
HWREG(ui32Base + AUX_TDC_O_TRIGCNTLOAD) = ui32Events;
// Counter successfully updated.
return true;
}
//*****************************************************************************
//
//! \brief Get the current number of counter compare/stop event to ignore before
//! taking a measurement.
//!
//! This function returns the current value of compare/stop events before
//! a measurement is registered. This value is decremented by one for each
//! registered compare/stop event and will always be less than or equal the
//! reset value of the counter set using \ref AUXTDCCounterSet().
//!
//! \param ui32Base is base address of the AUX TDC.
//!
//! \return Returns the current value of compare/stop events ignored before a
//! measurement is performed.
//!
//! \sa \ref AUXTDCCounterEnable().
//
//*****************************************************************************
__STATIC_INLINE uint32_t
AUXTDCCounterGet(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(AUXTDCBaseValid(ui32Base));
// Return the current counter value.
return (HWREG(ui32Base + AUX_TDC_O_TRIGCNT));
}
//*****************************************************************************
//
// Support for DriverLib in ROM:
// Redirect to implementation in ROM when available.
//
//*****************************************************************************
#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
#include "../driverlib/rom.h"
#ifdef ROM_AUXTDCConfigSet
#undef AUXTDCConfigSet
#define AUXTDCConfigSet ROM_AUXTDCConfigSet
#endif
#ifdef ROM_AUXTDCMeasurementDone
#undef AUXTDCMeasurementDone
#define AUXTDCMeasurementDone ROM_AUXTDCMeasurementDone
#endif
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __AUX_TDC_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

41
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@ -1,41 +0,0 @@
/******************************************************************************
* Filename: ccfgread.c
* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016)
* Revision: 47179
*
* Description: API for reading CCFG.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "ccfgread.h"
// See ccfgread.h for implementation

187
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View file

@ -1,187 +0,0 @@
/******************************************************************************
* Filename: ccfgread.h
* Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016)
* Revision: 47152
*
* Description: API for reading CCFG.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup system_control_group
//! @{
//! \addtogroup ccfgread_api
//! @{
//
//*****************************************************************************
#ifndef __CCFGREAD_H__
#define __CCFGREAD_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdbool.h>
#include <stdint.h>
#include "../inc/hw_types.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_ccfg.h"
//*****************************************************************************
//
// General constants and defines
//
//*****************************************************************************
//*****************************************************************************
//
// API Functions and prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Read DIS_GPRAM from CCFG.
//!
//! \return Value of CCFG field CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM
//
//*****************************************************************************
__STATIC_INLINE bool
CCFGRead_DIS_GPRAM( void )
{
return (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) &
CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M ) >>
CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S ) ;
}
//*****************************************************************************
//
//! \brief Read EXT_LF_CLK_DIO from CCFG.
//!
//! \return Value of CCFG field CCFG_EXT_LF_CLK_DIO
//
//*****************************************************************************
__STATIC_INLINE bool
CCFGRead_EXT_LF_CLK_DIO( void )
{
return (( HWREG( CCFG_BASE + CCFG_O_EXT_LF_CLK ) &
CCFG_EXT_LF_CLK_DIO_M ) >>
CCFG_EXT_LF_CLK_DIO_S ) ;
}
//*****************************************************************************
//
// Defines the possible values returned from CCFGRead_SCLK_LF_OPTION()
//
//*****************************************************************************
#define CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF ( CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S )
#define CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S )
#define CCFGREAD_SCLK_LF_OPTION_XOSC_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S )
#define CCFGREAD_SCLK_LF_OPTION_RCOSC_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S )
//*****************************************************************************
//
//! \brief Read SCLK_LF_OPTION from CCFG.
//!
//! \return Returns the value of the CCFG field CCFG_MODE_CONF_SCLK_LF_OPTION field.
//! Returns one of the following:
//! - \ref CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF
//! - \ref CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF
//! - \ref CCFGREAD_SCLK_LF_OPTION_XOSC_LF
//! - \ref CCFGREAD_SCLK_LF_OPTION_RCOSC_LF
//
//*****************************************************************************
__STATIC_INLINE uint32_t
CCFGRead_SCLK_LF_OPTION( void )
{
return (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF ) &
CCFG_MODE_CONF_SCLK_LF_OPTION_M ) >>
CCFG_MODE_CONF_SCLK_LF_OPTION_S ) ;
}
//*****************************************************************************
//
// Defines the possible values returned from CCFGRead_XOSC_FREQ()
//
//*****************************************************************************
#define CCFGREAD_XOSC_FREQ_24M ( CCFG_MODE_CONF_XOSC_FREQ_24M >> CCFG_MODE_CONF_XOSC_FREQ_S )
#define CCFGREAD_XOSC_FREQ_48M ( CCFG_MODE_CONF_XOSC_FREQ_48M >> CCFG_MODE_CONF_XOSC_FREQ_S )
#define CCFGREAD_XOSC_FREQ_HPOSC ( CCFG_MODE_CONF_XOSC_FREQ_HPOSC >> CCFG_MODE_CONF_XOSC_FREQ_S )
//*****************************************************************************
//
//! \brief Read XOSC_FREQ setting CCFG.
//!
//! \return Returns the value of the CCFG_MODE_CONF_XOSC_FREQ field.
//! Returns one of the following:
//! - \ref CCFGREAD_XOSC_FREQ_24M
//! - \ref CCFGREAD_XOSC_FREQ_48M
//! - \ref CCFGREAD_XOSC_FREQ_HPOSC
//!
//
//*****************************************************************************
__STATIC_INLINE uint32_t
CCFGRead_XOSC_FREQ( void )
{
return (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF ) &
CCFG_MODE_CONF_XOSC_FREQ_M ) >>
CCFG_MODE_CONF_XOSC_FREQ_S ) ;
}
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __AUX_SMPH_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

51
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread_doc.h
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@ -1,51 +0,0 @@
/******************************************************************************
* Filename: ccfgread_doc.h
* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016)
* Revision: 45971
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//! \addtogroup ccfgread_api
//! @{
//! \section sec_ccfgread Introduction
//!
//! The values of customer configuration (CCFG) settings in flash are determined by ccfg.c and typically
//! a user application does not need to read these CCFG values as they are used mainly during ROM boot
//! and device trimming. However, a subset of the CCFG settings need to be read by application
//! code thus DriverLib provides this API to allow easy read access to these specific settings.
//!
//! The remaining settings not accessible through this API can of course be read directly at the CCFG
//! addresses in the flash (starting at CCFG_BASE) using the HWREG macro and the provided defines.
//! CCFG settings are documented as part of the register descriptions in the CPU memory map.
//!
//! \note CCFG settings are located in flash and should be considered read-only from an application
//! point-of-view.
//! @}

210
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.c
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@ -1,210 +0,0 @@
/******************************************************************************
* Filename: chipinfo.c
* Revised: 2018-08-17 09:28:06 +0200 (Fri, 17 Aug 2018)
* Revision: 52354
*
* Description: Collection of functions returning chip information.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "chipinfo.h"
//*****************************************************************************
//
// Handle support for DriverLib in ROM:
// This section will undo prototype renaming made in the header file
//
//*****************************************************************************
#if !defined(DOXYGEN)
#undef ChipInfo_GetSupportedProtocol_BV
#define ChipInfo_GetSupportedProtocol_BV NOROM_ChipInfo_GetSupportedProtocol_BV
#undef ChipInfo_GetPackageType
#define ChipInfo_GetPackageType NOROM_ChipInfo_GetPackageType
#undef ChipInfo_GetChipType
#define ChipInfo_GetChipType NOROM_ChipInfo_GetChipType
#undef ChipInfo_GetChipFamily
#define ChipInfo_GetChipFamily NOROM_ChipInfo_GetChipFamily
#undef ChipInfo_GetHwRevision
#define ChipInfo_GetHwRevision NOROM_ChipInfo_GetHwRevision
#undef ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated
#define ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated NOROM_ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated
#endif
//*****************************************************************************
//
// ChipInfo_GetSupportedProtocol_BV()
//
//*****************************************************************************
ProtocolBitVector_t
ChipInfo_GetSupportedProtocol_BV( void )
{
return ((ProtocolBitVector_t)( HWREG( PRCM_BASE + 0x1D4 ) & 0x0E ));
}
//*****************************************************************************
//
// ChipInfo_GetPackageType()
//
//*****************************************************************************
PackageType_t
ChipInfo_GetPackageType( void )
{
PackageType_t packType = (PackageType_t)((
HWREG( FCFG1_BASE + FCFG1_O_USER_ID ) &
FCFG1_USER_ID_PKG_M ) >>
FCFG1_USER_ID_PKG_S ) ;
if (( packType < PACKAGE_4x4 ) ||
( packType > PACKAGE_7x7_Q1 ) )
{
packType = PACKAGE_Unknown;
}
return ( packType );
}
//*****************************************************************************
//
// ChipInfo_GetChipFamily()
//
//*****************************************************************************
ChipFamily_t
ChipInfo_GetChipFamily( void )
{
uint32_t waferId ;
ChipFamily_t chipFam = FAMILY_Unknown ;
waferId = (( HWREG( FCFG1_BASE + FCFG1_O_ICEPICK_DEVICE_ID ) &
FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_M ) >>
FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_S ) ;
if ( waferId == 0xBB41 ) {
chipFam = FAMILY_CC13x2_CC26x2 ;
}
return ( chipFam );
}
//*****************************************************************************
//
// ChipInfo_GetChipType()
//
//*****************************************************************************
ChipType_t
ChipInfo_GetChipType( void )
{
ChipType_t chipType = CHIP_TYPE_Unknown ;
ChipFamily_t chipFam = ChipInfo_GetChipFamily() ;
uint32_t fcfg1UserId = ChipInfo_GetUserId() ;
uint32_t fcfg1Protocol = (( fcfg1UserId & FCFG1_USER_ID_PROTOCOL_M ) >>
FCFG1_USER_ID_PROTOCOL_S ) ;
uint32_t fcfg1Cc13 = (( fcfg1UserId & FCFG1_USER_ID_CC13_M ) >>
FCFG1_USER_ID_CC13_S ) ;
uint32_t fcfg1Pa = (( fcfg1UserId & FCFG1_USER_ID_PA_M ) >>
FCFG1_USER_ID_PA_S ) ;
if ( chipFam == FAMILY_CC13x2_CC26x2 ) {
switch ( fcfg1Protocol ) {
case 0xF :
if( fcfg1Cc13 ) {
if ( fcfg1Pa ) {
chipType = CHIP_TYPE_CC1352P ;
} else {
chipType = CHIP_TYPE_CC1352 ;
}
} else {
chipType = CHIP_TYPE_CC2652 ;
}
break;
case 0x9 :
if( fcfg1Pa ) {
chipType = CHIP_TYPE_unused ;
} else {
chipType = CHIP_TYPE_CC2642 ;
}
break;
case 0x8 :
chipType = CHIP_TYPE_CC1312 ;
break;
}
}
return ( chipType );
}
//*****************************************************************************
//
// ChipInfo_GetHwRevision()
//
//*****************************************************************************
HwRevision_t
ChipInfo_GetHwRevision( void )
{
HwRevision_t hwRev = HWREV_Unknown ;
uint32_t fcfg1Rev = ChipInfo_GetDeviceIdHwRevCode() ;
uint32_t minorHwRev = ChipInfo_GetMinorHwRev() ;
ChipFamily_t chipFam = ChipInfo_GetChipFamily() ;
if ( chipFam == FAMILY_CC13x2_CC26x2 ) {
switch ( fcfg1Rev ) {
case 0 : // CC13x2, CC26x2 - PG1.0
case 1 : // CC13x2, CC26x2 - PG1.01 (will also show up as PG1.0)
hwRev = (HwRevision_t)((uint32_t)HWREV_1_0 );
break;
case 2 : // CC13x2, CC26x2 - PG1.1 (or later)
hwRev = (HwRevision_t)(((uint32_t)HWREV_1_1 ) + minorHwRev );
break;
case 3 : // CC13x2, CC26x2 - PG2.1 (or later)
hwRev = (HwRevision_t)(((uint32_t)HWREV_2_1 ) + minorHwRev );
break;
}
}
return ( hwRev );
}
//*****************************************************************************
// ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated()
//*****************************************************************************
void
ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated( void )
{
if (( ! ChipInfo_ChipFamilyIs_CC13x2_CC26x2() ) ||
( ! ChipInfo_HwRevisionIs_GTEQ_2_0() ) )
{
while(1)
{
// This driverlib version is for the CC13x2/CC26x2 PG2.0 and later chips.
// Do nothing - stay here forever
}
}
}

685
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@ -1,685 +0,0 @@
/******************************************************************************
* Filename: chipinfo.h
* Revised: 2018-06-18 10:26:12 +0200 (Mon, 18 Jun 2018)
* Revision: 52189
*
* Description: Collection of functions returning chip information.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup system_control_group
//! @{
//! \addtogroup ChipInfo
//! @{
//
//*****************************************************************************
#ifndef __CHIP_INFO_H__
#define __CHIP_INFO_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
#include <stdbool.h>
#include "../inc/hw_types.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_fcfg1.h"
//*****************************************************************************
//
// Support for DriverLib in ROM:
// This section renames all functions that are not "static inline", so that
// calling these functions will default to implementation in flash. At the end
// of this file a second renaming will change the defaults to implementation in
// ROM for available functions.
//
// To force use of the implementation in flash, e.g. for debugging:
// - Globally: Define DRIVERLIB_NOROM at project level
// - Per function: Use prefix "NOROM_" when calling the function
//
//*****************************************************************************
#if !defined(DOXYGEN)
#define ChipInfo_GetSupportedProtocol_BV NOROM_ChipInfo_GetSupportedProtocol_BV
#define ChipInfo_GetPackageType NOROM_ChipInfo_GetPackageType
#define ChipInfo_GetChipType NOROM_ChipInfo_GetChipType
#define ChipInfo_GetChipFamily NOROM_ChipInfo_GetChipFamily
#define ChipInfo_GetHwRevision NOROM_ChipInfo_GetHwRevision
#define ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated NOROM_ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated
#endif
//*****************************************************************************
//
//! \brief Enumeration identifying the protocols supported.
//!
//! \note
//! This is a bit vector enumeration that indicates supported protocols.
//! E.g: 0x06 means that the chip supports both BLE and IEEE 802.15.4
//
//*****************************************************************************
typedef enum {
PROTOCOL_Unknown = 0 , //!< None of the known protocols are supported.
PROTOCOLBIT_BLE = 0x02, //!< Bit[1] set, indicates that Bluetooth Low Energy is supported.
PROTOCOLBIT_IEEE_802_15_4 = 0x04, //!< Bit[2] set, indicates that IEEE 802.15.4 is supported.
PROTOCOLBIT_Proprietary = 0x08 //!< Bit[3] set, indicates that proprietary protocols are supported.
} ProtocolBitVector_t;
//*****************************************************************************
//
//! \brief Returns bit vector showing supported protocols.
//!
//! \return
//! Returns \ref ProtocolBitVector_t which is a bit vector indicating supported protocols.
//
//*****************************************************************************
extern ProtocolBitVector_t ChipInfo_GetSupportedProtocol_BV( void );
//*****************************************************************************
//
//! \brief Returns true if the chip supports the BLE protocol.
//!
//! \return
//! Returns \c true if supporting the BLE protocol, \c false otherwise.
//
//*****************************************************************************
__STATIC_INLINE bool
ChipInfo_SupportsBLE( void )
{
return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_BLE ) != 0 );
}
//*****************************************************************************
//
//! \brief Returns true if the chip supports the IEEE 802.15.4 protocol.
//!
//! \return
//! Returns \c true if supporting the IEEE 802.15.4 protocol, \c false otherwise.
//
//*****************************************************************************
__STATIC_INLINE bool
ChipInfo_SupportsIEEE_802_15_4( void )
{
return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_IEEE_802_15_4 ) != 0 );
}
//*****************************************************************************
//
//! \brief Returns true if the chip supports proprietary protocols.
//!
//! \return
//! Returns \c true if supporting proprietary protocols, \c false otherwise.
//
//*****************************************************************************
__STATIC_INLINE bool
ChipInfo_SupportsPROPRIETARY( void )
{
return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_Proprietary ) != 0 );
}
//*****************************************************************************
//
//! \brief Package type enumeration
//!
//! \note
//! Packages available for a specific device are shown in the device datasheet.
//
//*****************************************************************************
typedef enum {
PACKAGE_Unknown = -1, //!< -1 means that current package type is unknown.
PACKAGE_4x4 = 0, //!< 0 means that this is a 4x4 mm QFN (RHB) package.
PACKAGE_5x5 = 1, //!< 1 means that this is a 5x5 mm QFN (RSM) package.
PACKAGE_7x7 = 2, //!< 2 means that this is a 7x7 mm QFN (RGZ) package.
PACKAGE_WAFER = 3, //!< 3 means that this is a wafer sale package (naked die).
PACKAGE_WCSP = 4, //!< 4 means that this is a 2.7x2.7 mm WCSP (YFV).
PACKAGE_7x7_Q1 = 5 //!< 5 means that this is a 7x7 mm QFN package with Wettable Flanks.
} PackageType_t;
//*****************************************************************************
//
//! \brief Returns package type.
//!
//! \return
//! Returns \ref PackageType_t
//
//*****************************************************************************
extern PackageType_t ChipInfo_GetPackageType( void );
//*****************************************************************************
//
//! \brief Returns true if this is a 4x4mm chip.
//!
//! \return
//! Returns \c true if this is a 4x4mm chip, \c false otherwise.
//
//*****************************************************************************
__STATIC_INLINE bool
ChipInfo_PackageTypeIs4x4( void )
{
return ( ChipInfo_GetPackageType() == PACKAGE_4x4 );
}
//*****************************************************************************
//
//! \brief Returns true if this is a 5x5mm chip.
//!
//! \return
//! Returns \c true if this is a 5x5mm chip, \c false otherwise.
//
//*****************************************************************************
__STATIC_INLINE bool
ChipInfo_PackageTypeIs5x5( void )
{
return ( ChipInfo_GetPackageType() == PACKAGE_5x5 );
}
//*****************************************************************************
//
//! \brief Returns true if this is a 7x7mm chip.
//!
//! \return
//! Returns \c true if this is a 7x7mm chip, \c false otherwise.
//
//*****************************************************************************
__STATIC_INLINE bool
ChipInfo_PackageTypeIs7x7( void )
{
return ( ChipInfo_GetPackageType() == PACKAGE_7x7 );
}
//*****************************************************************************
//
//! \brief Returns true if this is a wafer sale chip (naked die).
//!
//! \return
//! Returns \c true if this is a wafer sale chip, \c false otherwise.
//
//*****************************************************************************
__STATIC_INLINE bool
ChipInfo_PackageTypeIsWAFER( void )
{
return ( ChipInfo_GetPackageType() == PACKAGE_WAFER );
}
//*****************************************************************************
//
//! \brief Returns true if this is a WCSP chip (flip chip).
//!
//! \return
//! Returns \c true if this is a WCSP chip, \c false otherwise.
//
//*****************************************************************************
__STATIC_INLINE bool
ChipInfo_PackageTypeIsWCSP( void )
{
return ( ChipInfo_GetPackageType() == PACKAGE_WCSP );
}
//*****************************************************************************
//
//! \brief Returns true if this is a 7x7 Q1 chip.
//!
//! \return
//! Returns \c true if this is a 7x7 Q1 chip, \c false otherwise.
//
//*****************************************************************************
__STATIC_INLINE bool
ChipInfo_PackageTypeIs7x7Q1( void )
{
return ( ChipInfo_GetPackageType() == PACKAGE_7x7_Q1 );
}
//*****************************************************************************
//
//! \brief Returns the internal chip HW revision code.
//!
//! \return
//! Returns the internal chip HW revision code (in range 0-15)
//*****************************************************************************
__STATIC_INLINE uint32_t
ChipInfo_GetDeviceIdHwRevCode( void )
{
// Returns HwRevCode = FCFG1_O_ICEPICK_DEVICE_ID[31:28]
return ( HWREG( FCFG1_BASE + FCFG1_O_ICEPICK_DEVICE_ID ) >> 28 );
}
//*****************************************************************************
//
//! \brief Returns minor hardware revision number
//!
//! The minor revision number is set to 0 for the first market released chip
//! and thereafter incremented by 1 for each minor hardware change.
//!
//! \return
//! Returns the minor hardware revision number (in range 0-127)
//
//*****************************************************************************
__STATIC_INLINE uint32_t
ChipInfo_GetMinorHwRev( void )
{
uint32_t minorRev = (( HWREG( FCFG1_BASE + FCFG1_O_MISC_CONF_1 ) &
FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M ) >>
FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S ) ;
if ( minorRev >= 0x80 ) {
minorRev = 0;
}
return( minorRev );
}
//*****************************************************************************
//
//! \brief Returns the 32 bits USER_ID field
//!
//! How to decode the USER_ID filed is described in the Technical Reference Manual (TRM)
//!
//! \return
//! Returns the 32 bits USER_ID field
//
//*****************************************************************************
__STATIC_INLINE uint32_t
ChipInfo_GetUserId( void )
{
return ( HWREG( FCFG1_BASE + FCFG1_O_USER_ID ));
}
//*****************************************************************************
//
//! \brief Chip type enumeration
//
//*****************************************************************************
typedef enum {
CHIP_TYPE_Unknown = -1, //!< -1 means that the chip type is unknown.
CHIP_TYPE_CC1310 = 0, //!< 0 means that this is a CC1310 chip.
CHIP_TYPE_CC1350 = 1, //!< 1 means that this is a CC1350 chip.
CHIP_TYPE_CC2620 = 2, //!< 2 means that this is a CC2620 chip.
CHIP_TYPE_CC2630 = 3, //!< 3 means that this is a CC2630 chip.
CHIP_TYPE_CC2640 = 4, //!< 4 means that this is a CC2640 chip.
CHIP_TYPE_CC2650 = 5, //!< 5 means that this is a CC2650 chip.
CHIP_TYPE_CUSTOM_0 = 6, //!< 6 means that this is a CUSTOM_0 chip.
CHIP_TYPE_CUSTOM_1 = 7, //!< 7 means that this is a CUSTOM_1 chip.
CHIP_TYPE_CC2640R2 = 8, //!< 8 means that this is a CC2640R2 chip.
CHIP_TYPE_CC2642 = 9, //!< 9 means that this is a CC2642 chip.
CHIP_TYPE_unused = 10,//!< 10 unused value
CHIP_TYPE_CC2652 = 11,//!< 11 means that this is a CC2652 chip.
CHIP_TYPE_CC1312 = 12,//!< 12 means that this is a CC1312 chip.
CHIP_TYPE_CC1352 = 13,//!< 13 means that this is a CC1352 chip.
CHIP_TYPE_CC1352P = 14 //!< 14 means that this is a CC1352P chip.
} ChipType_t;
//*****************************************************************************
//
//! \brief Returns chip type.
//!
//! \return
//! Returns \ref ChipType_t
//
//*****************************************************************************
extern ChipType_t ChipInfo_GetChipType( void );
//*****************************************************************************
//
//! \brief Chip family enumeration
//
//*****************************************************************************
typedef enum {
FAMILY_Unknown = -1, //!< -1 means that the chip's family member is unknown.
FAMILY_CC26x0 = 0, //!< 0 means that the chip is a CC26x0 family member.
FAMILY_CC13x0 = 1, //!< 1 means that the chip is a CC13x0 family member.
FAMILY_CC26x1 = 2, //!< 2 means that the chip is a CC26x1 family member.
FAMILY_CC26x0R2 = 3, //!< 3 means that the chip is a CC26x0R2 family (new ROM contents).
FAMILY_CC13x2_CC26x2 = 4 //!< 4 means that the chip is a CC13x2, CC26x2 family member.
} ChipFamily_t;
//*****************************************************************************
//
//! \brief Returns chip family member.
//!
//! \return
//! Returns \ref ChipFamily_t
//
//*****************************************************************************
extern ChipFamily_t ChipInfo_GetChipFamily( void );
//*****************************************************************************
//
// Options for the define THIS_DRIVERLIB_BUILD
//
//*****************************************************************************
#define DRIVERLIB_BUILD_CC26X0 0 //!< 0 is the driverlib build ID for the cc26x0 driverlib.
#define DRIVERLIB_BUILD_CC13X0 1 //!< 1 is the driverlib build ID for the cc13x0 driverlib.
#define DRIVERLIB_BUILD_CC26X1 2 //!< 2 is the driverlib build ID for the cc26x1 driverlib.
#define DRIVERLIB_BUILD_CC26X0R2 3 //!< 3 is the driverlib build ID for the cc26x0r2 driverlib.
#define DRIVERLIB_BUILD_CC13X2_CC26X2 4 //!< 4 is the driverlib build ID for the cc13x2_cc26x2 driverlib.
//*****************************************************************************
//
//! \brief Define THIS_DRIVERLIB_BUILD, identifying current driverlib build ID.
//!
//! This driverlib build identifier can be useful for compile time checking/optimization (supporting C preprocessor expressions).
//
//*****************************************************************************
#define THIS_DRIVERLIB_BUILD DRIVERLIB_BUILD_CC13X2_CC26X2
//*****************************************************************************
//
//! \brief Returns true if this chip is member of the CC13x0 family.
//!
//! \return
//! Returns \c true if this chip is member of the CC13x0 family, \c false otherwise.
//
//*****************************************************************************
__STATIC_INLINE bool
ChipInfo_ChipFamilyIs_CC13x0( void )
{
return ( ChipInfo_GetChipFamily() == FAMILY_CC13x0 );
}
//*****************************************************************************
//
//! \brief Returns true if this chip is member of the CC26x0 family.
//!
//! \return
//! Returns \c true if this chip is member of the CC26x0 family, \c false otherwise.
//
//*****************************************************************************
__STATIC_INLINE bool
ChipInfo_ChipFamilyIs_CC26x0( void )
{
return ( ChipInfo_GetChipFamily() == FAMILY_CC26x0 );
}
//*****************************************************************************
//
//! \brief Returns true if this chip is member of the CC26x0R2 family.
//!
//! \return
//! Returns \c true if this chip is member of the CC26x0R2 family, \c false otherwise.
//
//*****************************************************************************
__STATIC_INLINE bool
ChipInfo_ChipFamilyIs_CC26x0R2( void )
{
return ( ChipInfo_GetChipFamily() == FAMILY_CC26x0R2 );
}
//*****************************************************************************
//
//! \brief Returns true if this chip is member of the CC26x1 family.
//!
//! \return
//! Returns \c true if this chip is member of the CC26x1 family, \c false otherwise.
//
//*****************************************************************************
__STATIC_INLINE bool
ChipInfo_ChipFamilyIs_CC26x1( void )
{
return ( ChipInfo_GetChipFamily() == FAMILY_CC26x1 );
}
//*****************************************************************************
//
//! \brief Returns true if this chip is member of the CC13x2, CC26x2 family.
//!
//! \return
//! Returns \c true if this chip is member of the CC13x2, CC26x2 family, \c false otherwise.
//
//*****************************************************************************
__STATIC_INLINE bool
ChipInfo_ChipFamilyIs_CC13x2_CC26x2( void )
{
return ( ChipInfo_GetChipFamily() == FAMILY_CC13x2_CC26x2 );
}
//*****************************************************************************
//
//! \brief HW revision enumeration.
//
//*****************************************************************************
typedef enum {
HWREV_Unknown = -1, //!< -1 means that the chip's HW revision is unknown.
HWREV_1_0 = 10, //!< 10 means that the chip's HW revision is 1.0
HWREV_1_1 = 11, //!< 11 means that the chip's HW revision is 1.1
HWREV_2_0 = 20, //!< 20 means that the chip's HW revision is 2.0
HWREV_2_1 = 21, //!< 21 means that the chip's HW revision is 2.1
HWREV_2_2 = 22, //!< 22 means that the chip's HW revision is 2.2
HWREV_2_3 = 23, //!< 23 means that the chip's HW revision is 2.3
HWREV_2_4 = 24 //!< 24 means that the chip's HW revision is 2.4
} HwRevision_t;
//*****************************************************************************
//
//! \brief Returns chip HW revision.
//!
//! \return
//! Returns \ref HwRevision_t
//
//*****************************************************************************
extern HwRevision_t ChipInfo_GetHwRevision( void );
//*****************************************************************************
//
//! \brief Returns true if HW revision for this chip is 1.0.
//!
//! \return
//! Returns \c true if HW revision for this chip is 1.0, \c false otherwise.
//
//*****************************************************************************
__STATIC_INLINE bool
ChipInfo_HwRevisionIs_1_0( void )
{
return ( ChipInfo_GetHwRevision() == HWREV_1_0 );
}
//*****************************************************************************
//
//! \brief Returns true if HW revision for this chip is 2.0.
//!
//! \return
//! Returns \c true if HW revision for this chip is 2.0, \c false otherwise.
//
//*****************************************************************************
__STATIC_INLINE bool
ChipInfo_HwRevisionIs_2_0( void )
{
return ( ChipInfo_GetHwRevision() == HWREV_2_0 );
}
//*****************************************************************************
//
//! \brief Returns true if HW revision for this chip is 2.0 or greater.
//!
//! \return
//! Returns \c true if HW revision for this chip is 2.0 or greater, \c false otherwise.
//
//*****************************************************************************
__STATIC_INLINE bool
ChipInfo_HwRevisionIs_GTEQ_2_0( void )
{
return ( ChipInfo_GetHwRevision() >= HWREV_2_0 );
}
//*****************************************************************************
//
//! \brief Returns true if HW revision for this chip is 2.1.
//!
//! \return
//! Returns \c true if HW revision for this chip is 2.1, \c false otherwise.
//
//*****************************************************************************
__STATIC_INLINE bool
ChipInfo_HwRevisionIs_2_1( void )
{
return ( ChipInfo_GetHwRevision() == HWREV_2_1 );
}
//*****************************************************************************
//
//! \brief Returns true if HW revision for this chip is 2.1 or greater.
//!
//! \return
//! Returns \c true if HW revision for this chip is 2.1 or greater, \c false otherwise.
//
//*****************************************************************************
__STATIC_INLINE bool
ChipInfo_HwRevisionIs_GTEQ_2_1( void )
{
return ( ChipInfo_GetHwRevision() >= HWREV_2_1 );
}
//*****************************************************************************
//
//! \brief Returns true if HW revision for this chip is 2.2.
//!
//! \return
//! Returns \c true if HW revision for this chip is 2.2, \c false otherwise.
//
//*****************************************************************************
__STATIC_INLINE bool
ChipInfo_HwRevisionIs_2_2( void )
{
return ( ChipInfo_GetHwRevision() == HWREV_2_2 );
}
//*****************************************************************************
//
//! \brief Returns true if HW revision for this chip is 2.2 or greater.
//!
//! \return
//! Returns \c true if HW revision for this chip is 2.2 or greater, \c false otherwise.
//
//*****************************************************************************
__STATIC_INLINE bool
ChipInfo_HwRevisionIs_GTEQ_2_2( void )
{
return ( ChipInfo_GetHwRevision() >= HWREV_2_2 );
}
//*****************************************************************************
//
//! \brief Returns true if HW revision for this chip is 2.3 or greater.
//!
//! \return
//! Returns \c true if HW revision for this chip is 2.3 or greater, \c false otherwise.
//
//*****************************************************************************
__STATIC_INLINE bool
ChipInfo_HwRevisionIs_GTEQ_2_3( void )
{
return ( ChipInfo_GetHwRevision() >= HWREV_2_3 );
}
//*****************************************************************************
//
//! \brief Returns true if HW revision for this chip is 2.4 or greater.
//!
//! \return
//! Returns \c true if HW revision for this chip is 2.4 or greater, \c false otherwise.
//
//*****************************************************************************
__STATIC_INLINE bool
ChipInfo_HwRevisionIs_GTEQ_2_4( void )
{
return ( ChipInfo_GetHwRevision() >= HWREV_2_4 );
}
//*****************************************************************************
//
//! \brief Verifies that current chip is CC13x2 or CC26x2 PG2.0 or later and never returns if violated.
//!
//! \return None
//
//*****************************************************************************
extern void ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated( void );
//*****************************************************************************
//
// Support for DriverLib in ROM:
// Redirect to implementation in ROM when available.
//
//*****************************************************************************
#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
#include "../driverlib/rom.h"
#ifdef ROM_ChipInfo_GetSupportedProtocol_BV
#undef ChipInfo_GetSupportedProtocol_BV
#define ChipInfo_GetSupportedProtocol_BV ROM_ChipInfo_GetSupportedProtocol_BV
#endif
#ifdef ROM_ChipInfo_GetPackageType
#undef ChipInfo_GetPackageType
#define ChipInfo_GetPackageType ROM_ChipInfo_GetPackageType
#endif
#ifdef ROM_ChipInfo_GetChipType
#undef ChipInfo_GetChipType
#define ChipInfo_GetChipType ROM_ChipInfo_GetChipType
#endif
#ifdef ROM_ChipInfo_GetChipFamily
#undef ChipInfo_GetChipFamily
#define ChipInfo_GetChipFamily ROM_ChipInfo_GetChipFamily
#endif
#ifdef ROM_ChipInfo_GetHwRevision
#undef ChipInfo_GetHwRevision
#define ChipInfo_GetHwRevision ROM_ChipInfo_GetHwRevision
#endif
#ifdef ROM_ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated
#undef ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated
#define ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated ROM_ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated
#endif
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __CHIP_INFO_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

396
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/cpu.c
View file

@ -1,396 +0,0 @@
/******************************************************************************
* Filename: cpu.c
* Revised: 2018-05-08 10:04:01 +0200 (Tue, 08 May 2018)
* Revision: 51972
*
* Description: Instruction wrappers for special CPU instructions needed by
* the drivers.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "cpu.h"
//*****************************************************************************
//
// Handle support for DriverLib in ROM:
// This section will undo prototype renaming made in the header file
//
//*****************************************************************************
#if !defined(DOXYGEN)
#undef CPUcpsid
#define CPUcpsid NOROM_CPUcpsid
#undef CPUprimask
#define CPUprimask NOROM_CPUprimask
#undef CPUcpsie
#define CPUcpsie NOROM_CPUcpsie
#undef CPUbasepriGet
#define CPUbasepriGet NOROM_CPUbasepriGet
#undef CPUdelay
#define CPUdelay NOROM_CPUdelay
#endif
//*****************************************************************************
//
// Disable all external interrupts
//
//*****************************************************************************
#if defined(DOXYGEN)
uint32_t
CPUcpsid(void)
{
// This function is written in assembly. See cpu.c for compiler specific implementation.
}
#elif defined(__IAR_SYSTEMS_ICC__)
uint32_t
CPUcpsid(void)
{
// Read PRIMASK and disable interrupts.
__asm(" mrs r0, PRIMASK\n"
" cpsid i\n");
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
__asm uint32_t
CPUcpsid(void)
{
// Read PRIMASK and disable interrupts.
mrs r0, PRIMASK;
cpsid i;
bx lr
}
#elif defined(__TI_COMPILER_VERSION__)
uint32_t
CPUcpsid(void)
{
// Read PRIMASK and disable interrupts.
__asm(" mrs r0, PRIMASK\n"
" cpsid i\n"
" bx lr\n");
// The following keeps the compiler happy, because it wants to see a
// return value from this function. It will generate code to return
// a zero. However, the real return is the "bx lr" above, so the
// return(0) is never executed and the function returns with the value
// you expect in R0.
return(0);
}
#else
uint32_t __attribute__((naked))
CPUcpsid(void)
{
uint32_t ui32Ret;
// Read PRIMASK and disable interrupts
__asm volatile (" mrs %0, PRIMASK\n"
" cpsid i\n"
" bx lr\n"
: "=r"(ui32Ret)
);
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
return(ui32Ret);
}
#endif
//*****************************************************************************
//
// Get the current interrupt state
//
//*****************************************************************************
#if defined(DOXYGEN)
uint32_t
CPUprimask(void)
{
// This function is written in assembly. See cpu.c for compiler specific implementation.
}
#elif defined(__IAR_SYSTEMS_ICC__)
uint32_t
CPUprimask(void)
{
// Read PRIMASK.
__asm(" mrs r0, PRIMASK\n");
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
__asm uint32_t
CPUprimask(void)
{
// Read PRIMASK.
mrs r0, PRIMASK;
bx lr
}
#elif defined(__TI_COMPILER_VERSION__)
uint32_t
CPUprimask(void)
{
// Read PRIMASK.
__asm(" mrs r0, PRIMASK\n"
" bx lr\n");
// The following keeps the compiler happy, because it wants to see a
// return value from this function. It will generate code to return
// a zero. However, the real return is the "bx lr" above, so the
// return(0) is never executed and the function returns with the value
// you expect in R0.
return(0);
}
#else
uint32_t __attribute__((naked))
CPUprimask(void)
{
uint32_t ui32Ret;
// Read PRIMASK
__asm volatile (" mrs %0, PRIMASK\n"
" bx lr\n"
: "=r"(ui32Ret)
);
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
return(ui32Ret);
}
#endif
//*****************************************************************************
//
// Enable all external interrupts
//
//*****************************************************************************
#if defined(DOXYGEN)
uint32_t
CPUcpsie(void)
{
// This function is written in assembly. See cpu.c for compiler specific implementation.
}
#elif defined(__IAR_SYSTEMS_ICC__)
uint32_t
CPUcpsie(void)
{
// Read PRIMASK and enable interrupts.
__asm(" mrs r0, PRIMASK\n"
" cpsie i\n");
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
__asm uint32_t
CPUcpsie(void)
{
// Read PRIMASK and enable interrupts.
mrs r0, PRIMASK;
cpsie i;
bx lr
}
#elif defined(__TI_COMPILER_VERSION__)
uint32_t
CPUcpsie(void)
{
// Read PRIMASK and enable interrupts.
__asm(" mrs r0, PRIMASK\n"
" cpsie i\n"
" bx lr\n");
// The following keeps the compiler happy, because it wants to see a
// return value from this function. It will generate code to return
// a zero. However, the real return is the "bx lr" above, so the
// return(0) is never executed and the function returns with the value
// you expect in R0.
return(0);
}
#else
uint32_t __attribute__((naked))
CPUcpsie(void)
{
uint32_t ui32Ret;
// Read PRIMASK and enable interrupts.
__asm volatile (" mrs %0, PRIMASK\n"
" cpsie i\n"
" bx lr\n"
: "=r"(ui32Ret)
);
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
return(ui32Ret);
}
#endif
//*****************************************************************************
//
// Get the interrupt priority disable level
//
//*****************************************************************************
#if defined(DOXYGEN)
uint32_t
CPUbasepriGet(void)
{
// This function is written in assembly. See cpu.c for compiler specific implementation.
}
#elif defined(__IAR_SYSTEMS_ICC__)
uint32_t
CPUbasepriGet(void)
{
// Read BASEPRI.
__asm(" mrs r0, BASEPRI\n");
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
__asm uint32_t
CPUbasepriGet(void)
{
// Read BASEPRI.
mrs r0, BASEPRI;
bx lr
}
#elif defined(__TI_COMPILER_VERSION__)
uint32_t
CPUbasepriGet(void)
{
// Read BASEPRI.
__asm(" mrs r0, BASEPRI\n"
" bx lr\n");
// The following keeps the compiler happy, because it wants to see a
// return value from this function. It will generate code to return
// a zero. However, the real return is the "bx lr" above, so the
// return(0) is never executed and the function returns with the value
// you expect in R0.
return(0);
}
#else
uint32_t __attribute__((naked))
CPUbasepriGet(void)
{
uint32_t ui32Ret;
// Read BASEPRI.
__asm volatile (" mrs %0, BASEPRI\n"
" bx lr\n"
: "=r"(ui32Ret)
);
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
return(ui32Ret);
}
#endif
//*****************************************************************************
//
// Provide a small delay
//
//*****************************************************************************
#if defined(DOXYGEN)
void
CPUdelay(uint32_t ui32Count)
{
// This function is written in assembly. See cpu.c for compiler specific implementation.
}
#elif defined(__IAR_SYSTEMS_ICC__)
void
CPUdelay(uint32_t ui32Count)
{
// Loop the specified number of times
__asm("CPUdelay:\n"
" subs r0, #1\n"
" bne.n CPUdelay\n"
" bx lr");
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
__asm void
CPUdelay(uint32_t ui32Count)
{
// Delay the specified number of times (3 cycles pr. loop)
CPUdel
subs r0, #1;
bne CPUdel;
bx lr;
}
#elif defined(__TI_COMPILER_VERSION__)
// For CCS implement this function in pure assembly. This prevents the TI
// compiler from doing funny things with the optimizer.
// Loop the specified number of times
__asm(" .sect \".text:NOROM_CPUdelay\"\n"
" .clink\n"
" .thumbfunc NOROM_CPUdelay\n"
" .thumb\n"
" .global NOROM_CPUdelay\n"
"NOROM_CPUdelay:\n"
" subs r0, #1\n"
" bne.n NOROM_CPUdelay\n"
" bx lr\n");
#else
// GCC
void __attribute__((naked))
CPUdelay(uint32_t ui32Count)
{
// Loop the specified number of times
__asm volatile ("%=: subs %0, #1\n"
" bne %=b\n"
" bx lr\n"
: /* No output */
: "r" (ui32Count)
);
}
#endif

466
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/cpu.h
View file

@ -1,466 +0,0 @@
/******************************************************************************
* Filename: cpu.h
* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018)
* Revision: 52111
*
* Description: Defines and prototypes for the CPU instruction wrapper
* functions.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup system_cpu_group
//! @{
//! \addtogroup cpu_api
//! @{
//
//*****************************************************************************
#ifndef __CPU_H__
#define __CPU_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdbool.h>
#include <stdint.h>
#include "../inc/hw_types.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_cpu_scs.h"
//*****************************************************************************
//
// Support for DriverLib in ROM:
// This section renames all functions that are not "static inline", so that
// calling these functions will default to implementation in flash. At the end
// of this file a second renaming will change the defaults to implementation in
// ROM for available functions.
//
// To force use of the implementation in flash, e.g. for debugging:
// - Globally: Define DRIVERLIB_NOROM at project level
// - Per function: Use prefix "NOROM_" when calling the function
//
//*****************************************************************************
#if !defined(DOXYGEN)
#define CPUcpsid NOROM_CPUcpsid
#define CPUprimask NOROM_CPUprimask
#define CPUcpsie NOROM_CPUcpsie
#define CPUbasepriGet NOROM_CPUbasepriGet
#define CPUdelay NOROM_CPUdelay
#endif
//*****************************************************************************
//
// API Functions and prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Disable all external interrupts.
//!
//! Use this function to disable all system interrupts. This function is
//! implemented as a wrapper function for the CPSID instruction.
//!
//! \return Returns the state of \b PRIMASK on entry
//
//*****************************************************************************
extern uint32_t CPUcpsid(void);
//*****************************************************************************
//
//! \brief Get the current interrupt state.
//!
//! Use this function to retrieve the current state of the interrupts. This
//! function is implemented as a wrapper function returning the state of
//! PRIMASK.
//!
//! \return Returns the state of the \b PRIMASK (indicating whether interrupts
//! are enabled or disabled).
//
//*****************************************************************************
extern uint32_t CPUprimask(void);
//*****************************************************************************
//
//! \brief Enable all external interrupts.
//!
//! Use this function to enable all system interrupts. This function is
//! implemented as a wrapper function for the CPSIE instruction.
//!
//! \return Returns the state of \b PRIMASK on entry.
//
//*****************************************************************************
extern uint32_t CPUcpsie(void);
//*****************************************************************************
//
//! \brief Get the interrupt priority disable level.
//!
//! Use this function to get the level of priority that will disable
//! interrupts with a lower priority level.
//!
//! \return Returns the value of the \b BASEPRI register.
//
//*****************************************************************************
extern uint32_t CPUbasepriGet(void);
//*****************************************************************************
//
//! \brief Provide a small non-zero delay using a simple loop counter.
//!
//! This function provides means for generating a constant length delay. It
//! is written in assembly to keep the delay consistent across tool chains,
//! avoiding the need to tune the delay based on the tool chain in use.
//!
//! \note It is not recommended using this function for long delays.
//!
//! Notice that interrupts can affect the delay if not manually disabled in advance.
//!
//! The delay depends on where code resides and the path for code fetching:
//! - Code in flash, cache enabled, prefetch enabled : 4 cycles per loop (Default)
//! - Code in flash, cache enabled, prefetch disabled : 5 cycles per loop
//! - Code in flash, cache disabled : 7 cycles per loop
//! - Code in SRAM : 6 cycles per loop
//! - Code in GPRAM : 3 cycles per loop
//!
//! \note If using an RTOS, consider using RTOS provided delay functions because
//! these will not block task scheduling and will potentially save power.
//!
//! Calculate delay count based on the wanted delay in microseconds (us):
//! - ui32Count = [delay in us] * [CPU clock in MHz] / [cycles per loop]
//!
//! Example: 250 us delay with code in flash and with cache and prefetch enabled:
//! - ui32Count = 250 * 48 / 4 = 3000
//!
//! \param ui32Count is the number of delay loop iterations to perform. Number must be greater than zero.
//!
//! \return None
//
//*****************************************************************************
extern void CPUdelay(uint32_t ui32Count);
//*****************************************************************************
//
//! \brief Wait for interrupt.
//!
//! Use this function to let the System CPU wait for the next interrupt. This
//! function is implemented as a wrapper function for the WFI instruction.
//!
//! \return None
//
//*****************************************************************************
#if defined(DOXYGEN)
__STATIC_INLINE void
CPUwfi(void)
{
// This function is written in assembly. See cpu.h for compiler specific implementation.
}
#elif defined(__IAR_SYSTEMS_ICC__)
__STATIC_INLINE void
CPUwfi(void)
{
// Wait for the next interrupt.
__asm(" wfi\n");
}
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
__asm __STATIC_INLINE void
CPUwfi(void)
{
// Wait for the next interrupt.
wfi;
bx lr
}
#elif defined(__TI_COMPILER_VERSION__)
__STATIC_INLINE void
CPUwfi(void)
{
// Wait for the next interrupt.
__asm(" wfi\n");
}
#else
__STATIC_INLINE void __attribute__((always_inline))
CPUwfi(void)
{
// Wait for the next interrupt.
__asm volatile (" wfi\n");
}
#endif
//*****************************************************************************
//
//! \brief Wait for event.
//!
//! Use this function to let the System CPU wait for the next event. This
//! function is implemented as a wrapper function for the WFE instruction.
//!
//! \return None
//
//*****************************************************************************
#if defined(DOXYGEN)
__STATIC_INLINE void
CPUwfe(void)
{
// This function is written in assembly. See cpu.h for compiler specific implementation.
}
#elif defined(__IAR_SYSTEMS_ICC__)
__STATIC_INLINE void
CPUwfe(void)
{
// Wait for the next event.
__asm(" wfe\n");
}
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
__asm __STATIC_INLINE void
CPUwfe(void)
{
// Wait for the next event.
wfe;
bx lr
}
#elif defined(__TI_COMPILER_VERSION__)
__STATIC_INLINE void
CPUwfe(void)
{
// Wait for the next event.
__asm(" wfe\n");
}
#else
__STATIC_INLINE void __attribute__((always_inline))
CPUwfe(void)
{
// Wait for the next event.
__asm volatile (" wfe\n");
}
#endif
//*****************************************************************************
//
//! \brief Send event.
//!
//! Use this function to let the System CPU send an event. This function is
//! implemented as a wrapper function for the SEV instruction.
//!
//! \return None
//
//*****************************************************************************
#if defined(DOXYGEN)
__STATIC_INLINE void
CPUsev(void)
{
// This function is written in assembly. See cpu.h for compiler specific implementation.
}
#elif defined(__IAR_SYSTEMS_ICC__)
__STATIC_INLINE void
CPUsev(void)
{
// Send event.
__asm(" sev\n");
}
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
__asm __STATIC_INLINE void
CPUsev(void)
{
// Send event.
sev;
bx lr
}
#elif defined(__TI_COMPILER_VERSION__)
__STATIC_INLINE void
CPUsev(void)
{
// Send event.
__asm(" sev\n");
}
#else
__STATIC_INLINE void __attribute__((always_inline))
CPUsev(void)
{
// Send event.
__asm volatile (" sev\n");
}
#endif
//*****************************************************************************
//
//! \brief Update the interrupt priority disable level.
//!
//! Use this function to change the level of priority that will disable
//! interrupts with a lower priority level.
//!
//! \param ui32NewBasepri is the new basis priority level to set.
//!
//! \return None
//
//*****************************************************************************
#if defined(DOXYGEN)
__STATIC_INLINE void
CPUbasepriSet(uint32_t ui32NewBasepri)
{
// This function is written in assembly. See cpu.h for compiler specific implementation.
}
#elif defined(__IAR_SYSTEMS_ICC__)
__STATIC_INLINE void
CPUbasepriSet(uint32_t ui32NewBasepri)
{
// Set the BASEPRI register.
__asm(" msr BASEPRI, r0\n");
}
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
__asm __STATIC_INLINE void
CPUbasepriSet(uint32_t ui32NewBasepri)
{
// Set the BASEPRI register.
msr BASEPRI, r0;
bx lr
}
#elif defined(__TI_COMPILER_VERSION__)
__STATIC_INLINE void
CPUbasepriSet(uint32_t ui32NewBasepri)
{
// Set the BASEPRI register.
__asm(" msr BASEPRI, r0\n");
}
#else
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wattributes"
__STATIC_INLINE void __attribute__ ((naked))
CPUbasepriSet(uint32_t ui32NewBasepri)
{
// Set the BASEPRI register.
__asm volatile (" msr BASEPRI, %0\n"
" bx lr\n"
: /* No output */
: "r" (ui32NewBasepri)
);
}
#pragma GCC diagnostic pop
#endif
//*****************************************************************************
//
//! \brief Disable CPU write buffering (recommended for debug purpose only).
//!
//! This function helps debugging "bus fault crashes".
//! Disables write buffer use during default memory map accesses.
//!
//! This causes all bus faults to be precise bus faults but decreases the
//! performance of the processor because the stores to memory have to complete
//! before the next instruction can be executed.
//!
//! \return None
//!
//! \sa \ref CPU_WriteBufferEnable()
//
//*****************************************************************************
__STATIC_INLINE void
CPU_WriteBufferDisable( void )
{
HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 1;
}
//*****************************************************************************
//
//! \brief Enable CPU write buffering (default setting).
//!
//! Re-enables write buffer during default memory map accesses if
//! \ref CPU_WriteBufferDisable() has been used for bus fault debugging.
//!
//! \return None
//!
//! \sa \ref CPU_WriteBufferDisable()
//
//*****************************************************************************
__STATIC_INLINE void
CPU_WriteBufferEnable( void )
{
HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 0;
}
//*****************************************************************************
//
// Support for DriverLib in ROM:
// Redirect to implementation in ROM when available.
//
//*****************************************************************************
#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
#include "../driverlib/rom.h"
#ifdef ROM_CPUcpsid
#undef CPUcpsid
#define CPUcpsid ROM_CPUcpsid
#endif
#ifdef ROM_CPUprimask
#undef CPUprimask
#define CPUprimask ROM_CPUprimask
#endif
#ifdef ROM_CPUcpsie
#undef CPUcpsie
#define CPUcpsie ROM_CPUcpsie
#endif
#ifdef ROM_CPUbasepriGet
#undef CPUbasepriGet
#define CPUbasepriGet ROM_CPUbasepriGet
#endif
#ifdef ROM_CPUdelay
#undef CPUdelay
#define CPUdelay ROM_CPUdelay
#endif
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __CPU_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

44
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/cpu_doc.h
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@ -1,44 +0,0 @@
/******************************************************************************
* Filename: cpu_doc.h
* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016)
* Revision: 45971
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//! \addtogroup cpu_api
//! @{
//! \section sec_cpu Introduction
//!
//! The CPU API provides a set of functions performing very low-level control of the system CPU.
//! All functions in this API are written in assembler in order to either access special registers
//! or avoid any compiler optimizations. Each function exists in several compiler specific versions:
//! One version for each supported compiler.
//! @}

943
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/crypto.c
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@ -1,943 +0,0 @@
/******************************************************************************
* Filename: crypto.c
* Revised: 2017-12-20 16:40:03 +0100 (Wed, 20 Dec 2017)
* Revision: 50869
*
* Description: Driver for the Crypto module
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "crypto.h"
//*****************************************************************************
//
// Handle support for DriverLib in ROM:
// This section will undo prototype renaming made in the header file
//
//*****************************************************************************
#if !defined(DOXYGEN)
#undef CRYPTOAesLoadKey
#define CRYPTOAesLoadKey NOROM_CRYPTOAesLoadKey
#undef CRYPTOAesCbc
#define CRYPTOAesCbc NOROM_CRYPTOAesCbc
#undef CRYPTOAesCbcStatus
#define CRYPTOAesCbcStatus NOROM_CRYPTOAesCbcStatus
#undef CRYPTOAesEcb
#define CRYPTOAesEcb NOROM_CRYPTOAesEcb
#undef CRYPTOAesEcbStatus
#define CRYPTOAesEcbStatus NOROM_CRYPTOAesEcbStatus
#undef CRYPTOCcmAuthEncrypt
#define CRYPTOCcmAuthEncrypt NOROM_CRYPTOCcmAuthEncrypt
#undef CRYPTOCcmAuthEncryptStatus
#define CRYPTOCcmAuthEncryptStatus NOROM_CRYPTOCcmAuthEncryptStatus
#undef CRYPTOCcmAuthEncryptResultGet
#define CRYPTOCcmAuthEncryptResultGet NOROM_CRYPTOCcmAuthEncryptResultGet
#undef CRYPTOCcmInvAuthDecrypt
#define CRYPTOCcmInvAuthDecrypt NOROM_CRYPTOCcmInvAuthDecrypt
#undef CRYPTOCcmInvAuthDecryptStatus
#define CRYPTOCcmInvAuthDecryptStatus NOROM_CRYPTOCcmInvAuthDecryptStatus
#undef CRYPTOCcmInvAuthDecryptResultGet
#define CRYPTOCcmInvAuthDecryptResultGet NOROM_CRYPTOCcmInvAuthDecryptResultGet
#undef CRYPTODmaEnable
#define CRYPTODmaEnable NOROM_CRYPTODmaEnable
#undef CRYPTODmaDisable
#define CRYPTODmaDisable NOROM_CRYPTODmaDisable
#endif
//*****************************************************************************
//
// Write the key into the Key Ram.
//
//*****************************************************************************
uint32_t
CRYPTOAesLoadKey(uint32_t *pui32AesKey,
uint32_t ui32KeyLocation)
{
uint32_t returnStatus = AES_KEYSTORE_READ_ERROR;
// Check the arguments.
ASSERT((ui32KeyLocation == CRYPTO_KEY_AREA_0) |
(ui32KeyLocation == CRYPTO_KEY_AREA_1) |
(ui32KeyLocation == CRYPTO_KEY_AREA_2) |
(ui32KeyLocation == CRYPTO_KEY_AREA_3) |
(ui32KeyLocation == CRYPTO_KEY_AREA_4) |
(ui32KeyLocation == CRYPTO_KEY_AREA_5) |
(ui32KeyLocation == CRYPTO_KEY_AREA_6) |
(ui32KeyLocation == CRYPTO_KEY_AREA_7));
// Disable the external interrupt to stop the interrupt form propagating
// from the module to the System CPU.
IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);
// Clear any previously written key at the keyLocation
HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) = (0x00000001 << ui32KeyLocation);
// Enable internal interrupts.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL;
HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE |
CRYPTO_IRQEN_RESULT_AVAIL;
// Configure master control module.
HWREGBITW(CRYPTO_BASE + CRYPTO_O_ALGSEL, CRYPTO_ALGSEL_KEY_STORE_BITN) = 1;
// Clear any outstanding events.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
CRYPTO_IRQCLR_RESULT_AVAIL);
// Configure key store module for 128 bit operation.
// Do not write to the register if the correct key size is already set.
// Writing to this register causes all current keys to be invalidated.
if (HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) != KEY_STORE_SIZE_128) {
HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) = KEY_STORE_SIZE_128;
}
// Enable keys to write (e.g. Key 0).
HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITEAREA) = (0x00000001 << ui32KeyLocation);
// Enable Crypto DMA channel 0.
HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;
// Base address of the key in ext. memory.
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32AesKey;
// Total key length in bytes (e.g. 16 for 1 x 128-bit key).
// Writing the length of the key enables the DMA operation.
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = KEY_BLENGTH;
// Wait for the DMA operation to complete.
do
{
CPUdelay(1);
}
while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) &
(CRYPTO_IRQSTAT_DMA_BUS_ERR_M |
CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M |
CRYPTO_IRQSTAT_DMA_IN_DONE |
CRYPTO_IRQSTAT_RESULT_AVAIL_M)));
// Check for errors in DMA and key store.
if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) &
(CRYPTO_IRQSTAT_DMA_BUS_ERR |
CRYPTO_IRQSTAT_KEY_ST_WR_ERR)) == 0)
{
// Acknowledge/clear the interrupt and disable the master control.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
CRYPTO_IRQCLR_RESULT_AVAIL);
HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000;
// Check key status, return success if key valid.
if(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (0x00000001 << ui32KeyLocation))
{
returnStatus = AES_SUCCESS;
}
}
// Return status.
return returnStatus;
}
//*****************************************************************************
//
// Start an AES-CBC operation (encryption or decryption).
//
//*****************************************************************************
uint32_t
CRYPTOAesCbc(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, uint32_t ui32MsgLength,
uint32_t *pui32Nonce, uint32_t ui32KeyLocation,
bool bEncrypt, bool bIntEnable)
{
uint32_t ui32CtrlVal;
// Enable internal interrupts.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL;
HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL;
// Clear any outstanding interrupts.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
CRYPTO_IRQCLR_RESULT_AVAIL);
// Wait for interrupt lines from module to be cleared
while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL));
// If using interrupts clear any pending interrupts and enable interrupts
// for the Crypto module.
if(bIntEnable)
{
IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ);
IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ);
}
// Configure Master Control module.
HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES;
// Enable keys to read (e.g. Key 0).
HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation;
//Wait until key is loaded to the AES module.
do
{
CPUdelay(1);
}
while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY));
// Check for Key store Read error.
if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR))
{
return (AES_KEYSTORE_READ_ERROR);
}
// Write initialization vector.
HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = pui32Nonce[0];
HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = pui32Nonce[1];
HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = pui32Nonce[2];
HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = pui32Nonce[3];
// Configure AES engine for AES-CBC with 128-bit key size.
ui32CtrlVal = (CRYPTO_AESCTL_SAVE_CONTEXT | CRYPTO_AESCTL_CBC);
if(bEncrypt)
{
ui32CtrlVal |= CRYPTO_AES128_ENCRYPT;
}
else
{
ui32CtrlVal |= CRYPTO_AES128_DECRYPT;
}
HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ui32CtrlVal;
// Write the length of the crypto block (plain text).
// Low and high part (high part is assumed to be always 0).
HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = ui32MsgLength;
HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0;
HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = 0;
// Enable Crypto DMA channel 0.
HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;
// Base address of the input data in ext. memory.
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32MsgIn;
// Input data length in bytes, equal to the message.
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32MsgLength;
// Enable Crypto DMA channel 1.
HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1;
// Set up the address and length of the output data.
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)pui32MsgOut;
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = ui32MsgLength;
// Return success
return AES_SUCCESS;
}
//*****************************************************************************
//
// Check the result of an AES CBC operation
//
//*****************************************************************************
uint32_t
CRYPTOAesCbcStatus(void)
{
return(CRYPTOAesEcbStatus());
}
//*****************************************************************************
//
// Start an AES-ECB operation (encryption or decryption).
//
//*****************************************************************************
uint32_t
CRYPTOAesEcb(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut,
uint32_t ui32KeyLocation, bool bEncrypt,
bool bIntEnable)
{
// Enable internal interrupts.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL;
HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL;
// Clear any outstanding interrupts.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
CRYPTO_IRQCLR_RESULT_AVAIL);
// Wait for interrupt lines from module to be cleared
while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL));
// If using interrupts clear any pending interrupts and enable interrupts
// for the Crypto module.
if(bIntEnable)
{
IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ);
IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ);
}
// Configure Master Control module.
HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES;
// Enable keys to read (e.g. Key 0).
HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation;
//Wait until key is loaded to the AES module.
do
{
CPUdelay(1);
}
while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY));
// Check for Key store Read error.
if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR))
{
return (AES_KEYSTORE_READ_ERROR);
}
// Configure AES engine (program AES-ECB-128 encryption and no
// initialization vector - IV).
if(bEncrypt)
{
HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = CRYPTO_AES128_ENCRYPT;
}
else
{
HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = CRYPTO_AES128_DECRYPT;
}
// Write the length of the data.
HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = AES_ECB_LENGTH;
HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0;
// Enable Crypto DMA channel 0.
HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;
// Base address of the input data in ext. memory.
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32MsgIn;
// Input data length in bytes, equal to the message.
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = AES_ECB_LENGTH;
// Enable Crypto DMA channel 1.
HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1;
// Set up the address and length of the output data.
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)pui32MsgOut;
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = AES_ECB_LENGTH;
// Return success
return AES_SUCCESS;
}
//*****************************************************************************
//
// Check the result of an AES ECB operation
//
//*****************************************************************************
uint32_t
CRYPTOAesEcbStatus(void)
{
uint32_t ui32Status;
// Get the current DMA status.
ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT);
// Check if DMA is still busy.
if(ui32Status & CRYPTO_DMA_BSY)
{
return (AES_DMA_BSY);
}
// Check the status of the DMA operation - return error if not success.
if(ui32Status & CRYPTO_DMA_BUS_ERROR)
{
return (AES_DMA_BUS_ERROR);
}
// Operation successful - disable interrupt and return success.
IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);
return (AES_SUCCESS);
}
//*****************************************************************************
//
// Start CCM operation
//
//*****************************************************************************
uint32_t
CRYPTOCcmAuthEncrypt(bool bEncrypt, uint32_t ui32AuthLength ,
uint32_t *pui32Nonce, uint32_t *pui32PlainText,
uint32_t ui32PlainTextLength, uint32_t *pui32Header,
uint32_t ui32HeaderLength, uint32_t ui32KeyLocation,
uint32_t ui32FieldLength, bool bIntEnable)
{
uint32_t ui32CtrlVal;
uint32_t i;
uint32_t *pui32CipherText;
union {
uint32_t w[4];
uint8_t b[16];
} ui8InitVec;
// Input address for the encryption engine is the same as the output.
pui32CipherText = pui32PlainText;
// Disable global interrupt, enable local interrupt and clear any pending
// interrupts.
IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);
HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
CRYPTO_IRQCLR_RESULT_AVAIL);
// Enable internal interrupts.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL;
HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE |
CRYPTO_IRQEN_RESULT_AVAIL;
// Configure master control module for AES operation.
HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES;
// Enable keys to read (e.g. Key 0).
HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation;
// Wait until key is loaded to the AES module.
do
{
CPUdelay(1);
}
while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY));
// Check for Key store Read error.
if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR))
{
return (AES_KEYSTORE_READ_ERROR);
}
// Prepare the initialization vector (IV),
// Length of Nonce l(n) = 15 - ui32FieldLength.
ui8InitVec.b[0] = ui32FieldLength - 1;
for(i = 0; i < 12; i++)
{
ui8InitVec.b[i + 1] = ((uint8_t*)pui32Nonce)[i];
}
if(ui32FieldLength == 2)
{
ui8InitVec.b[13] = ((uint8_t*)pui32Nonce)[12];
}
else
{
ui8InitVec.b[13] = 0;
}
ui8InitVec.b[14] = 0;
ui8InitVec.b[15] = 0;
// Write initialization vector.
HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = ui8InitVec.w[0];
HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = ui8InitVec.w[1];
HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = ui8InitVec.w[2];
HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = ui8InitVec.w[3];
// Configure AES engine.
ui32CtrlVal = ((ui32FieldLength - 1) << CRYPTO_AESCTL_CCM_L_S);
if ( ui32AuthLength >= 2 ) {
ui32CtrlVal |= ((( ui32AuthLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S );
}
ui32CtrlVal |= CRYPTO_AESCTL_CCM;
ui32CtrlVal |= CRYPTO_AESCTL_CTR;
ui32CtrlVal |= CRYPTO_AESCTL_SAVE_CONTEXT;
ui32CtrlVal |= (KEY_STORE_SIZE_128 << CRYPTO_AESCTL_KEY_SIZE_S);
ui32CtrlVal |= (1 << CRYPTO_AESCTL_DIR_S);
ui32CtrlVal |= (CRYPTO_AES_CTR_128 << CRYPTO_AESCTL_CTR_WIDTH_S);
// Write the configuration for 128 bit AES-CCM.
HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ui32CtrlVal;
// Write the length of the crypto block (plain text).
// Low and high part (high part is assumed to be always 0).
HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = ui32PlainTextLength;
HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0;
// Write the length of the header field.
// Also called AAD - Additional Authentication Data.
HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = ui32HeaderLength;
// Check if any header information (AAD).
// If so configure the DMA controller to fetch the header.
if(ui32HeaderLength != 0)
{
// Enable DMA channel 0.
HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;
// Register the base address of the header (AAD).
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32Header;
// Header length in bytes (may be non-block size aligned).
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32HeaderLength;
// Wait for completion of the header data transfer, DMA_IN_DONE.
do
{
CPUdelay(1);
}
while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_DMA_IN_DONE));
// Check for DMA errors.
if(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_DMA_BUS_ERR)
{
return AES_DMA_BUS_ERROR;
}
}
// Clear interrupt status.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
CRYPTO_IRQCLR_RESULT_AVAIL);
// Wait for interrupt lines from module to be cleared
while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL));
// Disable CRYPTO_IRQEN_DMA_IN_DONE interrupt as we only
// want interrupt to trigger once RESULT_AVAIL occurs.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~CRYPTO_IRQEN_DMA_IN_DONE;
// Is using interrupts enable globally.
if(bIntEnable)
{
IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ);
IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ);
}
// Enable interrupts locally.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL;
// Perform encryption if requested.
if(bEncrypt)
{
// Enable DMA channel 0
HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;
// base address of the payload data in ext. memory.
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) =
(uint32_t)pui32PlainText;
// Enable DMA channel 1
HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1;
// Base address of the output data buffer.
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) =
(uint32_t)pui32CipherText;
// Payload data length in bytes, equal to the plaintext length.
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32PlainTextLength;
// Output data length in bytes, equal to the plaintext length.
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = ui32PlainTextLength;
}
return AES_SUCCESS;
}
//*****************************************************************************
//
// Check the result of an AES CCM operation.
//
//*****************************************************************************
uint32_t
CRYPTOCcmAuthEncryptStatus(void)
{
uint32_t ui32Status;
// Get the current DMA status.
ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT);
// Check if DMA is still busy.
if(ui32Status & CRYPTO_DMA_BSY)
{
return (AES_DMA_BSY);
}
// Check the status of the DMA operation - return error if not success.
if(ui32Status & CRYPTO_DMA_BUS_ERROR)
{
return (AES_DMA_BUS_ERROR);
}
// Operation successful - disable interrupt and return success.
IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);
return (AES_SUCCESS);
}
//*****************************************************************************
//
// Get the result of an AES-CCM operation
//
//*****************************************************************************
uint32_t
CRYPTOCcmAuthEncryptResultGet(uint32_t ui32TagLength, uint32_t *pui32CcmTag)
{
uint32_t volatile ui32Tag[4];
uint32_t ui32Idx;
// Result has already been copied to the output buffer by DMA
// Disable master control.
HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000;
// Read tag - wait for the context ready bit.
do
{
CPUdelay(1);
}
while(!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) &
CRYPTO_AESCTL_SAVED_CONTEXT_RDY));
// Read the Tag registers.
ui32Tag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0);
ui32Tag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1);
ui32Tag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2);
ui32Tag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3);
for(ui32Idx = 0; ui32Idx < ui32TagLength ; ui32Idx++)
{
*((uint8_t*)pui32CcmTag + ui32Idx) = *((uint8_t*)ui32Tag + ui32Idx);
}
// Operation successful - clear interrupt status.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
CRYPTO_IRQCLR_RESULT_AVAIL);
return AES_SUCCESS;
}
//*****************************************************************************
//
// Start a CCM Decryption and Inverse Authentication operation.
//
//*****************************************************************************
uint32_t
CRYPTOCcmInvAuthDecrypt(bool bDecrypt, uint32_t ui32AuthLength,
uint32_t *pui32Nonce, uint32_t *pui32CipherText,
uint32_t ui32CipherTextLength,
uint32_t *pui32Header, uint32_t ui32HeaderLength,
uint32_t ui32KeyLocation,
uint32_t ui32FieldLength, bool bIntEnable)
{
uint32_t ui32CtrlVal;
uint32_t i;
uint32_t *pui32PlainText;
uint32_t ui32CryptoBlockLength;
union {
uint32_t w[4];
uint8_t b[16];
} ui8InitVec;
// Input address for the encryption engine is the same as the output.
pui32PlainText = pui32CipherText;
// Disable global interrupt, enable local interrupt and clear any pending.
// interrupts.
IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);
HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
CRYPTO_IRQCLR_RESULT_AVAIL);
// Enable internal interrupts.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL;
HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE |
CRYPTO_IRQEN_RESULT_AVAIL;
// Configure master control module for AES operation.
HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES;
// Enable keys to read (e.g. Key 0).
HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation;
// Wait until key is loaded to the AES module.
do
{
CPUdelay(1);
}
while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY));
// Check for Key store Read error.
if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR))
{
return (AES_KEYSTORE_READ_ERROR);
}
// Prepare the initialization vector (IV),
// Length of Nonce l(n) = 15 - ui32FieldLength.
ui8InitVec.b[0] = ui32FieldLength - 1;
for(i = 0; i < 12; i++)
{
ui8InitVec.b[i + 1] = ((uint8_t*)pui32Nonce)[i];
}
if(ui32FieldLength == 2)
{
ui8InitVec.b[13] = ((uint8_t*)pui32Nonce)[12];
}
else
{
ui8InitVec.b[13] = 0;
}
ui8InitVec.b[14] = 0;
ui8InitVec.b[15] = 0;
// Write initialization vector.
HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = ui8InitVec.w[0];
HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = ui8InitVec.w[1];
HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = ui8InitVec.w[2];
HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = ui8InitVec.w[3];
// Configure AES engine
ui32CryptoBlockLength = ui32CipherTextLength - ui32AuthLength;
ui32CtrlVal = ((ui32FieldLength - 1) << CRYPTO_AESCTL_CCM_L_S);
if ( ui32AuthLength >= 2 ) {
ui32CtrlVal |= ((( ui32AuthLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S );
}
ui32CtrlVal |= CRYPTO_AESCTL_CCM;
ui32CtrlVal |= CRYPTO_AESCTL_CTR;
ui32CtrlVal |= CRYPTO_AESCTL_SAVE_CONTEXT;
ui32CtrlVal |= (KEY_STORE_SIZE_128 << CRYPTO_AESCTL_KEY_SIZE_S);
ui32CtrlVal |= (0 << CRYPTO_AESCTL_DIR_S);
ui32CtrlVal |= (CRYPTO_AES_CTR_128 << CRYPTO_AESCTL_CTR_WIDTH_S);
// Write the configuration for 128 bit AES-CCM.
HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ui32CtrlVal;
// Write the length of the crypto block (plain text).
// Low and high part (high part is assumed to be always 0).
HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = ui32CryptoBlockLength;
HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0;
// Write the length of the header field.
// Also called AAD - Additional Authentication Data.
HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = ui32HeaderLength;
// Check if any header information (AAD).
// If so configure the DMA controller to fetch the header.
if(ui32HeaderLength != 0)
{
// Enable DMA channel 0.
HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;
// Register the base address of the header (AAD).
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32Header;
// Header length in bytes (may be non-block size aligned).
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32HeaderLength;
// Wait for completion of the header data transfer, DMA_IN_DONE.
do
{
CPUdelay(1);
}
while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_DMA_IN_DONE));
// Check for DMA errors.
if(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_DMA_BUS_ERR)
{
return AES_DMA_BUS_ERROR;
}
}
// Clear interrupt status.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
CRYPTO_IRQCLR_RESULT_AVAIL);
// Wait for interrupt lines from module to be cleared
while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL));
// Disable CRYPTO_IRQEN_DMA_IN_DONE interrupt as we only
// want interrupt to trigger once RESULT_AVAIL occurs.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~CRYPTO_IRQEN_DMA_IN_DONE;
// Is using interrupts - clear and enable globally.
if(bIntEnable)
{
IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ);
IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ);
}
// Enable internal interrupts.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL;
HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL;
// Perform decryption if requested.
if(bDecrypt)
{
// Configure the DMA controller - enable both DMA channels.
HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;
// Base address of the payload data in ext. memory.
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) =
(uint32_t)pui32CipherText;
// Payload data length in bytes, equal to the cipher text length.
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32CryptoBlockLength;
// Enable DMA channel 1.
HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1;
// Base address of the output data buffer.
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) =
(uint32_t)pui32PlainText;
// Output data length in bytes, equal to the cipher text length.
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = ui32CryptoBlockLength;
}
return AES_SUCCESS;
}
//*****************************************************************************
//
// Checks CCM decrypt and Inverse Authentication result.
//
//*****************************************************************************
uint32_t
CRYPTOCcmInvAuthDecryptStatus(void)
{
uint32_t ui32Status;
// Get the current DMA status.
ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT);
// Check if DMA is still busy.
if(ui32Status & CRYPTO_DMA_BSY)
{
return (AES_DMA_BSY);
}
// Check the status of the DMA operation - return error if not success.
if(ui32Status & CRYPTO_DMA_BUS_ERROR)
{
return (AES_DMA_BUS_ERROR);
}
// Operation successful - disable interrupt and return success
IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);
return (AES_SUCCESS);
}
//*****************************************************************************
//
// Get the result of the CCM operation.
//
//*****************************************************************************
uint32_t
CRYPTOCcmInvAuthDecryptResultGet(uint32_t ui32AuthLength,
uint32_t *pui32CipherText,
uint32_t ui32CipherTextLength,
uint32_t *pui32CcmTag)
{
uint32_t volatile ui32Tag[4];
uint32_t ui32TagIndex;
uint32_t i;
uint32_t ui32Idx;
ui32TagIndex = ui32CipherTextLength - ui32AuthLength;
// Result has already been copied to the output buffer by DMA
// Disable master control.
HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000;
// Read tag - wait for the context ready bit.
do
{
CPUdelay(1);
}
while(!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) &
CRYPTO_AESCTL_SAVED_CONTEXT_RDY));
// Read the Tag registers.
ui32Tag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0);
ui32Tag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1);
ui32Tag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2);
ui32Tag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3);
for(ui32Idx = 0; ui32Idx < ui32AuthLength ; ui32Idx++)
{
*((uint8_t*)pui32CcmTag + ui32Idx) = *((uint8_t*)ui32Tag + ui32Idx);
}
// Operation successful - clear interrupt status.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
CRYPTO_IRQCLR_RESULT_AVAIL);
// Verify the Tag.
for(i = 0; i < ui32AuthLength; i++)
{
if(*((uint8_t *)pui32CcmTag + i) !=
(*((uint8_t *)pui32CipherText + ui32TagIndex + i)))
{
return CCM_AUTHENTICATION_FAILED;
}
}
return AES_SUCCESS;
}
//*****************************************************************************
//
// Enable Crypto DMA operation
//
//*****************************************************************************
void
CRYPTODmaEnable(uint32_t ui32Channels)
{
// Check the arguments.
ASSERT((ui32Channels & CRYPTO_DMA_CHAN0) |
(ui32Channels & CRYPTO_DMA_CHAN1));
// Enable the selected channels,
if(ui32Channels & CRYPTO_DMA_CHAN0)
{
HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;
}
if(ui32Channels & CRYPTO_DMA_CHAN1)
{
HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1;
}
}
//*****************************************************************************
//
// Disable Crypto DMA operation
//
//*****************************************************************************
void
CRYPTODmaDisable(uint32_t ui32Channels)
{
// Check the arguments.
ASSERT((ui32Channels & CRYPTO_DMA_CHAN0) |
(ui32Channels & CRYPTO_DMA_CHAN1));
// Enable the selected channels.
if(ui32Channels & CRYPTO_DMA_CHAN0)
{
HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 0;
}
if(ui32Channels & CRYPTO_DMA_CHAN1)
{
HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 0;
}
}

856
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/crypto.h
View file

@ -1,856 +0,0 @@
/******************************************************************************
* Filename: crypto.h
* Revised: 2018-01-12 18:46:31 +0100 (Fri, 12 Jan 2018)
* Revision: 51161
*
* Description: AES header file.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup peripheral_group
//! @{
//! \addtogroup crypto_api
//! @{
//
//*****************************************************************************
#ifndef __CRYPTO_H__
#define __CRYPTO_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdbool.h>
#include <stdint.h>
#include "../inc/hw_types.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_ints.h"
#include "../inc/hw_crypto.h"
#include "debug.h"
#include "interrupt.h"
#include "cpu.h"
//*****************************************************************************
//
// Support for DriverLib in ROM:
// This section renames all functions that are not "static inline", so that
// calling these functions will default to implementation in flash. At the end
// of this file a second renaming will change the defaults to implementation in
// ROM for available functions.
//
// To force use of the implementation in flash, e.g. for debugging:
// - Globally: Define DRIVERLIB_NOROM at project level
// - Per function: Use prefix "NOROM_" when calling the function
//
//*****************************************************************************
#if !defined(DOXYGEN)
#define CRYPTOAesLoadKey NOROM_CRYPTOAesLoadKey
#define CRYPTOAesCbc NOROM_CRYPTOAesCbc
#define CRYPTOAesCbcStatus NOROM_CRYPTOAesCbcStatus
#define CRYPTOAesEcb NOROM_CRYPTOAesEcb
#define CRYPTOAesEcbStatus NOROM_CRYPTOAesEcbStatus
#define CRYPTOCcmAuthEncrypt NOROM_CRYPTOCcmAuthEncrypt
#define CRYPTOCcmAuthEncryptStatus NOROM_CRYPTOCcmAuthEncryptStatus
#define CRYPTOCcmAuthEncryptResultGet NOROM_CRYPTOCcmAuthEncryptResultGet
#define CRYPTOCcmInvAuthDecrypt NOROM_CRYPTOCcmInvAuthDecrypt
#define CRYPTOCcmInvAuthDecryptStatus NOROM_CRYPTOCcmInvAuthDecryptStatus
#define CRYPTOCcmInvAuthDecryptResultGet NOROM_CRYPTOCcmInvAuthDecryptResultGet
#define CRYPTODmaEnable NOROM_CRYPTODmaEnable
#define CRYPTODmaDisable NOROM_CRYPTODmaDisable
#endif
//*****************************************************************************
//
// Length of AES Electronic Code Book (ECB) block in bytes
//
//*****************************************************************************
#define AES_ECB_LENGTH 16
//*****************************************************************************
//
// Values that can be passed to CryptoIntEnable, CryptoIntDisable, and CryptoIntClear
// as the ui32IntFlags parameter, and returned from CryptoIntStatus.
//
//*****************************************************************************
#define CRYPTO_DMA_IN_DONE 0x00000002 // DMA done interrupt mask
#define CRYPTO_RESULT_RDY 0x00000001 // Result ready interrupt mask
#define CRYPTO_DMA_BUS_ERR 0x80000000 // DMA Bus error
#define CRYPTO_KEY_ST_WR_ERR 0x40000000 // Key Store Write failed
#define CRYPTO_KEY_ST_RD_ERR 0x20000000 // Key Store Read failed
#define CRYPTO_IRQTYPE_LEVEL 0x00000001 // Crypto Level interrupt enabled
#define CRYPTO_IRQTYPE_PULSE 0x00000000 // Crypto pulse interrupt enabled
#define CRYPTO_DMA_CHAN0 0x00000001 // Crypto DMA Channel 0
#define CRYPTO_DMA_CHAN1 0x00000002 // Crypto DMA Channel 1
#define CRYPTO_AES128_ENCRYPT 0x0000000C //
#define CRYPTO_AES128_DECRYPT 0x00000008 //
#define CRYPTO_DMA_READY 0x00000000 // DMA ready
#define CRYPTO_DMA_BSY 0x00000003 // DMA busy
#define CRYPTO_DMA_BUS_ERROR 0x00020000 // DMA encountered bus error
//*****************************************************************************
//
// General constants
//
//*****************************************************************************
// AES module return codes
#define AES_SUCCESS 0
#define AES_KEYSTORE_READ_ERROR 1
#define AES_KEYSTORE_WRITE_ERROR 2
#define AES_DMA_BUS_ERROR 3
#define CCM_AUTHENTICATION_FAILED 4
#define AES_ECB_TEST_ERROR 8
#define AES_NULL_ERROR 9
#define AES_CCM_TEST_ERROR 10
#define AES_DMA_BSY 11
// Key store module defines
#define STATE_BLENGTH 16 // Number of bytes in State
#define KEY_BLENGTH 16 // Number of bytes in Key
#define KEY_EXP_LENGTH 176 // Nb * (Nr+1) * 4
#define KEY_STORE_SIZE_128 0x00000001
#define KEY_STORE_SIZE_192 0x00000002
#define KEY_STORE_SIZE_256 0x00000003
#define KEY_STORE_SIZE_BITS 0x00000003
//*****************************************************************************
//
// For 128 bit key all 8 Key Area locations from 0 to 8 are valid
// However for 192 bit and 256 bit keys, only even Key Areas 0, 2, 4, 6
// are valid.
//
//*****************************************************************************
#define CRYPTO_KEY_AREA_0 0
#define CRYPTO_KEY_AREA_1 1
#define CRYPTO_KEY_AREA_2 2
#define CRYPTO_KEY_AREA_3 3
#define CRYPTO_KEY_AREA_4 4
#define CRYPTO_KEY_AREA_5 5
#define CRYPTO_KEY_AREA_6 6
#define CRYPTO_KEY_AREA_7 7
//*****************************************************************************
//
// Defines for the current AES operation
//
//*****************************************************************************
#define CRYPTO_AES_NONE 0
#define CRYPTO_AES_KEYL0AD 1
#define CRYPTO_AES_ECB 2
#define CRYPTO_AES_CCM 3
#define CRYPTO_AES_RNG 4
#define CRYPTO_AES_CBC 5
//*****************************************************************************
//
// Defines for the AES-CTR mode counter width
//
//*****************************************************************************
#define CRYPTO_AES_CTR_32 0x0
#define CRYPTO_AES_CTR_64 0x1
#define CRYPTO_AES_CTR_96 0x2
#define CRYPTO_AES_CTR_128 0x3
//*****************************************************************************
//
// API Functions and prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Write the key into the Key Ram.
//!
//! The \c ui32KeyLocation parameter is an enumerated type which specifies
//! the Key Ram location in which the key is stored.
//!
//! The pointer \c pui8AesKey has the address where the Key is stored.
//!
//! \param pui32AesKey is a pointer to an AES Key.
//! \param ui32KeyLocation is the location of the key in Key RAM.
//! This parameter can have any of the following values:
//! - \ref CRYPTO_KEY_AREA_0
//! - \ref CRYPTO_KEY_AREA_1
//! - \ref CRYPTO_KEY_AREA_2
//! - \ref CRYPTO_KEY_AREA_3
//! - \ref CRYPTO_KEY_AREA_4
//! - \ref CRYPTO_KEY_AREA_5
//! - \ref CRYPTO_KEY_AREA_6
//! - \ref CRYPTO_KEY_AREA_7
//!
//! \return Returns status of the function:
//! - \ref AES_SUCCESS
//! - \ref AES_KEYSTORE_READ_ERROR
//
//*****************************************************************************
extern uint32_t CRYPTOAesLoadKey(uint32_t *pui32AesKey,
uint32_t ui32KeyLocation);
//*****************************************************************************
//
//! \brief Start an AES-CBC operation (encryption or decryption).
//!
//! The function starts an AES CBC mode encrypt or decrypt operation.
//! End operation can be detected by enabling interrupt or by polling
//! CRYPTOAesCbcStatus(). Result of operation is returned by CRYPTOAesCbcStatus().
//!
//! \param pui32MsgIn is a pointer to the input data.
//! \param pui32MsgOut is a pointer to the output data.
//! \param ui32MsgLength is the length in bytes of the input data.
//! \param pui32Nonce is a pointer to 16-byte Nonce.
//! \param ui32KeyLocation is the location of the key in Key RAM.
//! This parameter can have any of the following values:
//! - \ref CRYPTO_KEY_AREA_0
//! - \ref CRYPTO_KEY_AREA_1
//! - \ref CRYPTO_KEY_AREA_2
//! - \ref CRYPTO_KEY_AREA_3
//! - \ref CRYPTO_KEY_AREA_4
//! - \ref CRYPTO_KEY_AREA_5
//! - \ref CRYPTO_KEY_AREA_6
//! - \ref CRYPTO_KEY_AREA_7
//! \param bEncrypt is set \c true to encrypt or set \c false to decrypt.
//! \param bIntEnable is set \c true to enable Crypto interrupts or \c false to
//! disable Crypto interrupt.
//!
//! \return Returns status of the AES-CBC operation:
//! - \ref AES_SUCCESS
//! - \ref AES_KEYSTORE_READ_ERROR
//!
//! \sa \ref CRYPTOAesCbcStatus()
//
//*****************************************************************************
extern uint32_t CRYPTOAesCbc(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut,
uint32_t ui32MsgLength, uint32_t *pui32Nonce,
uint32_t ui32KeyLocation, bool bEncrypt,
bool bIntEnable);
//*****************************************************************************
//
//! \brief Check the result of an AES CBC operation.
//!
//! This function should be called after \ref CRYPTOAesCbc() function to
//! check if the AES CBC operation was successful.
//!
//! \return Returns the status of the AES CBC operation:
//! - \ref AES_SUCCESS : Successful.
//! - \ref AES_DMA_BUS_ERROR : Failed.
//! - \ref AES_DMA_BSY : Operation is ongoing.
//!
//! \sa \ref CRYPTOAesCbc()
//
//*****************************************************************************
extern uint32_t CRYPTOAesCbcStatus(void);
//*****************************************************************************
//
//! \brief Start an AES-ECB operation (encryption or decryption).
//!
//! The \c ui32KeyLocation parameter is an enumerated type which specifies
//! the Key Ram location in which the key is stored.
//!
//! \param pui32MsgIn is a pointer to the input data.
//! \param pui32MsgOut is a pointer to the output data.
//! \param ui32KeyLocation is the location of the key in Key RAM.
//! This parameter can have any of the following values:
//! - \ref CRYPTO_KEY_AREA_0
//! - \ref CRYPTO_KEY_AREA_1
//! - \ref CRYPTO_KEY_AREA_2
//! - \ref CRYPTO_KEY_AREA_3
//! - \ref CRYPTO_KEY_AREA_4
//! - \ref CRYPTO_KEY_AREA_5
//! - \ref CRYPTO_KEY_AREA_6
//! - \ref CRYPTO_KEY_AREA_7
//! \param bEncrypt is set \c true to encrypt or set \c false to decrypt.
//! \param bIntEnable is set \c true to enable Crypto interrupts or \c false to
//! disable Crypto interrupt.
//!
//! \return Returns status of the AES-ECB operation:
//! - \ref AES_SUCCESS
//! - \ref AES_KEYSTORE_READ_ERROR
//!
//! \sa \ref CRYPTOAesEcbStatus()
//
//*****************************************************************************
extern uint32_t CRYPTOAesEcb(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut,
uint32_t ui32KeyLocation, bool bEncrypt,
bool bIntEnable);
//*****************************************************************************
//
//! \brief Check the result of an AES ECB operation.
//!
//! This function should be called after \ref CRYPTOAesEcb() function to
//! check if the AES ECB operation was successful.
//!
//! \return Returns the status of the AES ECB operation:
//! - \ref AES_SUCCESS : Successful.
//! - \ref AES_DMA_BUS_ERROR : Failed.
//! - \ref AES_DMA_BSY : Operation is ongoing.
//!
//! \sa \ref CRYPTOAesEcb()
//
//*****************************************************************************
extern uint32_t CRYPTOAesEcbStatus(void);
//*****************************************************************************
//
//! \brief Finish the encryption operation by resetting the operation mode.
//!
//! This function should be called after \ref CRYPTOAesEcbStatus() has reported
//! that the operation is finished successfully.
//!
//! \return None
//!
//! \sa \ref CRYPTOAesEcbStatus()
//
//*****************************************************************************
__STATIC_INLINE void
CRYPTOAesEcbFinish(void)
{
// Result has already been copied to the output buffer by DMA.
// Disable master control/DMA clock and clear the operating mode.
HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000;
HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = 0x00000000;
}
//*****************************************************************************
//
//! \brief Finish the encryption operation by resetting the operation mode.
//!
//! This function should be called after \ref CRYPTOAesCbcStatus() has reported
//! that the operation is finished successfully.
//!
//! \return None
//!
//! \sa \ref CRYPTOAesCbcStatus()
//
//*****************************************************************************
__STATIC_INLINE void
CRYPTOAesCbcFinish(void)
{
// Result has already been copied to the output buffer by DMA.
// Disable master control/DMA clock and clear the operating mode.
HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000;
HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = 0x00000000;
}
//*****************************************************************************
//
//! \brief Start CCM operation.
//!
//! The \c ui32KeyLocation is an enumerated type which specifies the Key Ram
//! location in which the key is stored.
//!
//! \param bEncrypt determines whether to run encryption or not.
//! \param ui32AuthLength is the length of the authentication field -
//! 0, 2, 4, 6, 8, 10, 12, 14 or 16 octets.
//! \param pui32Nonce is a pointer to 13-byte or 12-byte Nonce (Number used once).
//! \param pui32PlainText is a pointer to the octet string input message.
//! \param ui32PlainTextLength is the length of the message.
//! \param pui32Header is the length of the header (Additional Authentication
//! Data or AAD).
//! \param ui32HeaderLength is the length of the header in octets.
//! \param ui32KeyLocation is the location in Key RAM where the key is stored.
//! This parameter can have any of the following values:
//! - \ref CRYPTO_KEY_AREA_0
//! - \ref CRYPTO_KEY_AREA_1
//! - \ref CRYPTO_KEY_AREA_2
//! - \ref CRYPTO_KEY_AREA_3
//! - \ref CRYPTO_KEY_AREA_4
//! - \ref CRYPTO_KEY_AREA_5
//! - \ref CRYPTO_KEY_AREA_6
//! - \ref CRYPTO_KEY_AREA_7
//! \param ui32FieldLength is the size of the length field (2 or 3).
//! \param bIntEnable enables interrupts.
//!
//! \return Returns the status of the CCM operation
//! - \ref AES_SUCCESS
//! - \ref AES_KEYSTORE_READ_ERROR
//! - \ref AES_DMA_BUS_ERROR
//!
//! \sa \ref CRYPTOCcmAuthEncryptStatus()
//
//*****************************************************************************
extern uint32_t CRYPTOCcmAuthEncrypt(bool bEncrypt, uint32_t ui32AuthLength,
uint32_t *pui32Nonce,
uint32_t *pui32PlainText,
uint32_t ui32PlainTextLength,
uint32_t *pui32Header,
uint32_t ui32HeaderLength,
uint32_t ui32KeyLocation,
uint32_t ui32FieldLength,
bool bIntEnable);
//*****************************************************************************
//
//! \brief Check the result of an AES CCM operation.
//!
//! This function should be called after \ref CRYPTOCcmAuthEncrypt() function to check
//! if the AES CCM operation was successful.
//!
//! \return Returns the status of the AES CCM operation:
//! - \ref AES_SUCCESS : Successful.
//! - \ref AES_DMA_BUS_ERROR : Failed.
//! - \ref AES_DMA_BSY : Operation is ongoing.
//!
//! \sa \ref CRYPTOCcmAuthEncrypt()
//
//*****************************************************************************
extern uint32_t CRYPTOCcmAuthEncryptStatus(void);
//*****************************************************************************
//
//! \brief Get the result of an AES CCM operation.
//!
//! This function should be called after \ref CRYPTOCcmAuthEncryptStatus().
//!
//! \param ui32TagLength is length of the Tag.
//! \param pui32CcmTag is the location of the authentication Tag.
//!
//! \return Returns \ref AES_SUCCESS if successful.
//!
//! \sa \ref CRYPTOCcmAuthEncryptStatus()
//
//*****************************************************************************
extern uint32_t CRYPTOCcmAuthEncryptResultGet(uint32_t ui32TagLength,
uint32_t *pui32CcmTag);
//*****************************************************************************
//
//! \brief Start a CCM Decryption and Inverse Authentication operation.
//!
//! The \c ui32KeyLocation is an enumerated type which specifies the Key Ram
//! location in which the key is stored.
//!
//! \param bDecrypt determines whether to run decryption or not.
//! \param ui32AuthLength is the length of the authentication field -
//! 0, 2, 4, 6, 8, 10, 12, 14 or 16 octets.
//! \param pui32Nonce is a pointer to 13-byte or 12-byte Nonce (Number used once).
//! \param pui32CipherText is a pointer to the octet string encrypted message.
//! \param ui32CipherTextLength is the length of the encrypted message.
//! \param pui32Header is the length of the header (Additional Authentication
//! Data or AAD).
//! \param ui32HeaderLength is the length of the header in octets.
//! \param ui32KeyLocation is the location in Key RAM where the key is stored.
//! This parameter can have any of the following values:
//! - \ref CRYPTO_KEY_AREA_0
//! - \ref CRYPTO_KEY_AREA_1
//! - \ref CRYPTO_KEY_AREA_2
//! - \ref CRYPTO_KEY_AREA_3
//! - \ref CRYPTO_KEY_AREA_4
//! - \ref CRYPTO_KEY_AREA_5
//! - \ref CRYPTO_KEY_AREA_6
//! - \ref CRYPTO_KEY_AREA_7
//! \param ui32FieldLength is the size of the length field (2 or 3).
//! \param bIntEnable enables interrupts.
//!
//! \return Returns the status of the operation:
//! - \ref AES_SUCCESS
//! - \ref AES_KEYSTORE_READ_ERROR
//! - \ref AES_DMA_BUS_ERROR
//
//*****************************************************************************
extern uint32_t CRYPTOCcmInvAuthDecrypt(bool bDecrypt, uint32_t ui32AuthLength,
uint32_t *pui32Nonce,
uint32_t *pui32CipherText,
uint32_t ui32CipherTextLength,
uint32_t *pui32Header,
uint32_t ui32HeaderLength,
uint32_t ui32KeyLocation,
uint32_t ui32FieldLength,
bool bIntEnable);
//*****************************************************************************
//
//! \brief Checks CCM decrypt and Inverse Authentication result.
//!
//! \return Returns status of operation:
//! - \ref AES_SUCCESS : Operation was successful.
//! - \ref AES_DMA_BSY : Operation is busy.
//! - \ref AES_DMA_BUS_ERROR : An error is encountered.
//
//*****************************************************************************
extern uint32_t CRYPTOCcmInvAuthDecryptStatus(void);
//*****************************************************************************
//
//! \brief Get the result of the CCM operation.
//!
//! \param ui32AuthLength is the length of the authentication field -
//! 0, 2, 4, 6, 8, 10, 12, 14 or 16 octets.
//! \param pui32CipherText is a pointer to the octet string encrypted message.
//! \param ui32CipherTextLength is the length of the encrypted message.
//! \param pui32CcmTag is the location of the authentication Tag.
//!
//! \return Returns AES_SUCCESS if successful.
//
//*****************************************************************************
extern uint32_t CRYPTOCcmInvAuthDecryptResultGet(uint32_t ui32AuthLength,
uint32_t *pui32CipherText,
uint32_t ui32CipherTextLength,
uint32_t *pui32CcmTag);
//*****************************************************************************
//
//! \brief Get the current status of the Crypto DMA controller.
//!
//! This function is used to poll the Crypto DMA controller to check if it is
//! ready for a new operation or if an error has occurred.
//!
//! The \ref CRYPTO_DMA_BUS_ERROR can also be caught using the crypto event
//! handler.
//!
//! \return Returns the current status of the DMA controller:
//! - \ref CRYPTO_DMA_READY : DMA ready for a new operation
//! - \ref CRYPTO_DMA_BSY : DMA is busy
//! - \ref CRYPTO_DMA_BUS_ERROR : DMA Bus error
//
//*****************************************************************************
__STATIC_INLINE uint32_t
CRYPTODmaStatus(void)
{
// Return the value of the status register.
return (HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT));
}
//*****************************************************************************
//
//! \brief Enable Crypto DMA operation.
//!
//! The specified Crypto DMA channels are enabled.
//!
//! \param ui32Channels is a bitwise OR of the channels to enable.
//! - \ref CRYPTO_DMA_CHAN0
//! - \ref CRYPTO_DMA_CHAN1
//!
//! \return None
//
//*****************************************************************************
extern void CRYPTODmaEnable(uint32_t ui32Channels);
//*****************************************************************************
//
//! \brief Disable Crypto DMA operation.
//!
//! The specified Crypto DMA channels are disabled.
//!
//! \param ui32Channels is a bitwise OR of the channels to disable.
//! - \ref CRYPTO_DMA_CHAN0
//! - \ref CRYPTO_DMA_CHAN1
//!
//! \return None
//
//*****************************************************************************
extern void CRYPTODmaDisable(uint32_t ui32Channels);
//*****************************************************************************
//
//! \brief Enables individual Crypto interrupt sources.
//!
//! This function enables the indicated Crypto interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt.
//! Disabled sources have no effect on the processor.
//!
//! \param ui32IntFlags is the bitwise OR of the interrupt sources to be enabled.
//! - \ref CRYPTO_DMA_IN_DONE
//! - \ref CRYPTO_RESULT_RDY
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
CRYPTOIntEnable(uint32_t ui32IntFlags)
{
// Check the arguments.
ASSERT((ui32IntFlags & CRYPTO_DMA_IN_DONE) |
(ui32IntFlags & CRYPTO_RESULT_RDY));
// Using level interrupt.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL;
// Enable the specified interrupts.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= ui32IntFlags;
}
//*****************************************************************************
//
//! \brief Disables individual CRYPTO interrupt sources.
//!
//! This function disables the indicated Crypto interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt.
//! Disabled sources have no effect on the processor.
//!
//! \param ui32IntFlags is the bitwise OR of the interrupt sources to be enabled.
//! - \ref CRYPTO_DMA_IN_DONE
//! - \ref CRYPTO_RESULT_RDY
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
CRYPTOIntDisable(uint32_t ui32IntFlags)
{
// Check the arguments.
ASSERT((ui32IntFlags & CRYPTO_DMA_IN_DONE) |
(ui32IntFlags & CRYPTO_RESULT_RDY));
// Disable the specified interrupts.
HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~ui32IntFlags;
}
//*****************************************************************************
//
//! \brief Gets the current interrupt status.
//!
//! This function returns the interrupt status for the specified Crypto. Either
//! the raw interrupt status or the status of interrupts that are allowed to
//! reflect to the processor can be returned.
//!
//! \param bMasked whether to use raw or masked interrupt status:
//! - \c false : Raw interrupt status is required.
//! - \c true : Masked interrupt status is required.
//!
//! \return Returns the current interrupt status:
//! - \ref CRYPTO_DMA_IN_DONE
//! - \ref CRYPTO_RESULT_RDY
//
//*****************************************************************************
__STATIC_INLINE uint32_t
CRYPTOIntStatus(bool bMasked)
{
uint32_t ui32Mask;
// Return either the interrupt status or the raw interrupt status as
// requested.
if(bMasked)
{
ui32Mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN);
return(ui32Mask & HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT));
}
else
{
return(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & 0x00000003);
}
}
//*****************************************************************************
//
//! \brief Clears Crypto interrupt sources.
//!
//! The specified Crypto interrupt sources are cleared, so that they no longer
//! assert. This function must be called in the interrupt handler to keep the
//! interrupt from being recognized again immediately upon exit.
//!
//! \note Due to write buffers and synchronizers in the system it may take several
//! clock cycles from a register write clearing an event in a module and until the
//! event is actually cleared in the NVIC of the system CPU. It is recommended to
//! clear the event source early in the interrupt service routine (ISR) to allow
//! the event clear to propagate to the NVIC before returning from the ISR.
//! At the same time, an early event clear allows new events of the same type to be
//! pended instead of ignored if the event is cleared later in the ISR.
//! It is the responsibility of the programmer to make sure that enough time has passed
//! before returning from the ISR to avoid false re-triggering of the cleared event.
//! A simple, although not necessarily optimal, way of clearing an event before
//! returning from the ISR is:
//! -# Write to clear event (interrupt source). (buffered write)
//! -# Dummy read from the event source module. (making sure the write has propagated)
//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers)
//!
//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
//! - \ref CRYPTO_DMA_IN_DONE
//! - \ref CRYPTO_RESULT_RDY
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
CRYPTOIntClear(uint32_t ui32IntFlags)
{
// Check the arguments.
ASSERT((ui32IntFlags & CRYPTO_DMA_IN_DONE) |
(ui32IntFlags & CRYPTO_RESULT_RDY));
// Clear the requested interrupt sources,
HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = ui32IntFlags;
}
//*****************************************************************************
//
//! \brief Registers an interrupt handler for a Crypto interrupt in the dynamic interrupt table.
//!
//! \note Only use this function if you want to use the dynamic vector table (in SRAM)!
//!
//! This function registers a function as the interrupt handler for a specific
//! interrupt and enables the corresponding interrupt in the interrupt controller.
//!
//! Specific UART interrupts must be enabled via \ref CRYPTOIntEnable(). It is the
//! interrupt handler's responsibility to clear the interrupt source.
//!
//! \param pfnHandler is a pointer to the function to be called when the
//! UART interrupt occurs.
//!
//! \return None
//!
//! \sa \ref IntRegister() for important information about registering interrupt
//! handlers.
//
//*****************************************************************************
__STATIC_INLINE void
CRYPTOIntRegister(void (*pfnHandler)(void))
{
// Register the interrupt handler.
IntRegister(INT_CRYPTO_RESULT_AVAIL_IRQ, pfnHandler);
// Enable the UART interrupt.
IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ);
}
//*****************************************************************************
//
//! \brief Unregisters an interrupt handler for a Crypto interrupt in the dynamic interrupt table.
//!
//! This function does the actual unregistering of the interrupt handler. It
//! clears the handler to be called when a Crypto interrupt occurs. This
//! function also masks off the interrupt in the interrupt controller so that
//! the interrupt handler no longer is called.
//!
//! \return None
//!
//! \sa \ref IntRegister() for important information about registering interrupt
//! handlers.
//
//*****************************************************************************
__STATIC_INLINE void
CRYPTOIntUnregister(void)
{
// Disable the interrupt.
IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);
// Unregister the interrupt handler.
IntUnregister(INT_CRYPTO_RESULT_AVAIL_IRQ);
}
//*****************************************************************************
//
// Support for DriverLib in ROM:
// Redirect to implementation in ROM when available.
//
//*****************************************************************************
#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
#include "../driverlib/rom.h"
#ifdef ROM_CRYPTOAesLoadKey
#undef CRYPTOAesLoadKey
#define CRYPTOAesLoadKey ROM_CRYPTOAesLoadKey
#endif
#ifdef ROM_CRYPTOAesCbc
#undef CRYPTOAesCbc
#define CRYPTOAesCbc ROM_CRYPTOAesCbc
#endif
#ifdef ROM_CRYPTOAesCbcStatus
#undef CRYPTOAesCbcStatus
#define CRYPTOAesCbcStatus ROM_CRYPTOAesCbcStatus
#endif
#ifdef ROM_CRYPTOAesEcb
#undef CRYPTOAesEcb
#define CRYPTOAesEcb ROM_CRYPTOAesEcb
#endif
#ifdef ROM_CRYPTOAesEcbStatus
#undef CRYPTOAesEcbStatus
#define CRYPTOAesEcbStatus ROM_CRYPTOAesEcbStatus
#endif
#ifdef ROM_CRYPTOCcmAuthEncrypt
#undef CRYPTOCcmAuthEncrypt
#define CRYPTOCcmAuthEncrypt ROM_CRYPTOCcmAuthEncrypt
#endif
#ifdef ROM_CRYPTOCcmAuthEncryptStatus
#undef CRYPTOCcmAuthEncryptStatus
#define CRYPTOCcmAuthEncryptStatus ROM_CRYPTOCcmAuthEncryptStatus
#endif
#ifdef ROM_CRYPTOCcmAuthEncryptResultGet
#undef CRYPTOCcmAuthEncryptResultGet
#define CRYPTOCcmAuthEncryptResultGet ROM_CRYPTOCcmAuthEncryptResultGet
#endif
#ifdef ROM_CRYPTOCcmInvAuthDecrypt
#undef CRYPTOCcmInvAuthDecrypt
#define CRYPTOCcmInvAuthDecrypt ROM_CRYPTOCcmInvAuthDecrypt
#endif
#ifdef ROM_CRYPTOCcmInvAuthDecryptStatus
#undef CRYPTOCcmInvAuthDecryptStatus
#define CRYPTOCcmInvAuthDecryptStatus ROM_CRYPTOCcmInvAuthDecryptStatus
#endif
#ifdef ROM_CRYPTOCcmInvAuthDecryptResultGet
#undef CRYPTOCcmInvAuthDecryptResultGet
#define CRYPTOCcmInvAuthDecryptResultGet ROM_CRYPTOCcmInvAuthDecryptResultGet
#endif
#ifdef ROM_CRYPTODmaEnable
#undef CRYPTODmaEnable
#define CRYPTODmaEnable ROM_CRYPTODmaEnable
#endif
#ifdef ROM_CRYPTODmaDisable
#undef CRYPTODmaDisable
#define CRYPTODmaDisable ROM_CRYPTODmaDisable
#endif
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __CRYPTO_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

214
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ddi.c
View file

@ -1,214 +0,0 @@
/******************************************************************************
* Filename: ddi.c
* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018)
* Revision: 52111
*
* Description: Driver for the DDI master interface
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "ddi.h"
//*****************************************************************************
//
// Handle support for DriverLib in ROM:
// This section will undo prototype renaming made in the header file
//
//*****************************************************************************
#if !defined(DOXYGEN)
#undef DDI32RegWrite
#define DDI32RegWrite NOROM_DDI32RegWrite
#undef DDI16BitWrite
#define DDI16BitWrite NOROM_DDI16BitWrite
#undef DDI16BitfieldWrite
#define DDI16BitfieldWrite NOROM_DDI16BitfieldWrite
#undef DDI16BitRead
#define DDI16BitRead NOROM_DDI16BitRead
#undef DDI16BitfieldRead
#define DDI16BitfieldRead NOROM_DDI16BitfieldRead
#endif
//*****************************************************************************
//
// Write a 32 bit value to a register in the DDI slave.
//
//*****************************************************************************
void
DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg,
uint32_t ui32Val)
{
// Check the arguments.
ASSERT(DDIBaseValid(ui32Base));
ASSERT(ui32Reg < DDI_SLAVE_REGS);
// Write the value to the register.
HWREG(ui32Base + ui32Reg) = ui32Val;
}
//*****************************************************************************
//
// Write a single bit using a 16-bit maskable write
//
//*****************************************************************************
void
DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg,
uint32_t ui32Mask, uint32_t ui32WrData)
{
uint32_t ui32RegAddr;
uint32_t ui32Data;
// Check the arguments.
ASSERT(DDIBaseValid(ui32Base));
ASSERT(!((ui32Mask & 0xFFFF0000) ^ (ui32Mask & 0x0000FFFF)));
ASSERT(!(ui32WrData & 0xFFFF0000));
// DDI 16-bit target is on 32-bit boundary so double offset
ui32RegAddr = ui32Base + (ui32Reg << 1) + DDI_O_MASK16B;
// Adjust for target bit in high half of the word.
if(ui32Mask & 0xFFFF0000)
{
ui32RegAddr += 4;
ui32Mask >>= 16;
}
// Write mask if data is not zero (to set mask bit), else write '0'.
ui32Data = ui32WrData ? ui32Mask : 0x0;
// Update the register.
HWREG(ui32RegAddr) = (ui32Mask << 16) | ui32Data;
}
//*****************************************************************************
//
// Write a bit field via the DDI using 16-bit maskable write
//
//*****************************************************************************
void
DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg,
uint32_t ui32Mask, uint32_t ui32Shift,
uint16_t ui32Data)
{
uint32_t ui32RegAddr;
uint32_t ui32WrData;
// Check the arguments.
ASSERT(DDIBaseValid(ui32Base));
// 16-bit target is on 32-bit boundary so double offset.
ui32RegAddr = ui32Base + (ui32Reg << 1) + DDI_O_MASK16B;
// Adjust for target bit in high half of the word.
if(ui32Shift >= 16)
{
ui32Shift = ui32Shift - 16;
ui32RegAddr += 4;
ui32Mask = ui32Mask >> 16;
}
// Shift data in to position.
ui32WrData = ui32Data << ui32Shift;
// Write data.
HWREG(ui32RegAddr) = (ui32Mask << 16) | ui32WrData;
}
//*****************************************************************************
//
// Read a bit via the DDI using 16-bit READ.
//
//*****************************************************************************
uint16_t
DDI16BitRead(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask)
{
uint32_t ui32RegAddr;
uint16_t ui16Data;
// Check the arguments.
ASSERT(DDIBaseValid(ui32Base));
// Calculate the address of the register.
ui32RegAddr = ui32Base + ui32Reg + DDI_O_DIR;
// Adjust for target bit in high half of the word.
if(ui32Mask & 0xFFFF0000)
{
ui32RegAddr += 2;
ui32Mask = ui32Mask >> 16;
}
// Read a halfword on the DDI interface.
ui16Data = HWREGH(ui32RegAddr);
// Mask data.
ui16Data = ui16Data & ui32Mask;
// Return masked data.
return(ui16Data);
}
//*****************************************************************************
//
// Read a bit field via the DDI using 16-bit read.
//
//*****************************************************************************
uint16_t
DDI16BitfieldRead(uint32_t ui32Base, uint32_t ui32Reg,
uint32_t ui32Mask, uint32_t ui32Shift)
{
uint32_t ui32RegAddr;
uint16_t ui16Data;
// Check the arguments.
ASSERT(DDIBaseValid(ui32Base));
// Calculate the register address.
ui32RegAddr = ui32Base + ui32Reg + DDI_O_DIR;
// Adjust for target bit in high half of the word.
if(ui32Shift >= 16)
{
ui32Shift = ui32Shift - 16;
ui32RegAddr += 2;
ui32Mask = ui32Mask >> 16;
}
// Read the register.
ui16Data = HWREGH(ui32RegAddr);
// Mask data and shift into place.
ui16Data &= ui32Mask;
ui16Data >>= ui32Shift;
// Return data.
return(ui16Data);
}

462
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@ -1,462 +0,0 @@
/******************************************************************************
* Filename: ddi.h
* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018)
* Revision: 52111
*
* Description: Defines and prototypes for the DDI master interface.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup analog_group
//! @{
//! \addtogroup ddi_api
//! @{
//
//*****************************************************************************
#ifndef __DDI_H__
#define __DDI_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdbool.h>
#include <stdint.h>
#include "../inc/hw_types.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_ddi.h"
#include "../inc/hw_aux_smph.h"
#include "debug.h"
#include "cpu.h"
//*****************************************************************************
//
// Support for DriverLib in ROM:
// This section renames all functions that are not "static inline", so that
// calling these functions will default to implementation in flash. At the end
// of this file a second renaming will change the defaults to implementation in
// ROM for available functions.
//
// To force use of the implementation in flash, e.g. for debugging:
// - Globally: Define DRIVERLIB_NOROM at project level
// - Per function: Use prefix "NOROM_" when calling the function
//
//*****************************************************************************
#if !defined(DOXYGEN)
#define DDI32RegWrite NOROM_DDI32RegWrite
#define DDI16BitWrite NOROM_DDI16BitWrite
#define DDI16BitfieldWrite NOROM_DDI16BitfieldWrite
#define DDI16BitRead NOROM_DDI16BitRead
#define DDI16BitfieldRead NOROM_DDI16BitfieldRead
#endif
//*****************************************************************************
//
// Number of register in the DDI slave
//
//*****************************************************************************
#define DDI_SLAVE_REGS 64
//*****************************************************************************
//
// Defines that is used to control the ADI slave and master
//
//*****************************************************************************
#define DDI_PROTECT 0x00000080
#define DDI_ACK 0x00000001
#define DDI_SYNC 0x00000000
//*****************************************************************************
//
// API Functions and prototypes
//
//*****************************************************************************
//*****************************************************************************
//
// Helper functions
//
//*****************************************************************************
#ifdef DRIVERLIB_DEBUG
//*****************************************************************************
//
//! \internal
//!
//! \brief Check a DDI base address.
//!
//! This function determines if a DDI port base address is valid.
//!
//! \param ui32Base is the base address of the DDI port.
//!
//! \return Returns \c true if the base address is valid and \c false
//! otherwise.
//!
//! \endinternal
//
//*****************************************************************************
static bool
DDIBaseValid(uint32_t ui32Base)
{
return(ui32Base == AUX_DDI0_OSC_BASE);
}
#endif
//*****************************************************************************
//
//! \brief Read the value in a 32 bit register.
//!
//! This function will read a register in the analog domain and return
//! the value as an \c uint32_t.
//!
//! \param ui32Base is DDI base address.
//! \param ui32Reg is the 32 bit register to read.
//!
//! \return Returns the 32 bit value of the analog register.
//
//*****************************************************************************
__STATIC_INLINE uint32_t
DDI32RegRead(uint32_t ui32Base, uint32_t ui32Reg)
{
// Check the arguments.
ASSERT(DDIBaseValid(ui32Base));
ASSERT(ui32Reg < DDI_SLAVE_REGS);
// Read the register and return the value.
return(HWREG(ui32Base + ui32Reg));
}
//*****************************************************************************
//
//! \brief Set specific bits in a DDI slave register.
//!
//! This function will set bits in a register in the analog domain.
//!
//! \note This operation is write only for the specified register.
//! This function is used to set bits in specific register in the
//! DDI slave. Only bits in the selected register are affected by the
//! operation.
//!
//! \param ui32Base is DDI base address.
//! \param ui32Reg is the base register to assert the bits in.
//! \param ui32Val is the 32 bit one-hot encoded value specifying which
//! bits to set in the register.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
DDI32BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val)
{
uint32_t ui32RegOffset;
// Check the arguments.
ASSERT(DDIBaseValid(ui32Base));
ASSERT(ui32Reg < DDI_SLAVE_REGS);
// Get the correct address of the first register used for setting bits
// in the DDI slave.
ui32RegOffset = DDI_O_SET;
// Set the selected bits.
HWREG(ui32Base + ui32RegOffset + ui32Reg) = ui32Val;
}
//*****************************************************************************
//
//! \brief Clear specific bits in a 32 bit DDI register.
//!
//! This function will clear bits in a register in the analog domain.
//!
//! \param ui32Base is DDI base address.
//! \param ui32Reg is the base registers to clear the bits in.
//! \param ui32Val is the 32 bit one-hot encoded value specifying which
//! bits to clear in the register.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
DDI32BitsClear(uint32_t ui32Base, uint32_t ui32Reg,
uint32_t ui32Val)
{
uint32_t ui32RegOffset;
// Check the arguments.
ASSERT(DDIBaseValid(ui32Base));
ASSERT(ui32Reg < DDI_SLAVE_REGS);
// Get the correct address of the first register used for setting bits
// in the DDI slave.
ui32RegOffset = DDI_O_CLR;
// Clear the selected bits.
HWREG(ui32Base + ui32RegOffset + ui32Reg) = ui32Val;
}
//*****************************************************************************
//
//! \brief Set a value on any 8 bits inside a 32 bit register in the DDI slave.
//!
//! This function allows byte (8 bit access) to the DDI slave registers.
//!
//! Use this function to write any value in the range 0-7 bits aligned on a
//! byte boundary. For example, for writing the value 0b101 to bits 1-3 set
//! <tt>ui16Val = 0x0A</tt> and <tt>ui16Mask = 0x0E</tt>. Bits 0 and 5-7 will
//! not be affected by the operation, as long as the corresponding bits are
//! not set in the \c ui16Mask.
//!
//! \param ui32Base is the base address of the DDI port.
//! \param ui32Reg is the Least Significant Register in the DDI slave that
//! will be affected by the write operation.
//! \param ui32Byte is the byte number to access within the 32 bit register.
//! \param ui16Mask is the mask defining which of the 8 bits that should be
//! overwritten. The mask must be defined in the lower half of the 16 bits.
//! \param ui16Val is the value to write. The value must be defined in the lower
//! half of the 16 bits.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
DDI8SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Byte,
uint16_t ui16Mask, uint16_t ui16Val)
{
uint32_t ui32RegOffset;
// Check the arguments.
ASSERT(DDIBaseValid(ui32Base));
ASSERT(ui32Reg < DDI_SLAVE_REGS);
ASSERT(!(ui16Val & 0xFF00));
ASSERT(!(ui16Mask & 0xFF00));
// Get the correct address of the first register used for setting bits
// in the DDI slave.
ui32RegOffset = DDI_O_MASK8B + (ui32Reg << 1) + (ui32Byte << 1);
// Set the selected bits.
HWREGH(ui32Base + ui32RegOffset) = (ui16Mask << 8) | ui16Val;
}
//*****************************************************************************
//
//! \brief Set a value on any 16 bits inside a 32 bit register aligned on a
//! half-word boundary in the DDI slave.
//!
//! This function allows 16 bit masked access to the DDI slave registers.
//!
//! Use this function to write any value in the range 0-15 bits aligned on a
//! half-word boundary. For example, for writing the value 0b101 to bits 1-3 set
//! <tt>ui32Val = 0x000A</tt> and <tt>ui32Mask = 0x000E</tt>. Bits 0 and 5-15 will not be
//! affected by the operation, as long as the corresponding bits are not set
//! in the \c ui32Mask.
//!
//! \param ui32Base is the base address of the DDI port.
//! \param ui32Reg is register to access.
//! \param bWriteHigh defines which part of the register to write in.
//! \param ui32Mask is the mask defining which of the 16 bit that should be
//! overwritten. The mask must be defined in the lower half of the 32 bits.
//! \param ui32Val is the value to write. The value must be defined in the lower
//! half of the 32 bits.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
DDI16SetValBit(uint32_t ui32Base, uint32_t ui32Reg, bool bWriteHigh,
uint32_t ui32Mask, uint32_t ui32Val)
{
uint32_t ui32RegOffset;
// Check the arguments.
ASSERT(DDIBaseValid(ui32Base));
ASSERT(ui32Reg < DDI_SLAVE_REGS);
ASSERT(!(ui32Val & 0xFFFF0000));
ASSERT(!(ui32Mask & 0xFFFF0000));
// Get the correct address of the first register used for setting bits
// in the DDI slave.
ui32RegOffset = DDI_O_MASK16B + (ui32Reg << 1) + (bWriteHigh ? 4 : 0);
// Set the selected bits.
HWREG(ui32Base + ui32RegOffset) = (ui32Mask << 16) | ui32Val;
}
//*****************************************************************************
//
//! \brief Write a 32 bit value to a register in the DDI slave.
//!
//! This function will write a value to a register in the analog
//! domain.
//!
//! \note This operation is write only for the specified register. No
//! conservation of the previous value of the register will be kept (i.e. this
//! is NOT read-modify-write on the register).
//!
//! \param ui32Base is DDI base address.
//! \param ui32Reg is the register to write.
//! \param ui32Val is the 32 bit value to write to the register.
//!
//! \return None
//
//*****************************************************************************
extern void DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val);
//*****************************************************************************
//
//! \brief Write a single bit using a 16-bit maskable write.
//!
//! A '1' is written to the bit if \c ui32WrData is non-zero, else a '0' is written.
//!
//! \param ui32Base is the base address of the DDI port.
//! \param ui32Reg is register to access.
//! \param ui32Mask is the mask defining which of the 16 bit that should be overwritten.
//! \param ui32WrData is the value to write. The value must be defined in the lower half of the 32 bits.
//!
//! \return None
//
//*****************************************************************************
extern void DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg,
uint32_t ui32Mask, uint32_t ui32WrData);
//*****************************************************************************
//
//! \brief Write a bit field via the DDI using 16-bit maskable write.
//!
//! Requires that entire bit field is within the half word boundary.
//!
//! \param ui32Base is the base address of the DDI port.
//! \param ui32Reg is register to access.
//! \param ui32Mask is the mask defining which of the 16 bits that should be overwritten.
//! \param ui32Shift is the shift value for the bit field.
//! \param ui32Data is the data aligned to bit 0.
//!
//! \return None
//
//*****************************************************************************
extern void DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg,
uint32_t ui32Mask, uint32_t ui32Shift,
uint16_t ui32Data);
//*****************************************************************************
//
//! \brief Read a bit via the DDI using 16-bit read.
//!
//! \param ui32Base is the base address of the DDI module.
//! \param ui32Reg is the register to read.
//! \param ui32Mask defines the bit which should be read.
//!
//! \return Returns a zero if bit selected by mask is '0'. Else returns the mask.
//
//*****************************************************************************
extern uint16_t DDI16BitRead(uint32_t ui32Base, uint32_t ui32Reg,
uint32_t ui32Mask);
//*****************************************************************************
//
//! \brief Read a bit field via the DDI using 16-bit read.
//!
//! Requires that entire bit field is within the half word boundary.
//!
//! \param ui32Base is the base address of the DDI port.
//! \param ui32Reg is register to access.
//! \param ui32Mask is the mask defining which of the 16 bits that should be overwritten.
//! \param ui32Shift defines the required shift of the data to align with bit 0.
//!
//! \return Returns data aligned to bit 0.
//
//*****************************************************************************
extern uint16_t DDI16BitfieldRead(uint32_t ui32Base, uint32_t ui32Reg,
uint32_t ui32Mask, uint32_t ui32Shift);
//*****************************************************************************
//
// Support for DriverLib in ROM:
// Redirect to implementation in ROM when available.
//
//*****************************************************************************
#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
#include "../driverlib/rom.h"
#ifdef ROM_DDI32RegWrite
#undef DDI32RegWrite
#define DDI32RegWrite ROM_DDI32RegWrite
#endif
#ifdef ROM_DDI16BitWrite
#undef DDI16BitWrite
#define DDI16BitWrite ROM_DDI16BitWrite
#endif
#ifdef ROM_DDI16BitfieldWrite
#undef DDI16BitfieldWrite
#define DDI16BitfieldWrite ROM_DDI16BitfieldWrite
#endif
#ifdef ROM_DDI16BitRead
#undef DDI16BitRead
#define DDI16BitRead ROM_DDI16BitRead
#endif
#ifdef ROM_DDI16BitfieldRead
#undef DDI16BitfieldRead
#define DDI16BitfieldRead ROM_DDI16BitfieldRead
#endif
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DDI_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

67
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@ -1,67 +0,0 @@
/******************************************************************************
* Filename: ddi_doc.h
* Revised: 2016-08-30 14:34:13 +0200 (Tue, 30 Aug 2016)
* Revision: 47080
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//! \addtogroup ddi_api
//! @{
//! \section sec_ddi Introduction
//! \n
//!
//! \section sec_ddi_api API
//!
//! The API functions can be grouped like this:
//!
//! Write:
//! - Direct (all bits):
//! - \ref DDI32RegWrite()
//! - Set individual bits:
//! - \ref DDI32BitsSet()
//! - Clear individual bits:
//! - \ref DDI32BitsClear()
//! - Masked:
//! - \ref DDI8SetValBit()
//! - \ref DDI16SetValBit()
//! - Special functions using masked write:
//! - \ref DDI16BitWrite()
//! - \ref DDI16BitfieldWrite()
//!
//! Read:
//! - Direct (all bits):
//! - \ref DDI32RegRead()
//! - Special functions using masked read:
//! - \ref DDI16BitRead()
//! - \ref DDI16BitfieldRead()
//!
//!
//! @}

57
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/debug.c
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@ -1,57 +0,0 @@
/******************************************************************************
* Filename: debug.c
* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017)
* Revision: 48852
*
* Description: Driver for the Debug functionality (NB. This is a stub which
* should never be included in a release).
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include <stdbool.h>
#include <stdint.h>
#include "../inc/hw_types.h"
#include "debug.h"
//*****************************************************************************
//
// Function stub for allowing compile with DRIVERLIB_DEBUG flag asserted.
//
//*****************************************************************************
void
__error__(char *pcFilename, uint32_t ui32Line)
{
// Error catching.
// User can implement custom error handling for failing ASSERTs.
// Setting breakpoint here allows tracing of the failing ASSERT.
while( true );
}

84
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@ -1,84 +0,0 @@
/******************************************************************************
* Filename: debug.h
* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017)
* Revision: 48852
*
* Description: Macros for assisting debug of the driver library.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup system_control_group
//! @{
//! \addtogroup debug_api
//! @{
//
//*****************************************************************************
#ifndef __DEBUG_H__
#define __DEBUG_H__
//*****************************************************************************
//
//! Function stub for allowing compile with DRIVERLIB_DEBUG flag asserted.
//
//*****************************************************************************
extern void __error__(char *pcFilename, uint32_t ui32Line);
//*****************************************************************************
//
// The ASSERT macro, which does the actual assertion checking. Typically, this
// will be for procedure arguments.
//
//*****************************************************************************
#ifdef DRIVERLIB_DEBUG
#define ASSERT(expr) { \
if(!(expr)) \
{ \
__error__(__FILE__, __LINE__); \
} \
}
#else
#define ASSERT(expr)
#endif
#endif // __DEBUG_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

45
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.c
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@ -1,45 +0,0 @@
/******************************************************************************
* Filename: driverlib_release.c
* Revised: $Date: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) $
* Revision: $Revision: 47152 $
*
* Description: Provides macros for ensuring that a specfic release of
* DriverLib is used.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "../driverlib/driverlib_release.h"
/// Declare the current DriverLib release
DRIVERLIB_DECLARE_RELEASE(0, 54539);

156
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@ -1,156 +0,0 @@
/******************************************************************************
* Filename: driverlib_release.h
* Revised: $Date: 2015-07-16 12:12:04 +0200 (Thu, 16 Jul 2015) $
* Revision: $Revision: 44151 $
*
* Description: Provides macros for ensuring that a specfic release of
* DriverLib is used.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup system_control_group
//! @{
//! \addtogroup driverlib_release_api
//! @{
//
//*****************************************************************************
#ifndef __DRIVERLIB_RELEASE_H__
#define __DRIVERLIB_RELEASE_H__
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
/// DriverLib release group number
#define DRIVERLIB_RELEASE_GROUP 0
/// DriverLib release build number
#define DRIVERLIB_RELEASE_BUILD 54539
//*****************************************************************************
//
//! This macro is called internally from within DriverLib to declare the
//! DriverLib release locking object:
//! \param group is the DriverLib release group number.
//! \param build is the DriverLib release build number.
//!
//! This macro shall not be called in the application unless the intention is
//! to bypass the release locking (at own risk).
//
//*****************************************************************************
#define DRIVERLIB_DECLARE_RELEASE(group, build) \
const volatile uint8_t driverlib_release_##group##_##build
/// External declaration of the DriverLib release locking object
extern DRIVERLIB_DECLARE_RELEASE(0, 54539);
//*****************************************************************************
//
//! This macro shall be called once from within a function of a precompiled
//! software deliverable to lock the deliverable to a specific DriverLib
//! release. It is essential that the call is made from code that is not
//! optimized away.
//!
//! This macro locks to a specific DriverLib release:
//! \param group is the DriverLib release group number.
//! \param build is the DriverLib release build number.
//!
//! If attempting to use the precompiled deliverable with a different release
//! of DriverLib, a linker error will be produced, stating that
//! "driverlib_release_xx_yyyyy is undefined" or similar.
//!
//! To override the check, for example when upgrading DriverLib but not the
//! precompiled deliverables, or when mixing precompiled deliverables,
//! application developers may (at own risk) declare the missing DriverLib
//! release using the \ref DRIVERLIB_DECLARE_RELEASE() macro.
//
//*****************************************************************************
#define DRIVERLIB_ASSERT_RELEASE(group, build) \
(driverlib_release_##group##_##build)
//*****************************************************************************
//
//! This macro shall be called once from within a function of a precompiled
//! software deliverable to lock the deliverable to a specific DriverLib
//! release. It is essential that the call is made from code that is not
//! optimized away.
//!
//! This macro locks to the current DriverLib release used at compile-time.
//!
//! If attempting to use the precompiled deliverable with a different release
//! of DriverLib, a linker error will be produced, stating that
//! "driverlib_release_xx_yyyyy is undefined" or similar.
//!
//! To override the check, for example when upgrading DriverLib but not the
//! precompiled deliverables, or when mixing precompiled deliverables,
//! application developers may (at own risk) declare the missing DriverLib
//! release using the \ref DRIVERLIB_DECLARE_RELEASE() macro.
//
//*****************************************************************************
#define DRIVERLIB_ASSERT_CURR_RELEASE() \
DRIVERLIB_ASSERT_RELEASE(0, 54539)
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_RELEASE_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

41
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/event.c
View file

@ -1,41 +0,0 @@
/******************************************************************************
* Filename: event.c
* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016)
* Revision: 47179
*
* Description: Driver for the Event Fabric.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "event.h"
// See event.h for implementation

267
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@ -1,267 +0,0 @@
/******************************************************************************
* Filename: event.h
* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016)
* Revision: 47179
*
* Description: Defines and prototypes for the Event Handler.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup peripheral_group
//! @{
//! \addtogroup event_api
//! @{
//
//*****************************************************************************
#ifndef __EVENT_H__
#define __EVENT_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdbool.h>
#include <stdint.h>
#include "../inc/hw_types.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_event.h"
#include "debug.h"
//*****************************************************************************
//
// API Functions and prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Connects an event to an event subscriber via Event Fabric.
//!
//! This function connects event sources to event subscribers.
//!
//! It is not possible to read event status in this module (except software events).
//! Event status must be read in the module that contains the event source. How a
//! specific event subscriber reacts to an event is configured and documented in
//! the respective modules.
//!
//! For a full list of configurable and constant mapped event sources to event
//! subscribers see the register descriptions for
//! <a href="../register_descriptions/CPU_MMAP/EVENT.html" target="_blank">Event Fabric</a>.
//!
//! Defines for event subscriber argument (\c ui32EventSubscriber) have the format:
//! - \ti_code{EVENT_O_[subscriber_name]}
//!
//! Defines for event source argument (\c ui32EventSource) must have the
//! following format where valid \c event_enum values are found in the
//! register description :
//! - \ti_code{EVENT_[subscriber_name]_EV_[event_enum]}
//!
//! Examples of valid defines for \c ui32EventSource:
//! - EVENT_CPUIRQSEL30_EV_AUX_TDC_DONE
//! - EVENT_RFCSEL9_EV_AUX_COMPA
//! - EVENT_GPT0ACAPTSEL_EV_AON_RTC_UPD
//!
//! \note Each event subscriber can only receive a sub-set of the event sources!
//!
//! \note Switching the event source is not glitch free, so it is imperative
//! that the subscriber is disabled for interrupts when switching the event
//! source. The behavior is undefined if not disabled.
//!
//! \param ui32EventSubscriber is the \b configurable event subscriber to receive the event.
//! Click the event subscriber to see the list of valid event sources in the
//! register description.
//! - EVENT_O_CPUIRQSEL30 : System CPU interrupt 30
//! - EVENT_O_RFCSEL9 : RF Core event 9
//! - EVENT_O_GPT0ACAPTSEL : GPT 0A capture event
//! - EVENT_O_GPT0BCAPTSEL : GPT 0B capture event
//! - EVENT_O_GPT1ACAPTSEL : GPT 1A capture event
//! - EVENT_O_GPT1BCAPTSEL : GPT 1B capture event
//! - EVENT_O_GPT2ACAPTSEL : GPT 2A capture event
//! - EVENT_O_GPT2BCAPTSEL : GPT 2B capture event
//! - EVENT_O_GPT3ACAPTSEL : GPT 3A capture event
//! - EVENT_O_GPT3BCAPTSEL : GPT 3B capture event
//! - EVENT_O_UDMACH9SSEL : uDMA channel 9 single request
//! - EVENT_O_UDMACH9BSEL : uDMA channel 9 burst request
//! - EVENT_O_UDMACH10SSEL : uDMA channel 10 single request
//! - EVENT_O_UDMACH10BSEL : uDMA channel 10 burst request
//! - EVENT_O_UDMACH11SSEL : uDMA channel 11 single request
//! - EVENT_O_UDMACH11BSEL : uDMA channel 11 burst request
//! - EVENT_O_UDMACH12SSEL : uDMA channel 12 single request
//! - EVENT_O_UDMACH12BSEL : uDMA channel 12 burst request
//! - EVENT_O_UDMACH14BSEL : uDMA channel 14 single request
//! - EVENT_O_AUXSEL0 : AUX
//! - EVENT_O_I2SSTMPSEL0 : I2S
//! - EVENT_O_FRZSEL0 : Freeze modules (some modules can freeze on CPU Halt)
//! \param ui32EventSource is the specific event that must be acted upon.
//! - Format: \ti_code{EVENT_[subscriber_name]_EV_[event_enum]} (see explanation above)
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
EventRegister(uint32_t ui32EventSubscriber, uint32_t ui32EventSource)
{
// Check the arguments.
ASSERT(( ui32EventSubscriber == EVENT_O_CPUIRQSEL30 ) ||
( ui32EventSubscriber == EVENT_O_RFCSEL9 ) ||
( ui32EventSubscriber == EVENT_O_GPT0ACAPTSEL ) ||
( ui32EventSubscriber == EVENT_O_GPT0BCAPTSEL ) ||
( ui32EventSubscriber == EVENT_O_GPT1ACAPTSEL ) ||
( ui32EventSubscriber == EVENT_O_GPT1BCAPTSEL ) ||
( ui32EventSubscriber == EVENT_O_GPT2ACAPTSEL ) ||
( ui32EventSubscriber == EVENT_O_GPT2BCAPTSEL ) ||
( ui32EventSubscriber == EVENT_O_GPT3ACAPTSEL ) ||
( ui32EventSubscriber == EVENT_O_GPT3BCAPTSEL ) ||
( ui32EventSubscriber == EVENT_O_UDMACH9SSEL ) ||
( ui32EventSubscriber == EVENT_O_UDMACH9BSEL ) ||
( ui32EventSubscriber == EVENT_O_UDMACH10SSEL ) ||
( ui32EventSubscriber == EVENT_O_UDMACH10BSEL ) ||
( ui32EventSubscriber == EVENT_O_UDMACH11SSEL ) ||
( ui32EventSubscriber == EVENT_O_UDMACH11BSEL ) ||
( ui32EventSubscriber == EVENT_O_UDMACH12SSEL ) ||
( ui32EventSubscriber == EVENT_O_UDMACH12BSEL ) ||
( ui32EventSubscriber == EVENT_O_UDMACH14BSEL ) ||
( ui32EventSubscriber == EVENT_O_AUXSEL0 ) ||
( ui32EventSubscriber == EVENT_O_I2SSTMPSEL0 ) ||
( ui32EventSubscriber == EVENT_O_FRZSEL0 ) );
// Map the event source to the event subscriber
HWREG(EVENT_BASE + ui32EventSubscriber) = ui32EventSource;
}
//*****************************************************************************
//
//! \brief Sets software event.
//!
//! Setting a software event triggers the event if the value was 0 before.
//!
//! \note The software event must be cleared manually after the event has
//! triggered the event subscriber.
//!
//! \param ui32SwEvent is the software event number.
//! - 0 : SW Event 0
//! - 1 : SW Event 1
//! - 2 : SW Event 2
//! - 3 : SW Event 3
//!
//! \return None
//!
//! \sa \ref EventSwEventClear()
//
//*****************************************************************************
__STATIC_INLINE void
EventSwEventSet(uint32_t ui32SwEvent)
{
// Check the arguments.
ASSERT( ui32SwEvent <= 3 );
// Each software event is byte accessible
HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent) = 1;
}
//*****************************************************************************
//
//! \brief Clears software event.
//!
//! \param ui32SwEvent is the software event number.
//! - 0 : SW Event 0
//! - 1 : SW Event 1
//! - 2 : SW Event 2
//! - 3 : SW Event 3
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
EventSwEventClear(uint32_t ui32SwEvent)
{
// Check the arguments.
ASSERT( ui32SwEvent <= 3 );
// Each software event is byte accessible
HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent) = 0;
}
//*****************************************************************************
//
//! \brief Gets software event status.
//!
//! \param ui32SwEvent is the software event number.
//! - 0 : SW Event 0
//! - 1 : SW Event 1
//! - 2 : SW Event 2
//! - 3 : SW Event 3
//!
//! \return Returns current value of requested software event.
//! - 0 : Software event is de-asserted.
//! - 1 : Software event is asserted.
//
//*****************************************************************************
__STATIC_INLINE uint32_t
EventSwEventGet(uint32_t ui32SwEvent)
{
// Check the arguments.
ASSERT( ui32SwEvent <= 3 );
// Each software event is byte accessible
return( HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent));
}
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __EVENT_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

58
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@ -1,58 +0,0 @@
/******************************************************************************
* Filename: event_doc.h
* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016)
* Revision: 45971
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//! \addtogroup event_api
//! @{
//! \section sec_event Introduction
//!
//! The event fabric consists of two event modules. One in the MCU power domain (MCU event fabric) and
//! the other in the AON power domain (AON event fabric). The MCU event fabric is one of the subscribers
//! to the AON event fabric. For more information on AON event fabric, see [AON event API](@ref aonevent_api).
//!
//! The MCU event fabric is a combinational router between event sources and event subscribers. Most
//! event subscribers have statically routed event sources but several event subscribers have
//! configurable event sources which is configured in the MCU event fabric through this API. Although
//! configurable only a subset of event sources are available to each of the configurable event subscribers.
//! This is explained in more details in the function @ref EventRegister() which does all the event routing
//! configuration.
//!
//! MCU event fabric also contains four software events which allow software to trigger certain event
//! subscribers. Each of the four software events is an independent event source which must be set and
//! cleared in the MCU event fabric through the functions:
//! - @ref EventSwEventSet()
//! - @ref EventSwEventClear()
//! - @ref EventSwEventGet()
//!
//! @}

672
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/flash.c
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@ -1,672 +0,0 @@
/******************************************************************************
* Filename: flash.c
* Revised: 2017-10-30 13:37:49 +0100 (Mon, 30 Oct 2017)
* Revision: 50105
*
* Description: Driver for on chip Flash.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "../inc/hw_types.h"
#include "../inc/hw_ccfg.h"
#include "flash.h"
#include "rom.h"
#include "chipinfo.h"
//*****************************************************************************
//
// Handle support for DriverLib in ROM:
// This section will undo prototype renaming made in the header file
//
//*****************************************************************************
#if !defined(DOXYGEN)
#undef FlashPowerModeSet
#define FlashPowerModeSet NOROM_FlashPowerModeSet
#undef FlashPowerModeGet
#define FlashPowerModeGet NOROM_FlashPowerModeGet
#undef FlashProtectionSet
#define FlashProtectionSet NOROM_FlashProtectionSet
#undef FlashProtectionGet
#define FlashProtectionGet NOROM_FlashProtectionGet
#undef FlashProtectionSave
#define FlashProtectionSave NOROM_FlashProtectionSave
#undef FlashSectorErase
#define FlashSectorErase NOROM_FlashSectorErase
#undef FlashProgram
#define FlashProgram NOROM_FlashProgram
#undef FlashEfuseReadRow
#define FlashEfuseReadRow NOROM_FlashEfuseReadRow
#undef FlashDisableSectorsForWrite
#define FlashDisableSectorsForWrite NOROM_FlashDisableSectorsForWrite
#endif
//*****************************************************************************
//
// Defines for accesses to the security control in the customer configuration
// area in flash top sector.
//
//*****************************************************************************
#define CCFG_OFFSET_SECURITY CCFG_O_BL_CONFIG
#define CCFG_OFFSET_SECT_PROT CCFG_O_CCFG_PROT_31_0
#define CCFG_SIZE_SECURITY 0x00000014
#define CCFG_SIZE_SECT_PROT 0x00000004
//*****************************************************************************
//
// Default values for security control in customer configuration area in flash
// top sector.
//
//*****************************************************************************
const uint8_t g_pui8CcfgDefaultSec[] = {0xFF, 0xFF, 0xFF, 0xC5,
0xFF, 0xFF, 0xFF, 0xFF,
0xC5, 0xFF, 0xFF, 0xFF,
0xC5, 0xC5, 0xC5, 0xFF,
0xC5, 0xC5, 0xC5, 0xFF
};
typedef uint32_t (* FlashPrgPointer_t) (uint8_t *, uint32_t, uint32_t);
typedef uint32_t (* FlashSectorErasePointer_t) (uint32_t);
//*****************************************************************************
//
// Function prototypes for static functions
//
//*****************************************************************************
static void SetReadMode(void);
//*****************************************************************************
//
// Set power mode
//
//*****************************************************************************
void
FlashPowerModeSet(uint32_t ui32PowerMode, uint32_t ui32BankGracePeriod,
uint32_t ui32PumpGracePeriod)
{
// Check the arguments.
ASSERT(ui32PowerMode == FLASH_PWR_ACTIVE_MODE ||
ui32PowerMode == FLASH_PWR_OFF_MODE ||
ui32PowerMode == FLASH_PWR_DEEP_STDBY_MODE);
ASSERT(ui32BankGracePeriod <= 0xFF);
ASSERT(ui32PumpGracePeriod <= 0xFFFF);
switch(ui32PowerMode)
{
case FLASH_PWR_ACTIVE_MODE:
// Set bank power mode to ACTIVE.
HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) =
(HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &
~FLASH_FBFALLBACK_BANKPWR0_M) | FBFALLBACK_ACTIVE;
// Set charge pump power mode to ACTIVE mode.
HWREG(FLASH_BASE + FLASH_O_FPAC1) =
(HWREG(FLASH_BASE + FLASH_O_FPAC1) & ~FLASH_FPAC1_PUMPPWR_M) | (1 << FLASH_FPAC1_PUMPPWR_S);
break;
case FLASH_PWR_OFF_MODE:
// Set bank grace period.
HWREG(FLASH_BASE + FLASH_O_FBAC) =
(HWREG(FLASH_BASE + FLASH_O_FBAC) & (~FLASH_FBAC_BAGP_M)) |
((ui32BankGracePeriod << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M);
// Set pump grace period.
HWREG(FLASH_BASE + FLASH_O_FPAC2) =
(HWREG(FLASH_BASE + FLASH_O_FPAC2) & (~FLASH_FPAC2_PAGP_M)) |
((ui32PumpGracePeriod << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M);
// Set bank power mode to SLEEP.
HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &= ~FLASH_FBFALLBACK_BANKPWR0_M;
// Set charge pump power mode to SLEEP mode.
HWREG(FLASH_BASE + FLASH_O_FPAC1) &= ~FLASH_FPAC1_PUMPPWR_M;
break;
case FLASH_PWR_DEEP_STDBY_MODE:
// Set bank grace period.
HWREG(FLASH_BASE + FLASH_O_FBAC) =
(HWREG(FLASH_BASE + FLASH_O_FBAC) & (~FLASH_FBAC_BAGP_M)) |
((ui32BankGracePeriod << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M);
// Set pump grace period.
HWREG(FLASH_BASE + FLASH_O_FPAC2) =
(HWREG(FLASH_BASE + FLASH_O_FPAC2) & (~FLASH_FPAC2_PAGP_M)) |
((ui32PumpGracePeriod << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M);
// Set bank power mode to DEEP STANDBY mode.
HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) =
(HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &
~FLASH_FBFALLBACK_BANKPWR0_M) | FBFALLBACK_DEEP_STDBY;
// Set charge pump power mode to STANDBY mode.
HWREG(FLASH_BASE + FLASH_O_FPAC1) |= FLASH_FPAC1_PUMPPWR_M;
break;
}
}
//*****************************************************************************
//
// Get current configured power mode
//
//*****************************************************************************
uint32_t
FlashPowerModeGet(void)
{
uint32_t ui32PowerMode;
uint32_t ui32BankPwrMode;
ui32BankPwrMode = HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &
FLASH_FBFALLBACK_BANKPWR0_M;
if(ui32BankPwrMode == FBFALLBACK_SLEEP)
{
ui32PowerMode = FLASH_PWR_OFF_MODE;
}
else if(ui32BankPwrMode == FBFALLBACK_DEEP_STDBY)
{
ui32PowerMode = FLASH_PWR_DEEP_STDBY_MODE;
}
else
{
ui32PowerMode = FLASH_PWR_ACTIVE_MODE;
}
// Return power mode.
return(ui32PowerMode);
}
//*****************************************************************************
//
// Set sector protection
//
//*****************************************************************************
void
FlashProtectionSet(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode)
{
uint32_t ui32SectorNumber;
// Check the arguments.
ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() -
FlashSectorSizeGet()));
ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00);
if(ui32ProtectMode == FLASH_WRITE_PROTECT)
{
ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) /
FlashSectorSizeGet();
HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
if(ui32SectorNumber <= 31)
{
HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) |= (1 << ui32SectorNumber);
HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) |= (1 << ui32SectorNumber);
}
else if(ui32SectorNumber <= 63)
{
HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) |=
(1 << (ui32SectorNumber & 0x1F));
HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) |=
(1 << (ui32SectorNumber & 0x1F));
}
HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
}
}
//*****************************************************************************
//
// Get sector protection
//
//*****************************************************************************
uint32_t
FlashProtectionGet(uint32_t ui32SectorAddress)
{
uint32_t ui32SectorProtect;
uint32_t ui32SectorNumber;
// Check the arguments.
ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() -
FlashSectorSizeGet()));
ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00);
ui32SectorProtect = FLASH_NO_PROTECT;
ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet();
if(ui32SectorNumber <= 31)
{
if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) & (1 << ui32SectorNumber)) &&
(HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) & (1 << ui32SectorNumber)))
{
ui32SectorProtect = FLASH_WRITE_PROTECT;
}
}
else if(ui32SectorNumber <= 63)
{
if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) &
(1 << (ui32SectorNumber & 0x1F))) &&
(HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) &
(1 << (ui32SectorNumber & 0x1F))))
{
ui32SectorProtect = FLASH_WRITE_PROTECT;
}
}
return(ui32SectorProtect);
}
//*****************************************************************************
//
// Save sector protection to make it permanent
//
//*****************************************************************************
uint32_t
FlashProtectionSave(uint32_t ui32SectorAddress)
{
uint32_t ui32ErrorReturn;
uint32_t ui32SectorNumber;
uint32_t ui32CcfgSectorAddr;
uint32_t ui32ProgBuf;
ui32ErrorReturn = FAPI_STATUS_SUCCESS;
// Check the arguments.
ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() -
FlashSectorSizeGet()));
ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00);
if(FlashProtectionGet(ui32SectorAddress) == FLASH_WRITE_PROTECT)
{
// Find sector number for specified sector.
ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet();
ui32CcfgSectorAddr = FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet();
// Adjust CCFG address to the 32-bit CCFG word holding the
// protect-bit for the specified sector.
ui32CcfgSectorAddr += (((ui32SectorNumber >> 5) * 4) + CCFG_OFFSET_SECT_PROT);
// Find value to program by setting the protect-bit which
// corresponds to specified sector number, to 0.
// Leave other protect-bits unchanged.
ui32ProgBuf = (~(1 << (ui32SectorNumber & 0x1F))) &
*(uint32_t *)ui32CcfgSectorAddr;
ui32ErrorReturn = FlashProgram((uint8_t*)&ui32ProgBuf, ui32CcfgSectorAddr,
CCFG_SIZE_SECT_PROT);
}
// Return status.
return(ui32ErrorReturn);
}
//*****************************************************************************
//
// Erase a flash sector
//
//*****************************************************************************
uint32_t
FlashSectorErase(uint32_t ui32SectorAddress)
{
uint32_t ui32ErrorReturn;
FlashSectorErasePointer_t FuncPointer;
// Check the arguments.
ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() -
FlashSectorSizeGet()));
ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00);
// Call ROM function that handles the actual erase operation
FuncPointer = (uint32_t (*)(uint32_t)) (ROM_API_FLASH_TABLE[5]);
ui32ErrorReturn = FuncPointer(ui32SectorAddress);
// Enable standby in flash bank since ROM function might have disabled it
HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0;
// Return status of operation.
return(ui32ErrorReturn);
}
//*****************************************************************************
//
// Programs unprotected main bank flash sectors
//
//*****************************************************************************
uint32_t
FlashProgram(uint8_t *pui8DataBuffer, uint32_t ui32Address, uint32_t ui32Count)
{
uint32_t ui32ErrorReturn;
FlashPrgPointer_t FuncPointer;
// Check the arguments.
ASSERT((ui32Address + ui32Count) <= (FLASHMEM_BASE + FlashSizeGet()));
// Call ROM function that handles the actual program operation
FuncPointer = (uint32_t (*)(uint8_t *, uint32_t, uint32_t)) (ROM_API_FLASH_TABLE[6]);
ui32ErrorReturn = FuncPointer( pui8DataBuffer, ui32Address, ui32Count);
// Enable standby in flash bank since ROM function might have disabled it
HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0;
// Return status of operation.
return(ui32ErrorReturn);
}
//*****************************************************************************
//
// Reads efuse data from specified row
//
//*****************************************************************************
bool
FlashEfuseReadRow(uint32_t *pui32EfuseData, uint32_t ui32RowAddress)
{
bool bStatus;
// Make sure the clock for the efuse is enabled
HWREG(FLASH_BASE + FLASH_O_CFG) &= ~FLASH_CFG_DIS_EFUSECLK;
// Set timing for EFUSE read operations.
HWREG(FLASH_BASE + FLASH_O_EFUSEREAD) |= ((5 << FLASH_EFUSEREAD_READCLOCK_S) &
FLASH_EFUSEREAD_READCLOCK_M);
// Clear status register.
HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) = 0;
// Select the FuseROM block 0.
HWREG(FLASH_BASE + FLASH_O_EFUSEADDR) = 0x00000000;
// Start the read operation.
HWREG(FLASH_BASE + FLASH_O_EFUSE) =
(DUMPWORD_INSTR << FLASH_EFUSE_INSTRUCTION_S) |
(ui32RowAddress & FLASH_EFUSE_DUMPWORD_M);
// Wait for operation to finish.
while(!(HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) & FLASH_EFUSEERROR_DONE))
{
}
// Check if error reported.
if(HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) & FLASH_EFUSEERROR_CODE_M)
{
// Set error status.
bStatus = 1;
// Clear data.
*pui32EfuseData = 0;
}
else
{
// Set ok status.
bStatus = 0;
// No error. Get data from data register.
*pui32EfuseData = HWREG(FLASH_BASE + FLASH_O_DATALOWER);
}
// Disable the efuse clock to conserve power
HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_EFUSECLK;
// Return the data.
return(bStatus);
}
//*****************************************************************************
//
// Disables all sectors for erase and programming on the active bank
//
//*****************************************************************************
void
FlashDisableSectorsForWrite(void)
{
// Configure flash back to read mode
SetReadMode();
// Disable Level 1 Protection.
HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS;
// Disable all sectors for erase and programming.
HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000;
// Enable Level 1 Protection.
HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0;
// Protect sectors from sector erase.
HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF;
HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF;
HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
}
//*****************************************************************************
//
//! \internal
//! Used to set flash in read mode.
//!
//! Flash is configured with values loaded from OTP dependent on the current
//! regulator mode.
//!
//! \return None.
//
//*****************************************************************************
static void
SetReadMode(void)
{
uint32_t ui32TrimValue;
uint32_t ui32Value;
// Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE,
// VIN_AT_X and VIN_BY_PASS for read mode
if(HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) &
AON_PMCTL_PWRCTL_EXT_REG_MODE)
{
// Select trim values for external regulator mode:
// Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 7)
// COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 6:5)
// Must be done while the register bit field CONFIG.DIS_STANDBY = 1
HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY;
ui32TrimValue =
HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4);
ui32Value = ((ui32TrimValue &
FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M) >>
FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S) <<
FLASH_CFG_STANDBY_MODE_SEL_S;
ui32Value |= ((ui32TrimValue &
FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M) >>
FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S) <<
FLASH_CFG_STANDBY_PW_SEL_S;
// Configure DIS_STANDBY (OTP offset 0x308 bit 4).
// Configure DIS_IDLE (OTP offset 0x308 bit 3).
ui32Value |= ((ui32TrimValue &
(FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M |
FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M)) >>
FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S) <<
FLASH_CFG_DIS_IDLE_S;
HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) &
~(FLASH_CFG_STANDBY_MODE_SEL_M |
FLASH_CFG_STANDBY_PW_SEL_M |
FLASH_CFG_DIS_STANDBY_M |
FLASH_CFG_DIS_IDLE_M)) | ui32Value;
// Check if sample and hold functionality is disabled.
if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE)
{
// Wait for disabled sample and hold functionality to be stable.
while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS))
{
}
}
// Configure VIN_AT_X (OTP offset 0x308 bits 2:0)
ui32Value = ((ui32TrimValue &
FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M) >>
FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S) <<
FLASH_FSEQPMP_VIN_AT_X_S;
// Configure VIN_BY_PASS which is dependent on the VIN_AT_X value.
// If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise
// VIN_BY_PASS should be 1
if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >>
FLASH_FSEQPMP_VIN_AT_X_S) != 0x7)
{
ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS;
}
HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA;
HWREG(FLASH_BASE + FLASH_O_FSEQPMP) =
(HWREG(FLASH_BASE + FLASH_O_FSEQPMP) &
~(FLASH_FSEQPMP_VIN_BY_PASS_M |
FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value;
HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA;
}
else
{
// Select trim values for internal regulator mode:
// Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 15)
// COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 14:13)
// Must be done while the register bit field CONFIG.DIS_STANDBY = 1
HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY;
ui32TrimValue =
HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4);
ui32Value = ((ui32TrimValue &
FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M) >>
FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S) <<
FLASH_CFG_STANDBY_MODE_SEL_S;
ui32Value |= ((ui32TrimValue &
FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M) >>
FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S) <<
FLASH_CFG_STANDBY_PW_SEL_S;
// Configure DIS_STANDBY (OTP offset 0x308 bit 12).
// Configure DIS_IDLE (OTP offset 0x308 bit 11).
ui32Value |= ((ui32TrimValue &
(FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M |
FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M)) >>
FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S) <<
FLASH_CFG_DIS_IDLE_S;
HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) &
~(FLASH_CFG_STANDBY_MODE_SEL_M |
FLASH_CFG_STANDBY_PW_SEL_M |
FLASH_CFG_DIS_STANDBY_M |
FLASH_CFG_DIS_IDLE_M)) | ui32Value;
// Check if sample and hold functionality is disabled.
if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE)
{
// Wait for disabled sample and hold functionality to be stable.
while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS))
{
}
}
// Configure VIN_AT_X (OTP offset 0x308 bits 10:8)
ui32Value = (((ui32TrimValue &
FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M) >>
FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S) <<
FLASH_FSEQPMP_VIN_AT_X_S);
// Configure VIN_BY_PASS which is dependent on the VIN_AT_X value.
// If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise
// VIN_BY_PASS should be 1
if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >>
FLASH_FSEQPMP_VIN_AT_X_S) != 0x7)
{
ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS;
}
HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA;
HWREG(FLASH_BASE + FLASH_O_FSEQPMP) =
(HWREG(FLASH_BASE + FLASH_O_FSEQPMP) &
~(FLASH_FSEQPMP_VIN_BY_PASS_M |
FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value;
HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA;
}
}
//*****************************************************************************
//
// HAPI Flash program function
//
//*****************************************************************************
uint32_t
MemBusWrkAroundHapiProgramFlash(uint8_t *pui8DataBuffer, uint32_t ui32Address,
uint32_t ui32Count)
{
uint32_t ui32ErrorReturn;
FlashPrgPointer_t FuncPointer;
uint32_t ui32RomAddr = HWREG(ROM_HAPI_TABLE_ADDR + (5 * 4));
// Call ROM function
FuncPointer = (uint32_t (*)(uint8_t *, uint32_t, uint32_t)) (ui32RomAddr);
ui32ErrorReturn = FuncPointer( pui8DataBuffer, ui32Address, ui32Count);
// Enable standby in flash bank since ROM function might have disabled it
HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0;
// Return status of operation.
return(ui32ErrorReturn);
}
//*****************************************************************************
//
// HAPI Flash sector erase function
//
//*****************************************************************************
uint32_t
MemBusWrkAroundHapiEraseSector(uint32_t ui32Address)
{
uint32_t ui32ErrorReturn;
FlashSectorErasePointer_t FuncPointer;
uint32_t ui32RomAddr = HWREG(ROM_HAPI_TABLE_ADDR + (3 * 4));
// Call ROM function
FuncPointer = (uint32_t (*)(uint32_t)) (ui32RomAddr);
ui32ErrorReturn = FuncPointer(ui32Address);
// Enable standby in flash bank since ROM function might have disabled it
HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0;
// Return status of operation.
return(ui32ErrorReturn);
}

817
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/flash.h
View file

@ -1,817 +0,0 @@
/******************************************************************************
* Filename: flash.h
* Revised: 2017-11-02 16:09:32 +0100 (Thu, 02 Nov 2017)
* Revision: 50166
*
* Description: Defines and prototypes for the Flash driver.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup system_control_group
//! @{
//! \addtogroup flash_api
//! @{
//
//*****************************************************************************
#ifndef __FLASH_H__
#define __FLASH_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdbool.h>
#include <stdint.h>
#include "../inc/hw_types.h"
#include "../inc/hw_flash.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_ints.h"
#include "../inc/hw_aon_pmctl.h"
#include "../inc/hw_fcfg1.h"
#include "interrupt.h"
#include "debug.h"
//*****************************************************************************
//
// Support for DriverLib in ROM:
// This section renames all functions that are not "static inline", so that
// calling these functions will default to implementation in flash. At the end
// of this file a second renaming will change the defaults to implementation in
// ROM for available functions.
//
// To force use of the implementation in flash, e.g. for debugging:
// - Globally: Define DRIVERLIB_NOROM at project level
// - Per function: Use prefix "NOROM_" when calling the function
//
//*****************************************************************************
#if !defined(DOXYGEN)
#define FlashPowerModeSet NOROM_FlashPowerModeSet
#define FlashPowerModeGet NOROM_FlashPowerModeGet
#define FlashProtectionSet NOROM_FlashProtectionSet
#define FlashProtectionGet NOROM_FlashProtectionGet
#define FlashProtectionSave NOROM_FlashProtectionSave
#define FlashSectorErase NOROM_FlashSectorErase
#define FlashProgram NOROM_FlashProgram
#define FlashEfuseReadRow NOROM_FlashEfuseReadRow
#define FlashDisableSectorsForWrite NOROM_FlashDisableSectorsForWrite
#endif
//*****************************************************************************
//
// Values that can be returned from the API functions
//
//*****************************************************************************
#define FAPI_STATUS_SUCCESS 0x00000000 // Function completed successfully
#define FAPI_STATUS_FSM_BUSY 0x00000001 // FSM is Busy
#define FAPI_STATUS_FSM_READY 0x00000002 // FSM is Ready
#define FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH \
0x00000003 // Incorrect parameter value
#define FAPI_STATUS_FSM_ERROR 0x00000004 // Operation failed
//*****************************************************************************
//
// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and
// returned from FlashIntStatus().
//
//*****************************************************************************
#define FLASH_INT_FSM_DONE 0x00400000 // FSM Done Interrupt Mask
#define FLASH_INT_RV 0x00010000 // Read Verify error Interrupt Mask
//*****************************************************************************
//
// Values passed to FlashSetPowerMode() and returned from FlashGetPowerMode().
//
//*****************************************************************************
#define FLASH_PWR_ACTIVE_MODE 0x00000000
#define FLASH_PWR_OFF_MODE 0x00000001
#define FLASH_PWR_DEEP_STDBY_MODE \
0x00000002
//*****************************************************************************
//
// Values passed to FlashSetProtection() and returned from FlashGetProtection().
//
//*****************************************************************************
#define FLASH_NO_PROTECT 0x00000000 // Sector not protected
#define FLASH_WRITE_PROTECT 0x00000001 // Sector erase and program
// protected
//*****************************************************************************
//
// Define used by the flash programming and erase functions
//
//*****************************************************************************
#define ADDR_OFFSET (0x1F800000 - FLASHMEM_BASE)
//*****************************************************************************
//
// Define used for access to factory configuration area.
//
//*****************************************************************************
#define FCFG1_OFFSET 0x1000
//*****************************************************************************
//
// Define for the clock frequency input to the flash module in number of MHz
//
//*****************************************************************************
#define FLASH_MODULE_CLK_FREQ 48
//*****************************************************************************
//
//! \brief Defined values for Flash State Machine commands
//
//*****************************************************************************
typedef enum
{
FAPI_PROGRAM_DATA = 0x0002, //!< Program data.
FAPI_ERASE_SECTOR = 0x0006, //!< Erase sector.
FAPI_ERASE_BANK = 0x0008, //!< Erase bank.
FAPI_VALIDATE_SECTOR = 0x000E, //!< Validate sector.
FAPI_CLEAR_STATUS = 0x0010, //!< Clear status.
FAPI_PROGRAM_RESUME = 0x0014, //!< Program resume.
FAPI_ERASE_RESUME = 0x0016, //!< Erase resume.
FAPI_CLEAR_MORE = 0x0018, //!< Clear more.
FAPI_PROGRAM_SECTOR = 0x0020, //!< Program sector.
FAPI_ERASE_OTP = 0x0030 //!< Erase OTP.
} tFlashStateCommandsType;
//*****************************************************************************
//
// Defines for values written to the FLASH_O_FSM_WR_ENA register
//
//*****************************************************************************
#define FSM_REG_WRT_ENABLE 5
#define FSM_REG_WRT_DISABLE 2
//*****************************************************************************
//
// Defines for the bank power mode field the FLASH_O_FBFALLBACK register
//
//*****************************************************************************
#define FBFALLBACK_SLEEP 0
#define FBFALLBACK_DEEP_STDBY 1
#define FBFALLBACK_ACTIVE 3
//*****************************************************************************
//
// Defines for the bank grace period and pump grace period
//
//*****************************************************************************
#define FLASH_BAGP 0x14
#define FLASH_PAGP 0x14
//*****************************************************************************
//
// Defines used by the FlashProgramPattern() function
//
//*****************************************************************************
#define PATTERN_BITS 0x20 // No of bits in data pattern to program
//*****************************************************************************
//
// Defines for the FW flag bits in the FLASH_O_FWFLAG register
//
//*****************************************************************************
#define FW_WRT_TRIMMED 0x00000001
//*****************************************************************************
//
// Defines used by the flash programming functions
//
//*****************************************************************************
typedef volatile uint8_t tFwpWriteByte;
#define FWPWRITE_BYTE_ADDRESS ((tFwpWriteByte *)((FLASH_BASE + FLASH_O_FWPWRITE0)))
//*****************************************************************************
//
// Define for efuse instruction
//
//*****************************************************************************
#define DUMPWORD_INSTR 0x04
//*****************************************************************************
//
// Define for FSM command execution
//
//*****************************************************************************
#define FLASH_CMD_EXEC 0x15
//*****************************************************************************
//
//! \brief Get size of a flash sector in number of bytes.
//!
//! This function will return the size of a flash sector in number of bytes.
//!
//! \return Returns size of a flash sector in number of bytes.
//
//*****************************************************************************
__STATIC_INLINE uint32_t
FlashSectorSizeGet(void)
{
uint32_t ui32SectorSizeInKbyte;
ui32SectorSizeInKbyte = (HWREG(FLASH_BASE + FLASH_O_FCFG_B0_SSIZE0) &
FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M) >>
FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S;
// Return flash sector size in number of bytes.
return(ui32SectorSizeInKbyte * 1024);
}
//*****************************************************************************
//
//! \brief Get the size of the flash.
//!
//! This function returns the size of the flash main bank in number of bytes.
//!
//! \return Returns the flash size in number of bytes.
//
//*****************************************************************************
__STATIC_INLINE uint32_t
FlashSizeGet(void)
{
uint32_t ui32NoOfSectors;
// Get number of flash sectors
ui32NoOfSectors = (HWREG(FLASH_BASE + FLASH_O_FLASH_SIZE) &
FLASH_FLASH_SIZE_SECTORS_M) >>
FLASH_FLASH_SIZE_SECTORS_S;
// Return flash size in number of bytes
return(ui32NoOfSectors * FlashSectorSizeGet());
}
//*****************************************************************************
//
//! \brief Set power mode.
//!
//! This function will set the specified power mode.
//!
//! Any access to the bank causes a reload of the specified bank grace period
//! input value into the bank down counter. After the last access to the
//! flash bank, the down counter delays from 0 to 255 prescaled HCLK clock
//! cycles before putting the bank into one of the fallback power modes as
//! determined by \c ui32PowerMode. This value must be greater than 1 when the
//! fallback mode is not \ref FLASH_PWR_ACTIVE_MODE.
//!
//! Note: The prescaled clock used for the down counter is a clock divided by
//! 16 from input HCLK. The \c ui32BankGracePeriod parameter is ignored if
//! \c ui32PowerMode is equal to \ref FLASH_PWR_ACTIVE_MODE.
//! Any access to flash memory causes the pump grace period down counter to
//! reload with value of \c ui32PumpGracePeriod. After the bank has gone to sleep,
//! the down counter delays this number of prescaled HCLK clock cycles before
//! entering one of the charge pump fallback power modes as determined by
//! \c ui32PowerMode. The prescaled clock used for the pump grace period down
//! counter is a clock divided by 16 from input HCLK. This parameter is ignored
//! if \c ui32PowerMode is equal to \ref FLASH_PWR_ACTIVE_MODE.
//!
//! Changing the power mode of the flash module must be a part within a
//! device power mode transition requiring configuration of multiple modules.
//! Refer to documents describing the device power modes.
//!
//! \param ui32PowerMode is the wanted power mode.
//! The defined flash power modes are:
//! - \ref FLASH_PWR_ACTIVE_MODE
//! - \ref FLASH_PWR_OFF_MODE
//! - \ref FLASH_PWR_DEEP_STDBY_MODE
//! \param ui32BankGracePeriod is the starting count value for the bank grace
//! period down counter.
//! \param ui32PumpGracePeriod is the starting count value for the pump grace
//! period down counter.
//!
//! \return None
//
//*****************************************************************************
extern void FlashPowerModeSet(uint32_t ui32PowerMode,
uint32_t ui32BankGracePeriod,
uint32_t ui32PumpGracePeriod);
//*****************************************************************************
//
//! \brief Get current configured power mode.
//!
//! This function will return the current configured power mode.
//!
//! \return Returns the current configured power mode.
//! The defined power modes are:
//! - \ref FLASH_PWR_ACTIVE_MODE
//! - \ref FLASH_PWR_OFF_MODE
//! - \ref FLASH_PWR_DEEP_STDBY_MODE
//
//*****************************************************************************
extern uint32_t FlashPowerModeGet(void);
//*****************************************************************************
//
//! \brief Set sector protection.
//!
//! This function will set the specified protection on specified flash bank
//! sector. A sector can either have no protection or have write protection
//! which guards for both program and erase of that sector.
//! Sector protection can only be changed from \ref FLASH_NO_PROTECT to
//! \ref FLASH_WRITE_PROTECT! After write protecting a sector this sector can
//! only be set back to unprotected by a device reset.
//!
//! \param ui32SectorAddress is the start address of the sector to protect.
//! \param ui32ProtectMode is the enumerated sector protection mode.
//! - \ref FLASH_NO_PROTECT
//! - \ref FLASH_WRITE_PROTECT
//!
//! \return None
//
//*****************************************************************************
extern void FlashProtectionSet(uint32_t ui32SectorAddress,
uint32_t ui32ProtectMode);
//*****************************************************************************
//
//! \brief Get sector protection.
//!
//! This return the protection mode for the specified flash bank sector.
//!
//! \param ui32SectorAddress is the start address of the desired sector.
//!
//! \return Returns the sector protection:
//! - \ref FLASH_NO_PROTECT
//! - \ref FLASH_WRITE_PROTECT
//
//*****************************************************************************
extern uint32_t FlashProtectionGet(uint32_t ui32SectorAddress);
//*****************************************************************************
//
//! \brief Save sector protection to make it permanent.
//!
//! This function will save the current protection mode for the specified
//! flash bank sector.
//!
//! This function must only be executed from ROM or SRAM.
//!
//! \note A write protected sector will become permanent write
//! protected!! A device reset will not change the write protection!
//!
//! \param ui32SectorAddress is the start address of the sector to be protected.
//!
//! \return Returns the status of the sector protection:
//! - \ref FAPI_STATUS_SUCCESS : Success.
//! - \ref FAPI_STATUS_FSM_ERROR : An erase error is encountered.
//
//*****************************************************************************
extern uint32_t FlashProtectionSave(uint32_t ui32SectorAddress);
//*****************************************************************************
//
//! \brief Checks if the Flash state machine has detected an error.
//!
//! This function returns the status of the Flash State Machine indicating if
//! an error is detected or not. Primary use is to check if an Erase or
//! Program operation has failed.
//!
//! \note Please note that code can not execute in flash while any part of the flash
//! is being programmed or erased. This function must be called from ROM or
//! SRAM while any part of the flash is being programmed or erased.
//!
//! \return Returns status of Flash state machine:
//! - \ref FAPI_STATUS_FSM_ERROR
//! - \ref FAPI_STATUS_SUCCESS
//
//*****************************************************************************
__STATIC_INLINE uint32_t
FlashCheckFsmForError(void)
{
if(HWREG(FLASH_BASE + FLASH_O_FMSTAT) & FLASH_FMSTAT_CSTAT)
{
return(FAPI_STATUS_FSM_ERROR);
}
else
{
return(FAPI_STATUS_SUCCESS);
}
}
//*****************************************************************************
//
//! \brief Checks if the Flash state machine is ready.
//!
//! This function returns the status of the Flash State Machine indicating if
//! it is ready to accept a new command or not. Primary use is to check if an
//! Erase or Program operation has finished.
//!
//! \note Please note that code can not execute in flash while any part of the flash
//! is being programmed or erased. This function must be called from ROM or
//! SRAMh while any part of the flash is being programmed or erased.
//!
//! \return Returns readiness status of Flash state machine:
//! - \ref FAPI_STATUS_FSM_READY
//! - \ref FAPI_STATUS_FSM_BUSY
//
//*****************************************************************************
__STATIC_INLINE uint32_t
FlashCheckFsmForReady(void)
{
if(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_BUSY)
{
return(FAPI_STATUS_FSM_BUSY);
}
else
{
return(FAPI_STATUS_FSM_READY);
}
}
//*****************************************************************************
//
//! \brief Registers an interrupt handler for the flash interrupt in the dynamic interrupt table.
//!
//! \note Only use this function if you want to use the dynamic vector table (in SRAM)!
//!
//! This function registers a function as the interrupt handler for a specific
//! interrupt and enables the corresponding interrupt in the interrupt controller.
//!
//! Specific FLASH interrupts must be enabled via \ref FlashIntEnable(). It is the
//! interrupt handler's responsibility to clear the interrupt source.
//!
//! \param pfnHandler is a pointer to the function to be called when the flash
//! interrupt occurs.
//!
//! \return None
//!
//! \sa \ref IntRegister() for important information about registering interrupt
//! handlers.
//
//*****************************************************************************
__STATIC_INLINE void
FlashIntRegister(void (*pfnHandler)(void))
{
// Register the interrupt handler.
IntRegister(INT_FLASH, pfnHandler);
// Enable the flash interrupt.
IntEnable(INT_FLASH);
}
//*****************************************************************************
//
//! \brief Unregisters the interrupt handler for the flash interrupt in the dynamic interrupt table.
//!
//! This function does the actual unregistering of the interrupt handler. It
//! clears the handler to be called when a FLASH interrupt occurs. This
//! function also masks off the interrupt in the interrupt controller so that
//! the interrupt handler no longer is called.
//!
//! \return None
//!
//! \sa \ref IntRegister() for important information about registering interrupt
//! handlers.
//
//*****************************************************************************
__STATIC_INLINE void
FlashIntUnregister(void)
{
// Disable the interrupts.
IntDisable(INT_FLASH);
// Unregister the interrupt handler.
IntUnregister(INT_FLASH);
}
//*****************************************************************************
//
//! \brief Enables flash controller interrupt sources.
//!
//! This function enables the flash controller interrupt sources.
//!
//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
//! The parameter is the bitwise OR of any of the following:
//! - \ref FLASH_INT_FSM_DONE : FSM Done interrupt.
//! - \ref FLASH_INT_RV : Read verify error interrupt.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
FlashIntEnable(uint32_t ui32IntFlags)
{
HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= ui32IntFlags;
HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
}
//*****************************************************************************
//
//! \brief Disables individual flash controller interrupt sources.
//!
//! This function disables the flash controller interrupt sources.
//!
//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled.
//! The parameter is the bitwise OR of any of the following:
//! - \ref FLASH_INT_FSM_DONE : FSM Done interrupt.
//! - \ref FLASH_INT_RV : Read verify error interrupt.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
FlashIntDisable(uint32_t ui32IntFlags)
{
HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~ui32IntFlags;
HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
}
//*****************************************************************************
//
//! \brief Gets the current interrupt status.
//!
//! This function returns the interrupt status for the Flash.
//!
//! \return Returns the current interrupt status as values described in
//! \ref FlashIntEnable().
//
//*****************************************************************************
__STATIC_INLINE uint32_t
FlashIntStatus(void)
{
uint32_t ui32IntFlags;
ui32IntFlags = 0;
// Check if FSM_DONE interrupt status is set.
if(HWREG(FLASH_BASE + FLASH_O_FEDACSTAT) & FLASH_FEDACSTAT_FSM_DONE)
{
ui32IntFlags = FLASH_INT_FSM_DONE;
}
// Check if RVF_INT interrupt status is set.
if(HWREG(FLASH_BASE + FLASH_O_FEDACSTAT) & FLASH_FEDACSTAT_RVF_INT)
{
ui32IntFlags |= FLASH_INT_RV;
}
return(ui32IntFlags);
}
//*****************************************************************************
//
//! \brief Clears flash controller interrupt source.
//!
//! The flash controller interrupt source is cleared, so that it no longer
//! asserts. This must be done in the interrupt handler to keep it from being
//! called again immediately upon exit.
//!
//! \note Due to write buffers and synchronizers in the system it may take several
//! clock cycles from a register write clearing an event in a module and until the
//! event is actually cleared in the NVIC of the system CPU. It is recommended to
//! clear the event source early in the interrupt service routine (ISR) to allow
//! the event clear to propagate to the NVIC before returning from the ISR.
//! At the same time, an early event clear allows new events of the same type to be
//! pended instead of ignored if the event is cleared later in the ISR.
//! It is the responsibility of the programmer to make sure that enough time has passed
//! before returning from the ISR to avoid false re-triggering of the cleared event.
//! A simple, although not necessarily optimal, way of clearing an event before
//! returning from the ISR is:
//! -# Write to clear event (interrupt source). (buffered write)
//! -# Dummy read from the event source module. (making sure the write has propagated)
//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers)
//!
//! \param ui32IntFlags is the bit mask of the interrupt sources to be cleared.
//! Can be any of:
//! - \ref FLASH_INT_FSM_DONE
//! - \ref FLASH_INT_RV
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
FlashIntClear(uint32_t ui32IntFlags)
{
uint32_t ui32TempVal;
ui32TempVal = 0;
if(ui32IntFlags & FLASH_INT_FSM_DONE)
{
ui32TempVal = FLASH_FEDACSTAT_FSM_DONE;
}
if(ui32IntFlags & FLASH_INT_RV)
{
ui32TempVal |= FLASH_FEDACSTAT_RVF_INT;
}
// Clear the flash interrupt source.
HWREG(FLASH_BASE + FLASH_O_FEDACSTAT) = ui32TempVal;
}
//*****************************************************************************
//
//! \brief Erase a flash sector.
//!
//! This function will erase the specified flash sector. The function will
//! not return until the flash sector has been erased or an error condition
//! occurred. If flash top sector is erased the function will program the
//! the device security data bytes with default values. The device security
//! data located in the customer configuration area of the flash top sector,
//! must have valid values at all times. These values affect the configuration
//! of the device during boot.
//!
//! \warning Please note that code can not execute in flash while any part of the flash
//! is being programmed or erased. The application must disable interrupts that have
//! interrupt routines in flash. This function calls a ROM function which handles the
//! actual program operation.
//!
//! \param ui32SectorAddress is the starting address in flash of the sector to be
//! erased.
//!
//! \return Returns the status of the sector erase:
//! - \ref FAPI_STATUS_SUCCESS : Success.
//! - \ref FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH : Invalid argument.
//! - \ref FAPI_STATUS_FSM_ERROR : A programming error is encountered.
//
//*****************************************************************************
extern uint32_t FlashSectorErase(uint32_t ui32SectorAddress);
//*****************************************************************************
//
//! \brief Programs unprotected flash sectors in the main bank.
//!
//! This function programs a sequence of bytes into the on-chip flash.
//! Programming each location consists of the result of an AND operation
//! of the new data and the existing data; in other words bits that contain
//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed
//! to 1. Therefore, a byte can be programmed multiple times as long as these
//! rules are followed; if a program operation attempts to change a 0 bit to
//! a 1 bit, that bit will not have its value changed.
//!
//! This function does not return until the data has been programmed or a
//! programming error occurs.
//!
//! \note It is recommended to disable cache and line buffer before programming the
//! flash. Cache and line buffer are not automatically updated if a flash program
//! causes a mismatch between new flash content and old content in cache and
//! line buffer. Remember to enable cache and line buffer when the program
//! operation completes. See \ref VIMSModeSafeSet(), \ref VIMSLineBufDisable(),
//! and \ref VIMSLineBufEnable() for more information.
//!
//! \warning Please note that code can not execute in flash while any part of the flash
//! is being programmed or erased. The application must disable interrupts that have
//! interrupt routines in flash. This function calls a ROM function which handles the
//! actual program operation.
//!
//! The \c pui8DataBuffer pointer can not point to flash.
//!
//! \param pui8DataBuffer is a pointer to the data to be programmed.
//! \param ui32Address is the starting address in flash to be programmed.
//! \param ui32Count is the number of bytes to be programmed.
//!
//! \return Returns status of the flash programming:
//! - \ref FAPI_STATUS_SUCCESS : Success.
//! - \ref FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH : Too many bytes were requested.
//! - \ref FAPI_STATUS_FSM_ERROR : A programming error is encountered.
//
//*****************************************************************************
extern uint32_t FlashProgram(uint8_t *pui8DataBuffer,
uint32_t ui32Address, uint32_t ui32Count);
//*****************************************************************************
//
//! \brief Reads efuse data from specified row.
//!
//! This function will read one efuse row.
//! It is assumed that any previous efuse operation has finished.
//!
//! \param pui32EfuseData is pointer to variable to be updated with efuse data.
//! \param ui32RowAddress is the efuse row number to be read. First row is row
//! number 0.
//!
//! \return Returns the status of the efuse read operation.
//! - \c false : OK status.
//! - \c true : Error status
//
//*****************************************************************************
extern bool FlashEfuseReadRow(uint32_t *pui32EfuseData,
uint32_t ui32RowAddress);
//*****************************************************************************
//
//! \brief Disables all sectors for erase and programming on the active bank.
//!
//! This function disables all sectors for erase and programming on the active
//! bank and enables the Idle Reading Power reduction mode if no low power
//! mode is configured. Furthermore, an additional level of protection from
//! erase is enabled.
//!
//! \note Please note that code can not execute in flash while any part of the flash
//! is being programmed or erased.
//!
//! \return None
//
//*****************************************************************************
extern void FlashDisableSectorsForWrite(void);
//*****************************************************************************
//
// Support for DriverLib in ROM:
// Redirect to implementation in ROM when available.
//
//*****************************************************************************
#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
#include "../driverlib/rom.h"
#ifdef ROM_FlashPowerModeSet
#undef FlashPowerModeSet
#define FlashPowerModeSet ROM_FlashPowerModeSet
#endif
#ifdef ROM_FlashPowerModeGet
#undef FlashPowerModeGet
#define FlashPowerModeGet ROM_FlashPowerModeGet
#endif
#ifdef ROM_FlashProtectionSet
#undef FlashProtectionSet
#define FlashProtectionSet ROM_FlashProtectionSet
#endif
#ifdef ROM_FlashProtectionGet
#undef FlashProtectionGet
#define FlashProtectionGet ROM_FlashProtectionGet
#endif
#ifdef ROM_FlashProtectionSave
#undef FlashProtectionSave
#define FlashProtectionSave ROM_FlashProtectionSave
#endif
#ifdef ROM_FlashSectorErase
#undef FlashSectorErase
#define FlashSectorErase ROM_FlashSectorErase
#endif
#ifdef ROM_FlashProgram
#undef FlashProgram
#define FlashProgram ROM_FlashProgram
#endif
#ifdef ROM_FlashEfuseReadRow
#undef FlashEfuseReadRow
#define FlashEfuseReadRow ROM_FlashEfuseReadRow
#endif
#ifdef ROM_FlashDisableSectorsForWrite
#undef FlashDisableSectorsForWrite
#define FlashDisableSectorsForWrite ROM_FlashDisableSectorsForWrite
#endif
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __FLASH_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

41
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@ -1,41 +0,0 @@
/******************************************************************************
* Filename: gpio.c
* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016)
* Revision: 47179
*
* Description: Driver for the GPIO
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "gpio.h"
// see gpio.h for implementation

643
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View file

@ -1,643 +0,0 @@
/******************************************************************************
* Filename: gpio.h
* Revised: 2018-05-02 11:11:40 +0200 (Wed, 02 May 2018)
* Revision: 51951
*
* Description: Defines and prototypes for the GPIO.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup peripheral_group
//! @{
//! \addtogroup gpio_api
//! @{
//
//*****************************************************************************
#ifndef __GPIO_H__
#define __GPIO_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
#include "../inc/hw_types.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_gpio.h"
#include "debug.h"
//*****************************************************************************
//
// Check for legal range of variable dioNumber
//
//*****************************************************************************
#ifdef DRIVERLIB_DEBUG
#include "../inc/hw_fcfg1.h"
#include "chipinfo.h"
static bool
dioNumberLegal( uint32_t dioNumber )
{
uint32_t ioCount =
(( HWREG( FCFG1_BASE + FCFG1_O_IOCONF ) &
FCFG1_IOCONF_GPIO_CNT_M ) >>
FCFG1_IOCONF_GPIO_CNT_S ) ;
// CC13x2 + CC26x2
if ( ChipInfo_ChipFamilyIs_CC13x2_CC26x2() )
{
return ( (dioNumber >= (31 - ioCount)) && (dioNumber < 31) )
}
// Special handling of CC13x0 7x7, where IO_CNT = 30 and legal range is 1..30
// for all other chips legal range is 0..(dioNumber-1)
else if (( ioCount == 30 ) && ChipInfo_ChipFamilyIs_CC13x0() )
{
return (( dioNumber > 0 ) && ( dioNumber <= ioCount ));
}
else
{
return ( dioNumber < ioCount );
}
}
#endif
//*****************************************************************************
//
// The following values define the bit field for the GPIO DIOs.
//
//*****************************************************************************
#define GPIO_DIO_0_MASK 0x00000001 // GPIO DIO 0 mask
#define GPIO_DIO_1_MASK 0x00000002 // GPIO DIO 1 mask
#define GPIO_DIO_2_MASK 0x00000004 // GPIO DIO 2 mask
#define GPIO_DIO_3_MASK 0x00000008 // GPIO DIO 3 mask
#define GPIO_DIO_4_MASK 0x00000010 // GPIO DIO 4 mask
#define GPIO_DIO_5_MASK 0x00000020 // GPIO DIO 5 mask
#define GPIO_DIO_6_MASK 0x00000040 // GPIO DIO 6 mask
#define GPIO_DIO_7_MASK 0x00000080 // GPIO DIO 7 mask
#define GPIO_DIO_8_MASK 0x00000100 // GPIO DIO 8 mask
#define GPIO_DIO_9_MASK 0x00000200 // GPIO DIO 9 mask
#define GPIO_DIO_10_MASK 0x00000400 // GPIO DIO 10 mask
#define GPIO_DIO_11_MASK 0x00000800 // GPIO DIO 11 mask
#define GPIO_DIO_12_MASK 0x00001000 // GPIO DIO 12 mask
#define GPIO_DIO_13_MASK 0x00002000 // GPIO DIO 13 mask
#define GPIO_DIO_14_MASK 0x00004000 // GPIO DIO 14 mask
#define GPIO_DIO_15_MASK 0x00008000 // GPIO DIO 15 mask
#define GPIO_DIO_16_MASK 0x00010000 // GPIO DIO 16 mask
#define GPIO_DIO_17_MASK 0x00020000 // GPIO DIO 17 mask
#define GPIO_DIO_18_MASK 0x00040000 // GPIO DIO 18 mask
#define GPIO_DIO_19_MASK 0x00080000 // GPIO DIO 19 mask
#define GPIO_DIO_20_MASK 0x00100000 // GPIO DIO 20 mask
#define GPIO_DIO_21_MASK 0x00200000 // GPIO DIO 21 mask
#define GPIO_DIO_22_MASK 0x00400000 // GPIO DIO 22 mask
#define GPIO_DIO_23_MASK 0x00800000 // GPIO DIO 23 mask
#define GPIO_DIO_24_MASK 0x01000000 // GPIO DIO 24 mask
#define GPIO_DIO_25_MASK 0x02000000 // GPIO DIO 25 mask
#define GPIO_DIO_26_MASK 0x04000000 // GPIO DIO 26 mask
#define GPIO_DIO_27_MASK 0x08000000 // GPIO DIO 27 mask
#define GPIO_DIO_28_MASK 0x10000000 // GPIO DIO 28 mask
#define GPIO_DIO_29_MASK 0x20000000 // GPIO DIO 29 mask
#define GPIO_DIO_30_MASK 0x40000000 // GPIO DIO 30 mask
#define GPIO_DIO_31_MASK 0x80000000 // GPIO DIO 31 mask
#define GPIO_DIO_ALL_MASK 0xFFFFFFFF // GPIO all DIOs mask
//*****************************************************************************
//
// Define constants that shall be passed as the outputEnableValue parameter to
// GPIO_setOutputEnableDio() and will be returned from the function
// GPIO_getOutputEnableDio().
//
//*****************************************************************************
#define GPIO_OUTPUT_DISABLE 0x00000000 // DIO output is disabled
#define GPIO_OUTPUT_ENABLE 0x00000001 // DIO output is enabled
//*****************************************************************************
//
// API Functions and prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Reads a specific DIO.
//!
//! \param dioNumber specifies the DIO to read (0-31).
//!
//! \return Returns 0 or 1 reflecting the input value of the specified DIO.
//!
//! \sa \ref GPIO_readMultiDio(), \ref GPIO_writeDio(), \ref GPIO_writeMultiDio()
//
//*****************************************************************************
__STATIC_INLINE uint32_t
GPIO_readDio( uint32_t dioNumber )
{
// Check the arguments.
ASSERT( dioNumberLegal( dioNumber ));
// Return the input value from the specified DIO.
return (( HWREG( GPIO_BASE + GPIO_O_DIN31_0 ) >> dioNumber ) & 1 );
}
//*****************************************************************************
//
//! \brief Reads the input value for the specified DIOs.
//!
//! This function returns the input value for multiple DIOs.
//! The value returned is not shifted and hence matches the corresponding dioMask bits.
//!
//! \param dioMask is the bit-mask representation of the DIOs to read.
//! The parameter must be a bitwise OR'ed combination of the following:
//! - \ref GPIO_DIO_0_MASK
//! - ...
//! - \ref GPIO_DIO_31_MASK
//!
//! \return Returns a bit vector reflecting the input value of the corresponding DIOs.
//! - 0 : Corresponding DIO is low.
//! - 1 : Corresponding DIO is high.
//!
//! \sa \ref GPIO_readDio(), \ref GPIO_writeDio(), \ref GPIO_writeMultiDio()
//
//*****************************************************************************
__STATIC_INLINE uint32_t
GPIO_readMultiDio( uint32_t dioMask )
{
// Check the arguments.
ASSERT( dioMask & GPIO_DIO_ALL_MASK );
// Return the input value from the specified DIOs.
return ( HWREG( GPIO_BASE + GPIO_O_DIN31_0 ) & dioMask );
}
//*****************************************************************************
//
//! \brief Writes a value to a specific DIO.
//!
//! \param dioNumber specifies the DIO to update (0-31).
//! \param value specifies the value to write
//! - 0 : Logic zero (low)
//! - 1 : Logic one (high)
//!
//! \return None
//!
//! \sa \ref GPIO_writeMultiDio(), \ref GPIO_readDio(), \ref GPIO_readMultiDio()
//
//*****************************************************************************
__STATIC_INLINE void
GPIO_writeDio( uint32_t dioNumber, uint32_t value )
{
// Check the arguments.
ASSERT( dioNumberLegal( dioNumber ));
ASSERT(( value == 0 ) || ( value == 1 ));
// Write 0 or 1 to the byte indexed DOUT map
HWREGB( GPIO_BASE + dioNumber ) = value;
}
//*****************************************************************************
//
//! \brief Writes masked data to the specified DIOs.
//!
//! Enables for writing multiple bits simultaneously.
//! The value to write must be shifted so it matches the corresponding dioMask bits.
//!
//! \note Note that this is a read-modify-write operation and hence not atomic.
//!
//! \param dioMask is the bit-mask representation of the DIOs to write.
//! The parameter must be a bitwise OR'ed combination of the following:
//! - \ref GPIO_DIO_0_MASK
//! - ...
//! - \ref GPIO_DIO_31_MASK
//! \param bitVectoredValue holds the value to be written to the corresponding DIO-bits.
//!
//! \return None
//!
//! \sa \ref GPIO_writeDio(), \ref GPIO_readDio(), \ref GPIO_readMultiDio()
//
//*****************************************************************************
__STATIC_INLINE void
GPIO_writeMultiDio( uint32_t dioMask, uint32_t bitVectoredValue )
{
// Check the arguments.
ASSERT( dioMask & GPIO_DIO_ALL_MASK );
HWREG( GPIO_BASE + GPIO_O_DOUT31_0 ) =
( HWREG( GPIO_BASE + GPIO_O_DOUT31_0 ) & ~dioMask ) |
( bitVectoredValue & dioMask );
}
//*****************************************************************************
//
//! \brief Sets a specific DIO to 1 (high).
//!
//! \param dioNumber specifies the DIO to set (0-31).
//!
//! \return None
//!
//! \sa \ref GPIO_setMultiDio(), \ref GPIO_clearDio(), \ref GPIO_clearMultiDio()
//
//*****************************************************************************
__STATIC_INLINE void
GPIO_setDio( uint32_t dioNumber )
{
// Check the arguments.
ASSERT( dioNumberLegal( dioNumber ));
// Set the specified DIO.
HWREG( GPIO_BASE + GPIO_O_DOUTSET31_0 ) = ( 1 << dioNumber );
}
//*****************************************************************************
//
//! \brief Sets the specified DIOs to 1 (high).
//!
//! \param dioMask is the bit-mask representation of the DIOs to set.
//! The parameter must be a bitwise OR'ed combination of the following:
//! - \ref GPIO_DIO_0_MASK
//! - ...
//! - \ref GPIO_DIO_31_MASK
//!
//! \return None
//!
//! \sa \ref GPIO_setDio(), \ref GPIO_clearDio(), \ref GPIO_clearMultiDio()
//
//*****************************************************************************
__STATIC_INLINE void
GPIO_setMultiDio( uint32_t dioMask )
{
// Check the arguments.
ASSERT( dioMask & GPIO_DIO_ALL_MASK );
// Set the DIOs.
HWREG( GPIO_BASE + GPIO_O_DOUTSET31_0 ) = dioMask;
}
//*****************************************************************************
//
//! \brief Clears a specific DIO to 0 (low).
//!
//! \param dioNumber specifies the DIO to clear (0-31).
//!
//! \return None
//!
//! \sa \ref GPIO_clearMultiDio(), \ref GPIO_setDio(), \ref GPIO_setMultiDio()
//
//*****************************************************************************
__STATIC_INLINE void
GPIO_clearDio( uint32_t dioNumber )
{
// Check the arguments.
ASSERT( dioNumberLegal( dioNumber ));
// Clear the specified DIO.
HWREG( GPIO_BASE + GPIO_O_DOUTCLR31_0 ) = ( 1 << dioNumber );
}
//*****************************************************************************
//
//! \brief Clears the specified DIOs to 0 (low).
//!
//! \param dioMask is the bit-mask representation of the DIOs to clear.
//! The parameter must be a bitwise OR'ed combination of the following:
//! - \ref GPIO_DIO_0_MASK
//! - ...
//! - \ref GPIO_DIO_31_MASK
//!
//! \return None
//!
//! \sa \ref GPIO_clearDio(), \ref GPIO_setDio(), \ref GPIO_setMultiDio()
//
//*****************************************************************************
__STATIC_INLINE void
GPIO_clearMultiDio( uint32_t dioMask )
{
// Check the arguments.
ASSERT( dioMask & GPIO_DIO_ALL_MASK );
// Clear the DIOs.
HWREG( GPIO_BASE + GPIO_O_DOUTCLR31_0 ) = dioMask;
}
//*****************************************************************************
//
//! \brief Toggles a specific DIO.
//!
//! \param dioNumber specifies the DIO to toggle (0-31).
//!
//! \return None
//!
//! \sa \ref GPIO_toggleMultiDio()
//
//*****************************************************************************
__STATIC_INLINE void
GPIO_toggleDio( uint32_t dioNumber )
{
// Check the arguments.
ASSERT( dioNumberLegal( dioNumber ));
// Toggle the specified DIO.
HWREG( GPIO_BASE + GPIO_O_DOUTTGL31_0 ) = ( 1 << dioNumber );
}
//*****************************************************************************
//
//! \brief Toggles the specified DIOs.
//!
//! \param dioMask is the bit-mask representation of the DIOs to toggle.
//! The parameter must be a bitwise OR'ed combination of the following:
//! - \ref GPIO_DIO_0_MASK
//! - ...
//! - \ref GPIO_DIO_31_MASK
//!
//! \return None
//!
//! \sa \ref GPIO_toggleDio()
//
//*****************************************************************************
__STATIC_INLINE void
GPIO_toggleMultiDio( uint32_t dioMask )
{
// Check the arguments.
ASSERT( dioMask & GPIO_DIO_ALL_MASK );
// Toggle the DIOs.
HWREG( GPIO_BASE + GPIO_O_DOUTTGL31_0 ) = dioMask;
}
//*****************************************************************************
//
//! \brief Gets the output enable status of a specific DIO.
//!
//! This function returns the output enable status for the specified DIO.
//! The DIO can be configured as either input or output under software control.
//!
//! \param dioNumber specifies the DIO to get the output enable setting from (0-31).
//!
//! \return Returns one of the enumerated data types (0 or 1):
//! - \ref GPIO_OUTPUT_DISABLE : DIO output is disabled.
//! - \ref GPIO_OUTPUT_ENABLE : DIO output is enabled.
//!
//! \sa \ref GPIO_getOutputEnableMultiDio(), \ref GPIO_setOutputEnableDio(), \ref GPIO_setOutputEnableMultiDio()
//
//*****************************************************************************
__STATIC_INLINE uint32_t
GPIO_getOutputEnableDio( uint32_t dioNumber )
{
// Check the arguments.
ASSERT( dioNumberLegal( dioNumber ));
// Return the output enable status for the specified DIO.
return (( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) >> dioNumber ) & 1 );
}
//*****************************************************************************
//
//! \brief Gets the output enable setting of the specified DIOs.
//!
//! This function returns the output enable setting for multiple DIOs.
//! The value returned is not shifted and hence matches the corresponding dioMask bits.
//!
//! \param dioMask is the bit-mask representation of the DIOs to return the output enable settings from.
//! The parameter must be a bitwise OR'ed combination of the following:
//! - \ref GPIO_DIO_0_MASK
//! - ...
//! - \ref GPIO_DIO_31_MASK
//!
//! \return Returns the output enable setting for multiple DIOs as a bit vector corresponding to the dioMask bits.
//! - 0 : Corresponding DIO is configured with output disabled.
//! - 1 : Corresponding DIO is configured with output enabled.
//!
//! \sa \ref GPIO_getOutputEnableDio(), \ref GPIO_setOutputEnableDio(), \ref GPIO_setOutputEnableMultiDio()
//
//*****************************************************************************
__STATIC_INLINE uint32_t
GPIO_getOutputEnableMultiDio( uint32_t dioMask )
{
// Check the arguments.
ASSERT( dioMask & GPIO_DIO_ALL_MASK );
// Return the output enable value for the specified DIOs.
return ( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) & dioMask );
}
//*****************************************************************************
//
//! \brief Sets output enable of a specific DIO.
//!
//! This function sets the GPIO output enable bit for the specified DIO.
//! The DIO can be configured as either input or output under software control.
//!
//! \param dioNumber specifies the DIO to configure (0-31).
//! \param outputEnableValue specifies the output enable setting of the specified DIO:
//! - \ref GPIO_OUTPUT_DISABLE : DIO output is disabled.
//! - \ref GPIO_OUTPUT_ENABLE : DIO output is enabled.
//!
//! \return None
//!
//! \sa \ref GPIO_setOutputEnableMultiDio(), \ref GPIO_getOutputEnableDio(), \ref GPIO_getOutputEnableMultiDio()
//
//*****************************************************************************
__STATIC_INLINE void
GPIO_setOutputEnableDio( uint32_t dioNumber, uint32_t outputEnableValue )
{
// Check the arguments.
ASSERT( dioNumberLegal( dioNumber ));
ASSERT(( outputEnableValue == GPIO_OUTPUT_DISABLE ) ||
( outputEnableValue == GPIO_OUTPUT_ENABLE ) );
// Update the output enable bit for the specified DIO.
HWREGBITW( GPIO_BASE + GPIO_O_DOE31_0, dioNumber ) = outputEnableValue;
}
//*****************************************************************************
//
//! \brief Configures the output enable setting for all specified DIOs.
//!
//! This function configures the output enable setting for the specified DIOs.
//! The output enable setting must be shifted so it matches the corresponding dioMask bits.
//! The DIOs can be configured as either an input or output under software control.
//!
//! \note Note that this is a read-modify-write operation and hence not atomic.
//!
//! \param dioMask is the bit-mask representation of the DIOs on which to configure the
//! output enable setting. The parameter must be a bitwise OR'ed combination of the following:
//! - \ref GPIO_DIO_0_MASK
//! - ...
//! - \ref GPIO_DIO_31_MASK
//! \param bitVectoredOutputEnable holds the output enable setting the corresponding DIO-bits:
//! - 0 : Corresponding DIO is configured with output disabled.
//! - 1 : Corresponding DIO is configured with output enabled.
//!
//! \return None
//!
//! \sa \ref GPIO_setOutputEnableDio(), \ref GPIO_getOutputEnableDio(), \ref GPIO_getOutputEnableMultiDio()
//
//*****************************************************************************
__STATIC_INLINE void
GPIO_setOutputEnableMultiDio( uint32_t dioMask, uint32_t bitVectoredOutputEnable )
{
// Check the arguments.
ASSERT( dioMask & GPIO_DIO_ALL_MASK );
HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) =
( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) & ~dioMask ) |
( bitVectoredOutputEnable & dioMask );
}
//*****************************************************************************
//
//! \brief Gets the event status of a specific DIO.
//!
//! \param dioNumber specifies the DIO to get the event status from (0-31).
//!
//! \return Returns the current event status on the specified DIO.
//! - 0 : Non-triggered event.
//! - 1 : Triggered event.
//!
//! \sa \ref GPIO_getEventMultiDio(), \ref GPIO_clearEventDio(), \ref GPIO_clearEventMultiDio()
//
//*****************************************************************************
__STATIC_INLINE uint32_t
GPIO_getEventDio( uint32_t dioNumber )
{
// Check the arguments.
ASSERT( dioNumberLegal( dioNumber ));
// Return the event status for the specified DIO.
return (( HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) >> dioNumber ) & 1 );
}
//*****************************************************************************
//
//! \brief Gets the event status of the specified DIOs.
//!
//! This function returns the event status for multiple DIOs.
//! The value returned is not shifted and hence matches the corresponding dioMask bits.
//!
//! \param dioMask is the bit-mask representation of the DIOs to get the
//! event status from (0-31).
//! The parameter must be a bitwise OR'ed combination of the following:
//! - \ref GPIO_DIO_0_MASK
//! - ...
//! - \ref GPIO_DIO_31_MASK
//!
//! \return Returns a bit vector with the current event status corresponding to the specified DIOs.
//! - 0 : Corresponding DIO has no triggered event.
//! - 1 : Corresponding DIO has a triggered event.
//!
//! \sa \ref GPIO_getEventDio(), \ref GPIO_clearEventDio(), \ref GPIO_clearEventMultiDio()
//
//*****************************************************************************
__STATIC_INLINE uint32_t
GPIO_getEventMultiDio( uint32_t dioMask )
{
// Check the arguments.
ASSERT( dioMask & GPIO_DIO_ALL_MASK );
// Return the event status for the specified DIO.
return ( HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) & dioMask );
}
//*****************************************************************************
//
//! \brief Clears the IO event status of a specific DIO.
//!
//! \param dioNumber specifies the DIO on which to clear the event status (0-31).
//!
//! \return None
//!
//! \sa \ref GPIO_clearEventMultiDio(), \ref GPIO_getEventDio(), \ref GPIO_getEventMultiDio()
//
//*****************************************************************************
__STATIC_INLINE void
GPIO_clearEventDio( uint32_t dioNumber )
{
// Check the arguments.
ASSERT( dioNumberLegal( dioNumber ));
// Clear the event status for the specified DIO.
HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) = ( 1 << dioNumber );
}
//*****************************************************************************
//
//! \brief Clears the IO event status on the specified DIOs.
//!
//! \param dioMask is the bit-mask representation of the DIOs on which to
//! clear the events status.
//! The parameter must be a bitwise OR'ed combination of the following:
//! - \ref GPIO_DIO_0_MASK
//! - ...
//! - \ref GPIO_DIO_31_MASK
//!
//! \return None
//!
//! \sa \ref GPIO_clearEventDio(), \ref GPIO_getEventDio(), \ref GPIO_getEventMultiDio()
//
//*****************************************************************************
__STATIC_INLINE void
GPIO_clearEventMultiDio( uint32_t dioMask )
{
// Check the arguments.
ASSERT( dioMask & GPIO_DIO_ALL_MASK );
// Clear the event status for the specified DIOs.
HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) = dioMask;
}
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __GPIO_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

90
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@ -1,90 +0,0 @@
/******************************************************************************
* Filename: gpio_doc.h
* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016)
* Revision: 45971
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//! \addtogroup gpio_api
//! @{
//! \section sec_gpio Introduction
//!
//! The GPIO module allows software to control the pins of the device directly if the IOC module has
//! been configured to route the GPIO signal to a physical pin (called DIO). Alternatively, pins can
//! be hardware controlled by other peripheral modules. For more information about the IOC module,
//! how to configure physical pins, and how to select between software controlled and hardware controlled,
//! see the [IOC API](\ref ioc_api).
//!
//! The System CPU can access the GPIO module to read the value of any DIO of the device and if the IOC
//! module has been configured such that one or more DIOs are GPIO controlled (software controlled) the
//! System CPU can write these DIOs through the GPIO module.
//!
//! The IOC module can also be configured to generate events on edge detection and these events can be
//! read and cleared in the GPIO module by the System CPU.
//!
//! \section sec_gpio_api API
//!
//! The API functions can be grouped like this:
//!
//! Set and get direction of DIO (output enable):
//! - \ref GPIO_setOutputEnableDio()
//! - \ref GPIO_setOutputEnableMultiDio()
//! - \ref GPIO_getOutputEnableDio()
//! - \ref GPIO_getOutputEnableMultiDio()
//!
//! Write DIO (requires IOC to be configured for GPIO usage):
//! - \ref GPIO_writeDio()
//! - \ref GPIO_writeMultiDio()
//!
//! Set, clear, or toggle DIO (requires IOC to be configured for GPIO usage):
//! - \ref GPIO_setDio()
//! - \ref GPIO_setMultiDio()
//! - \ref GPIO_clearDio()
//! - \ref GPIO_clearMultiDio()
//! - \ref GPIO_toggleDio()
//! - \ref GPIO_toggleMultiDio()
//!
//! Read DIO (even if IOC is NOT configured for GPIO usage; however, the DIO must be configured for input enable in IOC):
//! - \ref GPIO_readDio()
//! - \ref GPIO_readMultiDio()
//!
//! Read or clear events (even if IOC is NOT configured for GPIO usage; however, the DIO must be configured for input enable in IOC):
//! - \ref GPIO_getEventDio()
//! - \ref GPIO_getEventMultiDio()
//! - \ref GPIO_clearEventDio()
//! - \ref GPIO_clearEventMultiDio()
//!
//! The [IOC API](\ref ioc_api) provides two functions for easy configuration of DIOs as GPIO enabled using
//! typical settings. They also serve as examples on how to configure the IOC and GPIO modules for GPIO usage:
//! - \ref IOCPinTypeGpioInput()
//! - \ref IOCPinTypeGpioOutput()
//!
//! @}

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@ -1,105 +0,0 @@
/******************************************************************************
* Filename: group_analog_doc.h
* Revised: 2016-08-30 14:34:13 +0200 (Tue, 30 Aug 2016)
* Revision: 47080
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//! \addtogroup analog_group
//! @{
//! \section sec_analog Introduction
//!
//! Access to registers in the analog domain of the device goes through master modules controlling slave
//! modules which contain the actual registers. The master module is located in the digital domain of the
//! device. The interfaces between master and slave modules are called ADI (Analog-to-Digital Interface)
//! and DDI (Digital-to-Digital Interface) depending on the type of module to access and thus the slave
//! modules are referred to as ADI slave and DDI slave.
//!
//! The ADI and DDI APIs provide access to these registers:
//! - <a href="../register_descriptions/ANATOP_MMAP/ADI_2_REFSYS.html" target="_blank">ADI_2_REFSYS</a> : Reference System for generating reference voltages and reference currents.
//! - Reference system control
//! - SOC LDO control
//! - <a href="../register_descriptions/ANATOP_MMAP/ADI_3_REFSYS.html" target="_blank">ADI_3_REFSYS</a> : Reference System for generating reference voltages and reference currents.
//! - Reference system control
//! - DC/DC control
//! - <a href="../register_descriptions/ANATOP_MMAP/ADI_4_AUX.html" target="_blank">ADI_4_AUX</a> : Controlling analog peripherals of AUX.
//! - Multiplexers
//! - Current source
//! - Comparators
//! - ADCs
//! - <a href="../register_descriptions/ANATOP_MMAP/DDI_0_OSC.html" target="_blank">DDI_0_OSC</a> : Controlling the oscillators (via AUX domain)
//!
//! The register descriptions of CPU memory map document the ADI/DDI masters. The register descriptions of
//! analog memory map document the ADI/DDI slaves. The ADI/DDI APIs allow the programmer to focus on the
//! slave registers of interest without being concerned with the ADI/DDI master part of the interface.
//!
//! Although the ADI/DDI APIs make the master "transparent" it can be useful to know a few details about
//! the ADI/DDI protocol and how the master handles transactions as it can affect how the system CPU performs.
//! - ADI protocol uses 8-bit write bus compared to 32-bit write bus in DDI. ADI protocol uses 4-bit read
//! bus compared to 16-bit read bus in DDI. Hence a 32-bit read from an ADI register is translated into 8
//! transactions in the ADI protocol.
//! - One transaction on the ADI/DDI protocol takes several clock cycles for the master to complete.
//! - ADI slave registers are 8-bit wide.
//! - DDI slave registers are 32-bit wide.
//! - ADI/DDI master supports multiple data width accesses seen from the system CPU
//! (however, not all bit width accesses are supported by the APIs):
//! - Read: 8, 16, 32-bit
//! - Write
//! - Direct (write, set, clear): 8, 16, 32-bit
//! - Masked: 4, 8, 16-bit
//!
//! Making posted/buffered writes from the system CPU (default) to the ADI/DDI allows the system CPU to continue
//! while the ADI/DDI master handles the transactions on the ADI/DDI protocol. If using non-posted/non-buffered
//! writes the system CPU will wait for ADI/DDI master to complete the transactions to the slave before continuing
//! execution.
//!
//! Reading from ADI/DDI requires that all transactions on the ADI/DDI protocol have completed before the system CPU
//! receives the response thus the programmer must understand that the response time depends on the number of bytes
//! read. However, due to the 'set', 'clear' and 'masked write' features of the ADI/DDI most writes can be done
//! without the typical read-modify-write sequence thus reducing the need for reads to a minimum.
//!
//! Consequently, if making posted/buffered writes then the written value will not take effect in the
//! analog domain until some point later in time. An alternative to non-posted/non-buffered writes - in order to make
//! sure a written value has taken effect - is to read from the same ADI/DDI as the write as this will keep the system CPU
//! waiting until both the write and the read have completed.
//!
//! \note
//! Do NOT use masked write when writing bit fields spanning the "masked write boundary" i.e. the widest possible
//! masked write that the protocol supports (ADI = 4 bits, DDI = 16 bits). This will put the device into a
//! temporary state - which is potentially harmful to the device - as the bit field will be written over two transactions.
//! Thus to use masked writes:
//! - For ADI the bit field(s) must be within bit 0 to 3 (REG[3:0]) or bit 4 to 7 (REG[7:4]).
//! - For DDI the bit field(s) must be within bit 0 to 15 (REG[15:0]) or bit 16 to 31 (REG[31:16]).
//!
//! \note
//! If masked write is not allowed, a regular read-modify-write is necessary.
//!
//! @}

76
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@ -1,76 +0,0 @@
/******************************************************************************
* Filename: group_aon_doc.h
* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016)
* Revision: 45971
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//! \addtogroup aon_group
//! @{
//! \section sec_aon Introduction
//!
//! The Always-ON (AON) voltage domain contains the AUX power domain, AON power domain, and JTAG power domain.
//! The AON API includes functions to access the AON power domain. For functions accessing the AUX power domain
//! see the [AUX API](@ref aux_group).
//!
//! The AON power domain contains circuitry that is always enabled, except for the shutdown mode
//! (digital supply is off), and the AON power domain is clocked at 32-kHz.
//!
//! The AON API accesses the AON registers through a common module called AON Interface (AON IF) which handles the
//! actual transactions towards the much slower AON registers. Because accessing AON can cause a significant
//! delay in terms of system CPU clock cycles it is important to understand the basics about how the AON IF
//! operates. The following list describes a few of the most relevant properties of the AON IF seen from the system CPU:
//! - \ti_bold{Shadow registers}: The system CPU actually accesses a set of "shadow registers" which are being synchronized to the AON registers
//! by the AON IF every AON clock cycle.
//! - Writing an AON register via AON IF can take up to one AON clock cycle before taking effect in the AON domain. However, the system CPU can
//! continue executing without waiting for this.
//! - The AON IF supports multiple writes within the same AON clock cycle thus several registers/bit fields can be synchronized simultaneously.
//! - Reading from AON IF returns the value from last time the shadow registers were synchronized (if no writes to AON IF have occurred since)
//! thus the value can be up to one AON clock cycle old.
//! - Reading from AON IF after a write (but before synchronization has happened) will return the value from the shadow register
//! and not the last value from the AON register. Thus doing multiple read-modify-writes within one AON clock cycle is supported.
//! - \ti_bold{Read delay}: Due to an asynchronous interface to the AON IF, reading AON registers will generate a few wait cycles thus stalling
//! the system CPU until the read completes. There is no delay on writes to AON IF if using posted/buffered writes.
//! - \ti_bold{Synchronizing}: If it is required that a write to AON takes effect before continuing code execution it is possible to do a conditional "wait for
//! synchronization" by calling \ref SysCtrlAonSync(). This will wait for any pending writes to synchronize.
//! - \ti_bold{Updating}: It is also possible to do an unconditional "wait for synchronization", in case a new read
//! value is required, by calling \ref SysCtrlAonUpdate(). This is typically used after wake-up to make sure the AON IF has been
//! synchronized at least once before reading the values.
//!
//! Below are a few guidelines to write efficient code for AON access based on the properties of the interface to the AON registers.
//! - Avoid synchronizing unless required by the application. If synchronization is needed then try to group/arrange AON writes to
//! minimize the number of required synchronizations.
//! - If modifying several bit fields within a single AON register it is slightly faster to do a single read, modify the bit fields,
//! and then write it back rather than doing multiple independent read-modify-writes (due to the read delay).
//! - Using posted/buffered writes to AON (default) lets the system CPU continue execution immediately. Using non-posted/non-buffered
//! writes will generate a delay similar to a read access.
//!
//! @}

58
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@ -1,58 +0,0 @@
/******************************************************************************
* Filename: group_aux_doc.h
* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016)
* Revision: 45971
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//! \addtogroup aux_group
//! @{
//! \section sec_aux Introduction
//!
//! The AUX is a collective description of all the analog peripherals (ADC, comparators, and current source) and
//! the digital modules in the AUX power domain (AUX_PD) such as the sensor controller, timers, time-to-digital
//! converter, etc. AUX_PD is located within the AON voltage domain of the device.
//!
//! The sensor controller has the ability to
//! do its own power and clock management of AUX_PD, independently of the MCU domain. The sensor
//! controller can also continue doing tasks while the MCU subsystem is powered down, but with limited
//! resources compared to the larger MCU domain.
//!
//! The AUX power domain is connected to the MCU system through an asynchronous interface, ensuring
//! that all modules connected to the AUX bus are accessible from the system CPU.
//! Accessing the analog peripherals from the system CPU must be done by using TI-provided
//! drivers to ensure proper control of power management.
//!
//! \note To ease development of program code running on the sensor controller, TI provides a tool
//! chain for writing software for the controller, Sensor Controller Studio (SCS), which is a fully
//! integrated tool consisting of an IDE, compiler, assembler, and linker.
//!
//! @}

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/******************************************************************************
* Filename: i2c.c
* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017)
* Revision: 48852
*
* Description: Driver for the I2C module
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "i2c.h"
//*****************************************************************************
//
// Handle support for DriverLib in ROM:
// This section will undo prototype renaming made in the header file
//
//*****************************************************************************
#if !defined(DOXYGEN)
#undef I2CMasterInitExpClk
#define I2CMasterInitExpClk NOROM_I2CMasterInitExpClk
#undef I2CMasterErr
#define I2CMasterErr NOROM_I2CMasterErr
#undef I2CIntRegister
#define I2CIntRegister NOROM_I2CIntRegister
#undef I2CIntUnregister
#define I2CIntUnregister NOROM_I2CIntUnregister
#endif
//*****************************************************************************
//
// Initializes the I2C Master block
//
//*****************************************************************************
void
I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk,
bool bFast)
{
uint32_t ui32SCLFreq;
uint32_t ui32TPR;
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
// Must enable the device before doing anything else.
I2CMasterEnable(I2C0_BASE);
// Get the desired SCL speed.
if(bFast == true)
{
ui32SCLFreq = 400000;
}
else
{
ui32SCLFreq = 100000;
}
// Compute the clock divider that achieves the fastest speed less than or
// equal to the desired speed. The numerator is biased to favor a larger
// clock divider so that the resulting clock is always less than or equal
// to the desired clock, never greater.
ui32TPR = ((ui32I2CClk + (2 * 10 * ui32SCLFreq) - 1) / (2 * 10 * ui32SCLFreq)) - 1;
HWREG(I2C0_BASE + I2C_O_MTPR) = ui32TPR;
}
//*****************************************************************************
//
// Gets the error status of the I2C Master module
//
//*****************************************************************************
uint32_t
I2CMasterErr(uint32_t ui32Base)
{
uint32_t ui32Err;
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
// Get the raw error state.
ui32Err = HWREG(I2C0_BASE + I2C_O_MSTAT);
// If the I2C master is busy, then all the other status bits are invalid,
// and there is no error to report.
if(ui32Err & I2C_MSTAT_BUSY)
{
return(I2C_MASTER_ERR_NONE);
}
// Check for errors.
if(ui32Err & (I2C_MSTAT_ERR | I2C_MSTAT_ARBLST))
{
return(ui32Err & (I2C_MSTAT_ARBLST | I2C_MSTAT_DATACK_N | I2C_MSTAT_ADRACK_N));
}
else
{
return(I2C_MASTER_ERR_NONE);
}
}
//*****************************************************************************
//
// Registers an interrupt handler for the I2C module
//
//*****************************************************************************
void
I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
{
uint32_t ui32Int;
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
// Get the interrupt number.
ui32Int = INT_I2C_IRQ;
// Register the interrupt handler, returning an error if an error occurs.
IntRegister(ui32Int, pfnHandler);
// Enable the I2C interrupt.
IntEnable(ui32Int);
}
//*****************************************************************************
//
// Unregisters an interrupt handler for the I2C module
//
//*****************************************************************************
void
I2CIntUnregister(uint32_t ui32Base)
{
uint32_t ui32Int;
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
// Get the interrupt number.
ui32Int = INT_I2C_IRQ;
// Disable the interrupt.
IntDisable(ui32Int);
// Unregister the interrupt handler.
IntUnregister(ui32Int);
}

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/******************************************************************************
* Filename: i2c.h
* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017)
* Revision: 49048
*
* Description: Defines and prototypes for the I2C.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup peripheral_group
//! @{
//! \addtogroup i2c_api
//! @{
//
//*****************************************************************************
#ifndef __I2C_H__
#define __I2C_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdbool.h>
#include <stdint.h>
#include "../inc/hw_types.h"
#include "../inc/hw_ints.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_i2c.h"
#include "../inc/hw_sysctl.h"
#include "debug.h"
#include "interrupt.h"
#include "cpu.h"
//*****************************************************************************
//
// Support for DriverLib in ROM:
// This section renames all functions that are not "static inline", so that
// calling these functions will default to implementation in flash. At the end
// of this file a second renaming will change the defaults to implementation in
// ROM for available functions.
//
// To force use of the implementation in flash, e.g. for debugging:
// - Globally: Define DRIVERLIB_NOROM at project level
// - Per function: Use prefix "NOROM_" when calling the function
//
//*****************************************************************************
#if !defined(DOXYGEN)
#define I2CMasterInitExpClk NOROM_I2CMasterInitExpClk
#define I2CMasterErr NOROM_I2CMasterErr
#define I2CIntRegister NOROM_I2CIntRegister
#define I2CIntUnregister NOROM_I2CIntUnregister
#endif
//*****************************************************************************
//
// I2C Master commands
//
//*****************************************************************************
#define I2C_MASTER_CMD_SINGLE_SEND \
0x00000007
#define I2C_MASTER_CMD_SINGLE_RECEIVE \
0x00000007
#define I2C_MASTER_CMD_BURST_SEND_START \
0x00000003
#define I2C_MASTER_CMD_BURST_SEND_CONT \
0x00000001
#define I2C_MASTER_CMD_BURST_SEND_FINISH \
0x00000005
#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \
0x00000004
#define I2C_MASTER_CMD_BURST_RECEIVE_START \
0x0000000b
#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \
0x00000009
#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \
0x00000005
#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \
0x00000004
//*****************************************************************************
//
// I2C Master error status
//
//*****************************************************************************
#define I2C_MASTER_ERR_NONE 0
#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
#define I2C_MASTER_ERR_DATA_ACK 0x00000008
#define I2C_MASTER_ERR_ARB_LOST 0x00000010
//*****************************************************************************
//
// I2C Slave action requests
//
//*****************************************************************************
#define I2C_SLAVE_ACT_NONE 0
#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data
#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data
#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte
//*****************************************************************************
//
// I2C Slave interrupts
//
//*****************************************************************************
#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt.
#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt.
#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt.
//*****************************************************************************
//
// API Functions and prototypes
//
//*****************************************************************************
#ifdef DRIVERLIB_DEBUG
//*****************************************************************************
//
//! \internal
//!
//! \brief Checks an I2C base address.
//!
//! This function determines if a I2C port base address is valid.
//!
//! \param ui32Base is the base address of the I2C port.
//!
//! \return Returns \c true if the base address is valid and \c false
//! otherwise
//
//*****************************************************************************
static bool
I2CBaseValid(uint32_t ui32Base)
{
return(ui32Base == I2C0_BASE);
}
#endif
//*****************************************************************************
//
//! \brief Initializes the I2C Master block.
//!
//! This function initializes operation of the I2C Master block. Upon
//! successful initialization of the I2C block, this function will have set the
//! bus speed for the master, and will have enabled the I2C Master block.
//!
//! If the parameter \c bFast is \c true, then the master block will be set up
//! to transfer data at 400 kbps; otherwise, it will be set up to transfer data
//! at 100 kbps.
//!
//!
//! \param ui32Base is the base address of the I2C module.
//! \param ui32I2CClk is the rate of the clock supplied to the I2C module.
//! \param bFast set up for fast data transfers.
//!
//! \return None
//
//*****************************************************************************
extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk,
bool bFast);
//*****************************************************************************
//
//! \brief Controls the state of the I2C Master module.
//!
//! This function is used to control the state of the Master module send and
//! receive operations.
//!
//! \param ui32Base is the base address of the I2C module.
//! \param ui32Cmd is the command to be issued by the I2C Master module
//! The parameter can be one of the following values:
//! - \ref I2C_MASTER_CMD_SINGLE_SEND
//! - \ref I2C_MASTER_CMD_SINGLE_RECEIVE
//! - \ref I2C_MASTER_CMD_BURST_SEND_START
//! - \ref I2C_MASTER_CMD_BURST_SEND_CONT
//! - \ref I2C_MASTER_CMD_BURST_SEND_FINISH
//! - \ref I2C_MASTER_CMD_BURST_SEND_ERROR_STOP
//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_START
//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_CONT
//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_FINISH
//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd)
{
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
ASSERT((ui32Cmd == I2C_MASTER_CMD_SINGLE_SEND) ||
// (ui32Cmd == I2C_MASTER_CMD_SINGLE_RECEIVE) || -> Equal to SINGLE_SEND
(ui32Cmd == I2C_MASTER_CMD_BURST_SEND_START) ||
(ui32Cmd == I2C_MASTER_CMD_BURST_SEND_CONT) ||
(ui32Cmd == I2C_MASTER_CMD_BURST_SEND_FINISH) ||
(ui32Cmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) ||
(ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_START) ||
(ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) ||
(ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) ||
(ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP));
// Send the command.
HWREG(I2C0_BASE + I2C_O_MCTRL) = ui32Cmd;
// Delay minimum four cycles in order to ensure that the I2C_O_MSTAT
// register has been correctly updated before function exit
CPUdelay(2);
}
//*****************************************************************************
//
//! \brief Sets the address that the I2C Master will place on the bus.
//!
//! This function will set the address that the I2C Master will place on the
//! bus when initiating a transaction. When the \e bReceive parameter is set
//! to \b true, the address will indicate that the I2C Master is initiating a
//! read from the slave; otherwise the address will indicate that the I2C
//! Master is initiating a write to the slave.
//!
//! \param ui32Base is the base address of the I2C module.
//! \param ui8SlaveAddr is a 7-bit slave address
//! \param bReceive flag indicates the type of communication with the slave.
//! - \c true : I2C Master is initiating a read from the slave.
//! - \c false : I2C Master is initiating a write to the slave.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr,
bool bReceive)
{
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
ASSERT(!(ui8SlaveAddr & 0x80));
// Set the address of the slave with which the master will communicate.
HWREG(I2C0_BASE + I2C_O_MSA) = (ui8SlaveAddr << 1) | bReceive;
}
//*****************************************************************************
//
//! \brief Enables the I2C Master block.
//!
//! This will enable operation of the I2C Master block.
//!
//! \param ui32Base is the base address of the I2C module.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
I2CMasterEnable(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
// Enable the clock for the master.
HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_MFE_BITN) = 1;
// Enable the master block.
HWREG(I2C0_BASE + I2C_O_MCTRL) = I2C_MCTRL_RUN;
}
//*****************************************************************************
//
//! \brief Disables the I2C master block.
//!
//! This will disable operation of the I2C master block.
//!
//! \param ui32Base is the base address of the I2C module.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
I2CMasterDisable(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
// Disable the master block.
HWREG(I2C0_BASE + I2C_O_MCTRL) = 0;
// Disable the clock for the master.
HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_MFE_BITN) = 0;
}
//*****************************************************************************
//
//! \brief Indicates whether or not the I2C Master is busy.
//!
//! This function returns an indication of whether or not the I2C Master is
//! busy transmitting or receiving data.
//!
//! \param ui32Base is the base address of the I2C module.
//!
//! \return Returns status of I2C Master:
//! - \c true : I2C Master is busy.
//! - \c false : I2C Master is not busy.
//
//*****************************************************************************
__STATIC_INLINE bool
I2CMasterBusy(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
// Return the busy status.
if(HWREG(I2C0_BASE + I2C_O_MSTAT) & I2C_MSTAT_BUSY)
{
return(true);
}
else
{
return(false);
}
}
//*****************************************************************************
//
//! \brief Indicates whether or not the I2C bus is busy.
//!
//! This function returns an indication of whether or not the I2C bus is busy.
//! This function can be used in a multi-master environment to determine if
//! another master is currently using the bus.
//!
//! \param ui32Base is the base address of the I2C module.
//!
//! \return Returns status of the I2C bus:
//! - \c true : I2C bus is busy.
//! - \c false : I2C bus is not busy.
//
//*****************************************************************************
__STATIC_INLINE bool
I2CMasterBusBusy(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
// Return the bus busy status.
if(HWREG(I2C0_BASE + I2C_O_MSTAT) & I2C_MSTAT_BUSBSY)
{
return(true);
}
else
{
return(false);
}
}
//*****************************************************************************
//
//! \brief Receives a byte that has been sent to the I2C Master.
//!
//! This function reads a byte of data from the I2C Master Data Register.
//!
//! \param ui32Base is the base address of the I2C module.
//!
//! \return Returns the byte received from by the I2C Master, cast as an
//! uint32_t.
//
//*****************************************************************************
__STATIC_INLINE uint32_t
I2CMasterDataGet(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
// Read a byte.
return(HWREG(I2C0_BASE + I2C_O_MDR));
}
//*****************************************************************************
//
//! \brief Transmits a byte from the I2C Master.
//!
//! This function will place the supplied data into I2C Master Data Register.
//!
//! \param ui32Base is the base address of the I2C module.
//! \param ui8Data is the data to be transmitted by the I2C Master
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data)
{
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
// Write the byte.
HWREG(I2C0_BASE + I2C_O_MDR) = ui8Data;
}
//*****************************************************************************
//
//! \brief Gets the error status of the I2C Master module.
//!
//! This function is used to obtain the error status of the Master module send
//! and receive operations.
//!
//! \param ui32Base is the base address of the I2C module.
//!
//! \return Returns the error status of the Master module:
//! - \ref I2C_MASTER_ERR_NONE
//! - \ref I2C_MASTER_ERR_ADDR_ACK
//! - \ref I2C_MASTER_ERR_DATA_ACK
//! - \ref I2C_MASTER_ERR_ARB_LOST
//
//*****************************************************************************
extern uint32_t I2CMasterErr(uint32_t ui32Base);
//*****************************************************************************
//
//! \brief Enables the I2C Master interrupt.
//!
//! Enables the I2C Master interrupt source.
//!
//! \param ui32Base is the base address of the I2C module.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
I2CMasterIntEnable(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
// Enable the master interrupt.
HWREG(I2C0_BASE + I2C_O_MIMR) = I2C_MIMR_IM;
}
//*****************************************************************************
//
//! \brief Disables the I2C Master interrupt.
//!
//! Disables the I2C Master interrupt source.
//!
//! \param ui32Base is the base address of the I2C module.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
I2CMasterIntDisable(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
// Disable the master interrupt.
HWREG(I2C0_BASE + I2C_O_MIMR) = 0;
}
//*****************************************************************************
//
//! \brief Clears I2C Master interrupt sources.
//!
//! The I2C Master interrupt source is cleared, so that it no longer asserts.
//! This must be done in the interrupt handler to keep it from being called
//! again immediately upon exit.
//!
//! \note Due to write buffers and synchronizers in the system it may take several
//! clock cycles from a register write clearing an event in a module and until the
//! event is actually cleared in the NVIC of the system CPU. It is recommended to
//! clear the event source early in the interrupt service routine (ISR) to allow
//! the event clear to propagate to the NVIC before returning from the ISR.
//! At the same time, an early event clear allows new events of the same type to be
//! pended instead of ignored if the event is cleared later in the ISR.
//! It is the responsibility of the programmer to make sure that enough time has passed
//! before returning from the ISR to avoid false re-triggering of the cleared event.
//! A simple, although not necessarily optimal, way of clearing an event before
//! returning from the ISR is:
//! -# Write to clear event (interrupt source). (buffered write)
//! -# Dummy read from the event source module. (making sure the write has propagated)
//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers)
//!
//! \param ui32Base is the base address of the I2C module.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
I2CMasterIntClear(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
// Clear the I2C master interrupt source.
HWREG(I2C0_BASE + I2C_O_MICR) = I2C_MICR_IC;
}
//*****************************************************************************
//
//! \brief Gets the current I2C Master interrupt status.
//!
//! This returns the interrupt status for the I2C Master module. Either the
//! raw interrupt status or the status of interrupts that are allowed to
//! reflect to the processor can be returned.
//!
//! \param ui32Base is the base address of the I2C Master module.
//! \param bMasked selects either raw or masked interrupt status.
//! - \c false : Raw interrupt status is requested.
//! - \c true : Masked interrupt status is requested.
//!
//! \return Returns the current interrupt status.
//! - \c true : Active.
//! - \c false : Not active.
//
//*****************************************************************************
__STATIC_INLINE bool
I2CMasterIntStatus(uint32_t ui32Base, bool bMasked)
{
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
// Return either the interrupt status or the raw interrupt status as
// requested.
if(bMasked)
{
return((HWREG(I2C0_BASE + I2C_O_MMIS)) ? true : false);
}
else
{
return((HWREG(I2C0_BASE + I2C_O_MRIS)) ? true : false);
}
}
//*****************************************************************************
//
//! \brief Enables the I2C Slave block.
//!
//! This will enable operation of the I2C Slave block.
//!
//! \param ui32Base is the base address of the I2C Slave module.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
I2CSlaveEnable(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
// Enable the clock to the slave block.
HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_SFE_BITN) = 1;
// Enable the slave.
HWREG(I2C0_BASE + I2C_O_SCTL) = I2C_SCTL_DA;
}
//*****************************************************************************
//
//! \brief Initializes the I2C Slave block.
//!
//! This function initializes operation of the I2C Slave block. Upon
//! successful initialization of the I2C blocks, this function will have set
//! the slave address and have enabled the I2C Slave block.
//!
//! The parameter \c ui8SlaveAddr is the value that will be compared against the
//! slave address sent by an I2C master.
//!
//! \param ui32Base is the base address of the I2C Slave module.
//! \param ui8SlaveAddr is the 7-bit slave address.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr)
{
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
ASSERT(!(ui8SlaveAddr & 0x80));
// Must enable the device before doing anything else.
I2CSlaveEnable(I2C0_BASE);
// Set up the slave address.
HWREG(I2C0_BASE + I2C_O_SOAR) = ui8SlaveAddr;
}
//*****************************************************************************
//
//! \brief Sets the I2C slave address.
//!
//! This function writes the specified slave address.
//!
//! \param ui32Base is the base address of the I2C Slave module.
//! \param ui8SlaveAddr is the 7-bit slave address
//!
//! \return None.
//
//*****************************************************************************
__STATIC_INLINE void
I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8SlaveAddr)
{
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
ASSERT(!(ui8SlaveAddr & 0x80));
// Set up the primary slave address.
HWREG(I2C0_BASE + I2C_O_SOAR) = ui8SlaveAddr;
}
//*****************************************************************************
//
//! \brief Disables the I2C slave block.
//!
//! This will disable operation of the I2C slave block.
//!
//! \param ui32Base is the base address of the I2C Slave module.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
I2CSlaveDisable(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
// Disable the slave.
HWREG(I2C0_BASE + I2C_O_SCTL) = 0x0;
// Disable the clock to the slave block.
HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_SFE_BITN) = 0;
}
//*****************************************************************************
//
//! \brief Gets the I2C Slave module status.
//!
//! This function will return the action requested from a master, if any.
//!
//! \param ui32Base is the base address of the I2C Slave module.
//!
//! \return Returns the status of the I2C Slave module:
//! - \ref I2C_SLAVE_ACT_NONE : No action has been requested of the I2C Slave module.
//! - \ref I2C_SLAVE_ACT_RREQ : An I2C master has sent data to the I2C Slave module.
//! - \ref I2C_SLAVE_ACT_TREQ : An I2C master has requested that the I2C Slave module send data.
//! - \ref I2C_SLAVE_ACT_RREQ_FBR : An I2C master has sent data to the I2C slave
//! and the first byte following the slave's own address has been received.
//
//*****************************************************************************
__STATIC_INLINE uint32_t
I2CSlaveStatus(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
// Return the slave status.
return(HWREG(I2C0_BASE + I2C_O_SSTAT));
}
//*****************************************************************************
//
//! \brief Receives a byte that has been sent to the I2C Slave.
//!
//! This function reads a byte of data from the I2C Slave Data Register.
//!
//! \param ui32Base is the base address of the I2C Slave module.
//!
//! \return Returns the byte received from by the I2C Slave, cast as an
//! uint32_t.
//
//*****************************************************************************
__STATIC_INLINE uint32_t
I2CSlaveDataGet(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
// Read a byte.
return(HWREG(I2C0_BASE + I2C_O_SDR));
}
//*****************************************************************************
//
//! \brief Transmits a byte from the I2C Slave.
//!
//! This function will place the supplied data into I2C Slave Data Register.
//!
//! \param ui32Base is the base address of the I2C Slave module.
//! \param ui8Data data to be transmitted from the I2C Slave.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data)
{
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
// Write the byte.
HWREG(I2C0_BASE + I2C_O_SDR) = ui8Data;
}
//*****************************************************************************
//
//! \brief Enables individual I2C Slave interrupt sources.
//!
//! Enables the indicated I2C Slave interrupt sources. Only the sources that
//! are enabled can be reflected to the processor interrupt; disabled sources
//! have no effect on the processor.
//!
//! \param ui32Base is the base address of the I2C module.
//! \param ui32IntFlags is the bit mask of the slave interrupt sources to be enabled.
//! The parameter is the bitwise OR of any of the following:
//! - \ref I2C_SLAVE_INT_STOP
//! - \ref I2C_SLAVE_INT_START
//! - \ref I2C_SLAVE_INT_DATA
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
I2CSlaveIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
{
uint32_t ui32Val;
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
ASSERT(ui32IntFlags & (I2C_SLAVE_INT_STOP | I2C_SLAVE_INT_START |
I2C_SLAVE_INT_DATA));
// Enable the slave interrupt.
ui32Val = HWREG(I2C0_BASE + I2C_O_SIMR);
ui32Val |= ui32IntFlags;
HWREG(I2C0_BASE + I2C_O_SIMR) = ui32Val;
}
//*****************************************************************************
//
//! \brief Disables individual I2C Slave interrupt sources.
//!
//! Disables the indicated I2C Slave interrupt sources. Only the sources that
//! are enabled can be reflected to the processor interrupt; disabled sources
//! have no effect on the processor.
//!
//! \param ui32Base is the base address of the I2C Slave module.
//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled.
//! The parameter is the bitwise OR of any of the following:
//! - \ref I2C_SLAVE_INT_STOP
//! - \ref I2C_SLAVE_INT_START
//! - \ref I2C_SLAVE_INT_DATA
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
I2CSlaveIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
{
uint32_t ui32Val;
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
ASSERT(ui32IntFlags & (I2C_SLAVE_INT_STOP | I2C_SLAVE_INT_START |
I2C_SLAVE_INT_DATA));
// Disable the slave interrupt.
ui32Val = HWREG(I2C0_BASE + I2C_O_SIMR);
ui32Val &= ~ui32IntFlags;
HWREG(I2C0_BASE + I2C_O_SIMR) = ui32Val;
}
//*****************************************************************************
//
//! \brief Clears I2C Slave interrupt sources.
//!
//! The specified I2C Slave interrupt sources are cleared, so that they no
//! longer assert. This must be done in the interrupt handler to keep it from
//! being called again immediately upon exit.
//!
//! \note Due to write buffers and synchronizers in the system it may take several
//! clock cycles from a register write clearing an event in a module and until the
//! event is actually cleared in the NVIC of the system CPU. It is recommended to
//! clear the event source early in the interrupt service routine (ISR) to allow
//! the event clear to propagate to the NVIC before returning from the ISR.
//! At the same time, an early event clear allows new events of the same type to be
//! pended instead of ignored if the event is cleared later in the ISR.
//! It is the responsibility of the programmer to make sure that enough time has passed
//! before returning from the ISR to avoid false re-triggering of the cleared event.
//! A simple, although not necessarily optimal, way of clearing an event before
//! returning from the ISR is:
//! -# Write to clear event (interrupt source). (buffered write)
//! -# Dummy read from the event source module. (making sure the write has propagated)
//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers)
//!
//! \param ui32Base is the base address of the I2C module.
//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
//! The parameter is the bitwise OR of any of the following:
//! - \ref I2C_SLAVE_INT_STOP
//! - \ref I2C_SLAVE_INT_START
//! - \ref I2C_SLAVE_INT_DATA
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
I2CSlaveIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
{
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
// Clear the I2C slave interrupt source.
HWREG(I2C0_BASE + I2C_O_SICR) = ui32IntFlags;
}
//*****************************************************************************
//
//! \brief Gets the current I2C Slave interrupt status.
//!
//! This returns the interrupt status for the I2C Slave module. Either the raw
//! interrupt status or the status of interrupts that are allowed to reflect to
//! the processor can be returned.
//!
//! \param ui32Base is the base address of the I2C Slave module.
//! \param bMasked selects either raw or masked interrupt status.
//! - \c false : Raw interrupt status is requested.
//! - \c true : Masked interrupt status is requested.
//!
//! \return Returns the current interrupt status as an OR'ed combination of:
//! - \ref I2C_SLAVE_INT_STOP
//! - \ref I2C_SLAVE_INT_START
//! - \ref I2C_SLAVE_INT_DATA
//
//*****************************************************************************
__STATIC_INLINE uint32_t
I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked)
{
// Check the arguments.
ASSERT(I2CBaseValid(ui32Base));
// Return either the interrupt status or the raw interrupt status as
// requested.
if(bMasked)
{
return(HWREG(I2C0_BASE + I2C_O_SMIS));
}
else
{
return(HWREG(I2C0_BASE + I2C_O_SRIS));
}
}
//*****************************************************************************
//
//! \brief Registers an interrupt handler for the I2C module in the dynamic interrupt table.
//!
//! \note Only use this function if you want to use the dynamic vector table (in SRAM)!
//!
//! This function registers a function as the interrupt handler for a specific
//! interrupt and enables the corresponding interrupt in the interrupt controller.
//!
//! Specific I2C interrupts must be enabled via \ref I2CMasterIntEnable() and
//! \ref I2CSlaveIntEnable(). If necessary, it is the interrupt handler's
//! responsibility to clear the interrupt source via \ref I2CMasterIntClear() and
//! \ref I2CSlaveIntClear().
//!
//! \param ui32Base is the base address of the I2C Master module.
//! \param pfnHandler is a pointer to the function to be called when the
//! I2C interrupt occurs.
//!
//! \return None
//!
//! \sa \ref IntRegister() for important information about registering interrupt
//! handlers.
//
//*****************************************************************************
extern void I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
//*****************************************************************************
//
//! \brief Unregisters an interrupt handler for the I2C module in the dynamic interrupt table.
//!
//! This function will clear the handler to be called when an I2C interrupt
//! occurs. This will also mask off the interrupt in the interrupt controller
//! so that the interrupt handler no longer is called.
//!
//! \param ui32Base is the base address of the I2C Master module.
//!
//! \return None
//!
//! \sa \brief IntRegister() for important information about registering interrupt
//! handlers.
//
//*****************************************************************************
extern void I2CIntUnregister(uint32_t ui32Base);
//*****************************************************************************
//
// Support for DriverLib in ROM:
// Redirect to implementation in ROM when available.
//
//*****************************************************************************
#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
#include "../driverlib/rom.h"
#ifdef ROM_I2CMasterInitExpClk
#undef I2CMasterInitExpClk
#define I2CMasterInitExpClk ROM_I2CMasterInitExpClk
#endif
#ifdef ROM_I2CMasterErr
#undef I2CMasterErr
#define I2CMasterErr ROM_I2CMasterErr
#endif
#ifdef ROM_I2CIntRegister
#undef I2CIntRegister
#define I2CIntRegister ROM_I2CIntRegister
#endif
#ifdef ROM_I2CIntUnregister
#undef I2CIntUnregister
#define I2CIntUnregister ROM_I2CIntUnregister
#endif
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __I2C_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

162
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@ -1,162 +0,0 @@
/******************************************************************************
* Filename: i2c_doc.h
* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016)
* Revision: 45971
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//! \addtogroup i2c_api
//! @{
//! \section sec_i2c Introduction
//!
//! The Inter-Integrated Circuit (\i2c) API provides a set of functions for using
//! the \ti_device \i2c master and slave module. Functions are provided to perform
//! the following actions:
//! - Initialize the \i2c module.
//! - Send and receive data.
//! - Obtain status.
//! - Manage interrupts for the \i2c module.
//!
//! The \i2c master and slave module provide the ability to communicate to other IC
//! devices over an \i2c bus. The \i2c bus is specified to support devices that can
//! both transmit and receive (write and read) data. Also, devices on the \i2c bus
//! can be designated as either a master or a slave. The \ti_device \i2c module
//! supports both sending and receiving data as either a master or a slave, and also
//! support the simultaneous operation as both a master and a slave. Finally, the
//! \ti_device \i2c module can operate at two speeds: standard (100 kb/s) and fast
//! (400 kb/s).
//!
//! The master and slave \i2c module can generate interrupts. The \i2c master
//! module generates interrupts when a transmit or receive operation
//! completes (or aborts due to an error).
//! The \i2c slave module can generate interrupts when data is
//! sent or requested by a master and when a START or STOP condition is present.
//!
//! \section sec_i2c_master Master Operations
//!
//! When using this API to drive the \i2c master module, the user must first
//! initialize the \i2c master module with a call to \ref I2CMasterInitExpClk(). This
//! function sets the bus speed and enables the master module.
//!
//! The user may transmit or receive data after the successful initialization of
//! the \i2c master module. Data is transferred by first setting the slave address
//! using \ref I2CMasterSlaveAddrSet(). This function is also used to define whether
//! the transfer is a send (a write to the slave from the master) or a receive (a
//! read from the slave by the master). Then, if connected to an \i2c bus that has
//! multiple masters, the \ti_device \i2c master must first call \ref I2CMasterBusBusy()
//! before trying to initiate the desired transaction. After determining that
//! the bus is not busy, if trying to send data, the user must call the
//! \ref I2CMasterDataPut() function. The transaction can then be initiated on the bus
//! by calling the \ref I2CMasterControl() function with any of the following commands:
//! - \ref I2C_MASTER_CMD_SINGLE_SEND
//! - \ref I2C_MASTER_CMD_SINGLE_RECEIVE
//! - \ref I2C_MASTER_CMD_BURST_SEND_START
//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_START
//!
//! Any of these commands result in the master arbitrating for the bus,
//! driving the start sequence onto the bus, and sending the slave address and
//! direction bit across the bus. The remainder of the transaction can then be
//! driven using either a polling or interrupt-driven method.
//!
//! For the single send and receive cases, the polling method involves looping
//! on the return from \ref I2CMasterBusy(). Once the function indicates that the \i2c
//! master is no longer busy, the bus transaction is complete and can be
//! checked for errors using \ref I2CMasterErr(). If there are no errors, then the data
//! has been sent or is ready to be read using \ref I2CMasterDataGet(). For the burst
//! send and receive cases, the polling method also involves calling the
//! \ref I2CMasterControl() function for each byte transmitted or received
//! (using either the \ref I2C_MASTER_CMD_BURST_SEND_CONT or \ref I2C_MASTER_CMD_BURST_RECEIVE_CONT
//! commands), and for the last byte sent or received (using either the
//! \ref I2C_MASTER_CMD_BURST_SEND_FINISH or \ref I2C_MASTER_CMD_BURST_RECEIVE_FINISH
//! commands).
//!
//! If any error is detected during the burst transfer,
//! the appropriate stop command (\ref I2C_MASTER_CMD_BURST_SEND_ERROR_STOP or
//! \ref I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP) should be used to call the
//! \ref I2CMasterControl() function.
//!
//! For the interrupt-driven transaction, the user must register an interrupt
//! handler for the \i2c devices and enable the \i2c master interrupt; the interrupt
//! occurs when the master is no longer busy.
//!
//! \section sec_i2c_slave Slave Operations
//!
//! When using this API to drive the \i2c slave module, the user must first
//! initialize the \i2c slave module with a call to \ref I2CSlaveInit(). This function
//! enables the \i2c slave module and initializes the address of the slave. After the
//! initialization completes, the user may poll the slave status using
//! \ref I2CSlaveStatus() to determine if a master requested a send or receive
//! operation. Depending on the type of operation requested, the user can call
//! \ref I2CSlaveDataPut() or \ref I2CSlaveDataGet() to complete the transaction.
//! Alternatively, the \i2c slave can handle transactions using an interrupt handler
//! registered with \ref I2CIntRegister(), and by enabling the \i2c slave interrupt.
//!
//! \section sec_i2c_api API
//!
//! The \i2c API is broken into three groups of functions:
//! those that handle status and initialization, those that
//! deal with sending and receiving data, and those that deal with
//! interrupts.
//!
//! Status and initialization functions for the \i2c module are:
//! - \ref I2CMasterInitExpClk()
//! - \ref I2CMasterEnable()
//! - \ref I2CMasterDisable()
//! - \ref I2CMasterBusBusy()
//! - \ref I2CMasterBusy()
//! - \ref I2CMasterErr()
//! - \ref I2CSlaveInit()
//! - \ref I2CSlaveEnable()
//! - \ref I2CSlaveDisable()
//! - \ref I2CSlaveStatus()
//!
//! Sending and receiving data from the \i2c module is handled by the following functions:
//! - \ref I2CMasterSlaveAddrSet()
//! - \ref I2CSlaveAddressSet()
//! - \ref I2CMasterControl()
//! - \ref I2CMasterDataGet()
//! - \ref I2CMasterDataPut()
//! - \ref I2CSlaveDataGet()
//! - \ref I2CSlaveDataPut()
//!
//! The \i2c master and slave interrupts are handled by the following functions:
//! - \ref I2CIntRegister()
//! - \ref I2CIntUnregister()
//! - \ref I2CMasterIntEnable()
//! - \ref I2CMasterIntDisable()
//! - \ref I2CMasterIntClear()
//! - \ref I2CMasterIntStatus()
//! - \ref I2CSlaveIntEnable()
//! - \ref I2CSlaveIntDisable()
//! - \ref I2CSlaveIntClear()
//! - \ref I2CSlaveIntStatus()
//!
//! @}

349
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2s.c
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@ -1,349 +0,0 @@
/******************************************************************************
* Filename: i2s.c
* Revised: 2017-05-08 12:18:04 +0200 (Mon, 08 May 2017)
* Revision: 48924
*
* Description: Driver for the I2S.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "i2s.h"
//*****************************************************************************
//
// Handle support for DriverLib in ROM:
// This section will undo prototype renaming made in the header file
//
//*****************************************************************************
#if !defined(DOXYGEN)
#undef I2SEnable
#define I2SEnable NOROM_I2SEnable
#undef I2SAudioFormatConfigure
#define I2SAudioFormatConfigure NOROM_I2SAudioFormatConfigure
#undef I2SChannelConfigure
#define I2SChannelConfigure NOROM_I2SChannelConfigure
#undef I2SBufferConfig
#define I2SBufferConfig NOROM_I2SBufferConfig
#undef I2SPointerUpdate
#define I2SPointerUpdate NOROM_I2SPointerUpdate
#undef I2SPointerSet
#define I2SPointerSet NOROM_I2SPointerSet
#undef I2SSampleStampConfigure
#define I2SSampleStampConfigure NOROM_I2SSampleStampConfigure
#undef I2SSampleStampGet
#define I2SSampleStampGet NOROM_I2SSampleStampGet
#endif
//*****************************************************************************
//
// Global pointer to the current I2S data structure
//
//*****************************************************************************
I2SControlTable *g_pControlTable;
//*****************************************************************************
//
// Enables the I2S module for operation
//
//*****************************************************************************
void
I2SEnable(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(I2SBaseValid(ui32Base));
// Make sure the control table pointer is setup to a memory location.
if(!(g_pControlTable))
{
return;
}
// Write the address to the first input/output buffer.
HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = g_pControlTable->ui32InBase;
g_pControlTable->ui32InOffset = 0;
HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = g_pControlTable->ui32OutBase;
g_pControlTable->ui32OutOffset = 0;
// Enable the I2S module.
HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = (uint32_t)g_pControlTable->ui16DMABufSize - 1;
}
//*****************************************************************************
//
// Configures the I2S module
//
//*****************************************************************************
void
I2SAudioFormatConfigure(uint32_t ui32Base, uint32_t ui32FmtCfg,
uint32_t ui32BitClkDelay)
{
// Check the arguments.
ASSERT(I2SBaseValid(ui32Base));
ASSERT(ui32BitClkDelay <= 255);
// Save the length of the audio words stored in memory.
g_pControlTable->ui16MemLen = (ui32FmtCfg & I2S_MEM_LENGTH_24) ? 24 : 16;
// Write the configuration.
HWREG(I2S0_BASE + I2S_O_AIFFMTCFG) = ui32FmtCfg | (ui32BitClkDelay << I2S_AIFFMTCFG_DATA_DELAY_S);
}
//****************************************************************************
//
// Setup the audio channel configuration
//
//****************************************************************************
void
I2SChannelConfigure(uint32_t ui32Base, uint32_t ui32Chan0Cfg,
uint32_t ui32Chan1Cfg)
{
uint32_t ui32InChan;
uint32_t ui32OutChan;
uint32_t ui32ChanMask;
// Check the arguments.
ASSERT(I2SBaseValid(ui32Base));
ASSERT(ui32Chan0Cfg & (I2S_CHAN_CFG_MASK | I2S_LINE_MASK))
ASSERT(ui32Chan1Cfg & (I2S_CHAN_CFG_MASK | I2S_LINE_MASK))
ui32InChan = 0;
ui32OutChan = 0;
// Configure input/output channels.
HWREG(I2S0_BASE + I2S_O_AIFDIRCFG) = (
(( ui32Chan0Cfg << I2S_AIFDIRCFG_AD0_S) & I2S_AIFDIRCFG_AD0_M ) |
(( ui32Chan1Cfg << I2S_AIFDIRCFG_AD1_S) & I2S_AIFDIRCFG_AD1_M ) );
// Configure the valid channel mask.
HWREG(I2S0_BASE + I2S_O_AIFWMASK0) = (ui32Chan0Cfg >> 8) & I2S_AIFWMASK0_MASK_M;
HWREG(I2S0_BASE + I2S_O_AIFWMASK1) = (ui32Chan1Cfg >> 8) & I2S_AIFWMASK1_MASK_M;
// Resolve and save the number of input and output channels.
ui32ChanMask = (ui32Chan0Cfg & I2S_CHAN_CFG_MASK) >> 8;
if(ui32Chan0Cfg & I2S_LINE_INPUT)
{
while(ui32ChanMask)
{
if(ui32ChanMask & 0x1)
{
ui32InChan++;
}
// Shift down channel mask
ui32ChanMask >>= 1;
}
}
else if(ui32Chan0Cfg & I2S_LINE_OUTPUT)
{
while(ui32ChanMask)
{
if(ui32ChanMask & 0x1)
{
ui32OutChan++;
}
// Shift down channel mask
ui32ChanMask >>= 1;
}
}
ui32ChanMask = (ui32Chan1Cfg & I2S_CHAN_CFG_MASK) >> 8;
if(ui32Chan1Cfg & I2S_LINE_INPUT)
{
while(ui32ChanMask)
{
if(ui32ChanMask & 0x1)
{
ui32InChan++;
}
// Shift down channel mask
ui32ChanMask >>= 1;
}
}
else if(ui32Chan1Cfg & I2S_LINE_OUTPUT)
{
while(ui32ChanMask)
{
if(ui32ChanMask & 0x1)
{
ui32OutChan++;
}
// Shift down channel mask
ui32ChanMask >>= 1;
}
}
g_pControlTable->ui8InChan = (uint8_t)ui32InChan;
g_pControlTable->ui8OutChan = (uint8_t)ui32OutChan;
}
//****************************************************************************
//
// Set the input buffer pointers
//
//****************************************************************************
void
I2SBufferConfig(uint32_t ui32Base, uint32_t ui32InBufBase,
uint32_t ui32OutBufBase, uint16_t ui16DMABufSize,
uint16_t ui16ChanBufSize)
{
// Check the arguments.
ASSERT(I2SBaseValid(ui32Base));
ASSERT(ui16DMABufSize > 0);
// Setup the input data pointer and buffer sizes.
g_pControlTable->ui16DMABufSize = ui16DMABufSize;
g_pControlTable->ui16ChBufSize = ui16ChanBufSize;
g_pControlTable->ui32InBase = ui32InBufBase;
g_pControlTable->ui32OutBase = ui32OutBufBase;
}
//****************************************************************************
//
// Set the buffer pointers
//
//****************************************************************************
void
I2SPointerSet(uint32_t ui32Base, bool bInput, void * pNextPointer)
{
// Check the arguments.
ASSERT(I2SBaseValid(ui32Base));
// Update the next input/output pointer with the correct address.
if(bInput == true)
{
HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = (uint32_t)pNextPointer;
}
else
{
HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = (uint32_t)pNextPointer;
}
}
//****************************************************************************
//
// Update the buffer pointers
//
//****************************************************************************
void
I2SPointerUpdate(uint32_t ui32Base, bool bInput)
{
uint32_t ui32NextPtr;
// Check the arguments.
ASSERT(I2SBaseValid(ui32Base));
// Update the next input/output pointer with the correct address.
if(bInput == true)
{
ui32NextPtr = (g_pControlTable->ui8InChan *
(g_pControlTable->ui16MemLen >> 3)) *
g_pControlTable->ui16DMABufSize;
g_pControlTable->ui32InOffset = ((g_pControlTable->ui32InOffset +
ui32NextPtr) %
g_pControlTable->ui16ChBufSize);
HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = g_pControlTable->ui32InOffset +
g_pControlTable->ui32InBase;
}
else
{
ui32NextPtr = (g_pControlTable->ui8OutChan *
(g_pControlTable->ui16MemLen >> 3)) *
g_pControlTable->ui16DMABufSize;
g_pControlTable->ui32OutOffset = ((g_pControlTable->ui32OutOffset +
ui32NextPtr) %
g_pControlTable->ui16ChBufSize);
HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) =
g_pControlTable->ui32OutOffset +
g_pControlTable->ui32OutBase;
}
}
//*****************************************************************************
//
// Configure the sample stamp generator
//
//*****************************************************************************
void
I2SSampleStampConfigure(uint32_t ui32Base, bool bInput, bool bOutput)
{
uint32_t ui32Trigger;
// Check the arguments.
ASSERT(I2SBaseValid(ui32Base));
ui32Trigger = HWREG(I2S0_BASE + I2S_O_STMPWCNT);
ui32Trigger = (ui32Trigger + 2) % g_pControlTable->ui16ChBufSize;
// Setup the sample stamp trigger for input streams.
if(bInput)
{
HWREG(I2S0_BASE + I2S_O_STMPINTRIG) = ui32Trigger;
}
// Setup the sample stamp trigger for output streams.
if(bOutput)
{
HWREG(I2S0_BASE + I2S_O_STMPOUTTRIG) = ui32Trigger;
}
}
//*****************************************************************************
//
// Get the current value of a sample stamp counter
//
//*****************************************************************************
uint32_t
I2SSampleStampGet(uint32_t ui32Base, uint32_t ui32Channel)
{
uint32_t ui32FrameClkCnt;
uint32_t ui32SysClkCnt;
uint32_t ui32PeriodSysClkCnt;
uint32_t ui32SampleStamp;
// Get the number of Frame clock counts since last stamp.
ui32FrameClkCnt = HWREG(I2S0_BASE + I2S_O_STMPWCNTCAPT0);
// Get the number of system clock ticks since last frame clock edge.
ui32SysClkCnt = HWREG(I2S0_BASE + I2S_O_STMPXCNTCAPT0);
// Get the number system clock ticks in the last frame clock period.
ui32PeriodSysClkCnt = HWREG(I2S0_BASE + I2S_O_STMPXPER);
// Calculate the sample stamp.
ui32SampleStamp = (ui32SysClkCnt << 16) / ui32PeriodSysClkCnt;
ui32SampleStamp = (ui32SampleStamp > I2S_STMP_SATURATION) ?
I2S_STMP_SATURATION : ui32SampleStamp;
ui32SampleStamp |= (ui32FrameClkCnt << 16);
return (ui32SampleStamp);
}

1359
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2s.h
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141
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2s_doc.h
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@ -1,141 +0,0 @@
/******************************************************************************
* Filename: i2s_doc.h
* Revised: $$
* Revision: $$
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//! \addtogroup i2s_api
//! @{
//! \section sec_i2s Introduction
//!
//! The I2S API provides a set of functions for using the I2S module.
//! This module provides a standardized serial interface to transfer
//! audio samples from and to external audio devices such as a codec,
//! DAC, or ADC.
//!
//! The I2S module has the following features:
//! - Audio clock signals are internally generated by the PRCM module
//! or externally by another device.
//! - One or two data pins, which can be configured independently as
//! input or output
//! - Various data formats according to the settings of the module
//! - Up to two channels per data pin for dual phase formats and up
//! to eight channels per data pin for single phase formats
//! - DMA with double-buffered pointers
//! - Error detection for DMA and audio clock signal integrity
//! - A Samplestamp generator that allows maintaining of constant
//! audio latency
//!
//! The I2S module is configured through the functions \ref I2SFormatConfigure(),
//! \ref I2SFrameConfigure() and \ref I2SWclkConfigure().
//! Transfers are enabled using \ref I2SStart(). Transfers are disabled using
//! \ref I2SStop(). Please note that a specific procedure exists in order
//! to disable transfers without losing data (refer to \ref I2SStop()).
//!
//! Data are transmitted using the two double-buffered pointers.
//! For each interface, two registers are set with the address of the data to
//! transfer. These registers are named INPTR and INPTRNEXT for the input
//! interface and OUTPTR and OUTPTRNEXT for the output. When PTR is consumed,
//! the hardware copies the content of PTRNEXT into PTR and the next transfer
//! begins.
//! The address of the next value to write or to read in memory (i.e. to receive
//! or to send out) is set using \ref I2SInPointerSet() and \ref I2SOutPointerSet().
//! The values contented by INPTRNEXT, OUTPTRNEXT, INPTR and OUTPTR can be read using
//! \ref I2SInPointerNextGet(), \ref I2SOutPointerNextGet(), \ref I2SInPointerGet() and
//! \ref I2SOutPointerGet() functions.
//!
//! Interrupts can help the user to refresh pointers on time. Interrupts can also
//! be used to detect I2S errors. \ref I2SIntEnable() and \ref I2SIntDisable()
//! activate and deactivate interrupt(s). Interrupt status can be read through
//! \ref I2SIntStatus() and a pending interrupt can be acquitted by
//! \ref I2SIntClear() function.
//!
//! The sample stamps generator can be configured to slightly delay the
//! emission or the reception of the data (based on the number of WCLK
//! cycles) using \ref I2SSampleStampInConfigure(), \ref I2SSampleStampOutConfigure(),
//! \ref I2SWclkCounterReset() and \ref I2SWclkCounterConfigure(). The current sample stamp
//! can be computed using \ref I2SSampleStampGet().
//! To finish, the sample stamps generator can be enable and disable using
//! the following functions: \ref I2SSampleStampEnable() and
//! \ref I2SSampleStampDisable().
//! The sample stamps generator must be enabled prior to any transfer.
//!
//! Note: Other functions contained in the PRCM API are required to handle I2S.
//!
//! \section sec_i2s_api API
//!
//! Two APIs are coexisting.
//! It is recommended to only use the new API as the old one is deprecated and
//! will be removed soon.
//!
//! New API:
//! Functions to perform I2S configuration:
//! - \ref I2SStart()
//! - \ref I2SStop()
//! - \ref I2SFormatConfigure()
//! - \ref I2SFrameConfigure()
//! - \ref I2SWclkConfigure()
//!
//! Functions to perform transfers:
//! - \ref I2SInPointerSet()
//! - \ref I2SOutPointerSet()
//! - \ref I2SInPointerGet()
//! - \ref I2SOutPointerGet()
//! - \ref I2SInPointerNextGet()
//! - \ref I2SOutPointerNextGet()
//!
//! Functions to handle interruptions:
//! - \ref I2SIntEnable()
//! - \ref I2SIntDisable()
//! - \ref I2SIntStatus()
//! - \ref I2SIntClear()
//!
//! Functions to handle sample stamps
//! - \ref I2SSampleStampEnable()
//! - \ref I2SSampleStampDisable()
//! - \ref I2SSampleStampInConfigure()
//! - \ref I2SSampleStampOutConfigure()
//! - \ref I2SSampleStampGet()
//! - \ref I2SWclkCounterConfigure()
//! - \ref I2SWclkCounterReset()
//!
//! Old API:
//! \ref I2SEnable(), \ref I2SDisable(), \ref I2SAudioFormatConfigure(),
//! \ref I2SChannelConfigure(), \ref I2SClockConfigure(),
//! \ref I2SBufferConfig(), \ref I2SIntEnable(), \ref I2SIntDisable(),
//! \ref I2SIntStatus(), \ref I2SIntClear(), \ref I2SSampleStampEnable(),
//! \ref I2SSampleStampDisable(), \ref I2SSampleStampGet(),
//! \ref I2SPointerSet (), \ref I2SPointerUpdate(),
//! \ref I2SSampleStampConfigure(), \ref I2SIntRegister(),
//! \ref I2SIntUnregister()
//!
//! @}

469
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt.c
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@ -1,469 +0,0 @@
/******************************************************************************
* Filename: interrupt.c
* Revised: 2017-05-19 11:31:39 +0200 (Fri, 19 May 2017)
* Revision: 49017
*
* Description: Driver for the NVIC Interrupt Controller.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "interrupt.h"
//*****************************************************************************
//
// Handle support for DriverLib in ROM:
// This section will undo prototype renaming made in the header file
//
//*****************************************************************************
#if !defined(DOXYGEN)
#undef IntRegister
#define IntRegister NOROM_IntRegister
#undef IntUnregister
#define IntUnregister NOROM_IntUnregister
#undef IntPriorityGroupingSet
#define IntPriorityGroupingSet NOROM_IntPriorityGroupingSet
#undef IntPriorityGroupingGet
#define IntPriorityGroupingGet NOROM_IntPriorityGroupingGet
#undef IntPrioritySet
#define IntPrioritySet NOROM_IntPrioritySet
#undef IntPriorityGet
#define IntPriorityGet NOROM_IntPriorityGet
#undef IntEnable
#define IntEnable NOROM_IntEnable
#undef IntDisable
#define IntDisable NOROM_IntDisable
#undef IntPendSet
#define IntPendSet NOROM_IntPendSet
#undef IntPendGet
#define IntPendGet NOROM_IntPendGet
#undef IntPendClear
#define IntPendClear NOROM_IntPendClear
#endif
//*****************************************************************************
//
//! This is a mapping between priority grouping encodings and the number of
//! preemption priority bits.
//
//*****************************************************************************
static const uint32_t g_pui32Priority[] =
{
NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6,
NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3,
NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1
};
//*****************************************************************************
//
//! This is a mapping between interrupt number and the register that contains
//! the priority encoding for that interrupt.
//
//*****************************************************************************
static const uint32_t g_pui32Regs[] =
{
0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1,
NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13
};
//*****************************************************************************
//
//! \brief The default interrupt handler.
//!
//! This is the default interrupt handler for all interrupts. It simply loops
//! forever so that the system state is preserved for observation by a
//! debugger. Since interrupts should be disabled before unregistering the
//! corresponding handler, this should never be called.
//!
//! \return None
//
//*****************************************************************************
static void
IntDefaultHandler(void)
{
// Go into an infinite loop.
while(1)
{
}
}
//*****************************************************************************
//
//! \brief Global pointer to the (dynamic) interrupt vector table when placed in SRAM.
//!
//! Interrupt vector table is placed at "vtable_ram" defined in the linker file
//! provided by Texas Instruments. By default, this is at the beginning of SRAM.
//!
//! \note See \ti_code{interrupt.c} for compiler specific implementation!
//
//*****************************************************************************
#if defined(DOXYGEN)
// Dummy void pointer used as placeholder to generate Doxygen documentation.
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma data_alignment=256
static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ ".vtable_ram";
#elif defined(__TI_COMPILER_VERSION__)
#pragma DATA_ALIGN(g_pfnRAMVectors, 256)
#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable_ram")
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
#elif defined (__CC_ARM)
static __attribute__((section("vtable_ram")))
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__((aligned(256)));
#else
static __attribute__((section("vtable_ram")))
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__((aligned(256)));
#endif
//*****************************************************************************
//
// Registers a function to be called when an interrupt occurs.
//
//*****************************************************************************
void
IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void))
{
uint32_t ui32Idx, ui32Value;
// Check the arguments.
ASSERT(ui32Interrupt < NUM_INTERRUPTS);
// Make sure that the RAM vector table is correctly aligned.
ASSERT(((uint32_t)g_pfnRAMVectors & 0x000000ff) == 0);
// See if the RAM vector table has been initialized.
if(HWREG(NVIC_VTABLE) != (uint32_t)g_pfnRAMVectors)
{
// Copy the vector table from the beginning of FLASH to the RAM vector
// table.
ui32Value = HWREG(NVIC_VTABLE);
for(ui32Idx = 0; ui32Idx < NUM_INTERRUPTS; ui32Idx++)
{
g_pfnRAMVectors[ui32Idx] = (void (*)(void))HWREG((ui32Idx * 4) +
ui32Value);
}
// Point NVIC at the RAM vector table.
HWREG(NVIC_VTABLE) = (uint32_t)g_pfnRAMVectors;
}
// Save the interrupt handler.
g_pfnRAMVectors[ui32Interrupt] = pfnHandler;
}
//*****************************************************************************
//
// Unregisters the function to be called when an interrupt occurs.
//
//*****************************************************************************
void
IntUnregister(uint32_t ui32Interrupt)
{
// Check the arguments.
ASSERT(ui32Interrupt < NUM_INTERRUPTS);
// Reset the interrupt handler.
g_pfnRAMVectors[ui32Interrupt] = IntDefaultHandler;
}
//*****************************************************************************
//
// Sets the priority grouping of the interrupt controller.
//
//*****************************************************************************
void
IntPriorityGroupingSet(uint32_t ui32Bits)
{
// Check the arguments.
ASSERT(ui32Bits < NUM_PRIORITY);
// Set the priority grouping.
HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pui32Priority[ui32Bits];
}
//*****************************************************************************
//
// Gets the priority grouping of the interrupt controller
//
//*****************************************************************************
uint32_t
IntPriorityGroupingGet(void)
{
uint32_t ui32Loop, ui32Value;
// Read the priority grouping.
ui32Value = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M;
// Loop through the priority grouping values.
for(ui32Loop = 0; ui32Loop < NUM_PRIORITY; ui32Loop++)
{
// Stop looping if this value matches.
if(ui32Value == g_pui32Priority[ui32Loop])
{
break;
}
}
// Return the number of priority bits.
return(ui32Loop);
}
//*****************************************************************************
//
// Sets the priority of an interrupt
//
//*****************************************************************************
void
IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority)
{
uint32_t ui32Temp;
// Check the arguments.
ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS));
ASSERT(ui8Priority <= INT_PRI_LEVEL7);
// Set the interrupt priority.
ui32Temp = HWREG(g_pui32Regs[ui32Interrupt >> 2]);
ui32Temp &= ~(0xFF << (8 * (ui32Interrupt & 3)));
ui32Temp |= ui8Priority << (8 * (ui32Interrupt & 3));
HWREG(g_pui32Regs[ui32Interrupt >> 2]) = ui32Temp;
}
//*****************************************************************************
//
// Gets the priority of an interrupt
//
//*****************************************************************************
int32_t
IntPriorityGet(uint32_t ui32Interrupt)
{
// Check the arguments.
ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS));
// Return the interrupt priority.
return((HWREG(g_pui32Regs[ui32Interrupt >> 2]) >> (8 * (ui32Interrupt & 3))) &
0xFF);
}
//*****************************************************************************
//
// Enables an interrupt
//
//*****************************************************************************
void
IntEnable(uint32_t ui32Interrupt)
{
// Check the arguments.
ASSERT(ui32Interrupt < NUM_INTERRUPTS);
// Determine the interrupt to enable.
if(ui32Interrupt == INT_MEMMANAGE_FAULT)
{
// Enable the MemManage interrupt.
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM;
}
else if(ui32Interrupt == INT_BUS_FAULT)
{
// Enable the bus fault interrupt.
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS;
}
else if(ui32Interrupt == INT_USAGE_FAULT)
{
// Enable the usage fault interrupt.
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE;
}
else if(ui32Interrupt == INT_SYSTICK)
{
// Enable the System Tick interrupt.
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
}
else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47))
{
// Enable the general interrupt.
HWREG(NVIC_EN0) = 1 << (ui32Interrupt - 16);
}
else if(ui32Interrupt >= 48)
{
// Enable the general interrupt.
HWREG(NVIC_EN1) = 1 << (ui32Interrupt - 48);
}
}
//*****************************************************************************
//
// Disables an interrupt
//
//*****************************************************************************
void
IntDisable(uint32_t ui32Interrupt)
{
// Check the arguments.
ASSERT(ui32Interrupt < NUM_INTERRUPTS);
// Determine the interrupt to disable.
if(ui32Interrupt == INT_MEMMANAGE_FAULT)
{
// Disable the MemManage interrupt.
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM);
}
else if(ui32Interrupt == INT_BUS_FAULT)
{
// Disable the bus fault interrupt.
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS);
}
else if(ui32Interrupt == INT_USAGE_FAULT)
{
// Disable the usage fault interrupt.
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE);
}
else if(ui32Interrupt == INT_SYSTICK)
{
// Disable the System Tick interrupt.
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
}
else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47))
{
// Disable the general interrupt.
HWREG(NVIC_DIS0) = 1 << (ui32Interrupt - 16);
}
else if(ui32Interrupt >= 48)
{
// Disable the general interrupt.
HWREG(NVIC_DIS1) = 1 << (ui32Interrupt - 48);
}
}
//*****************************************************************************
//
// Pends an interrupt
//
//*****************************************************************************
void
IntPendSet(uint32_t ui32Interrupt)
{
// Check the arguments.
ASSERT(ui32Interrupt < NUM_INTERRUPTS);
// Determine the interrupt to pend.
if(ui32Interrupt == INT_NMI_FAULT)
{
// Pend the NMI interrupt.
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET;
}
else if(ui32Interrupt == INT_PENDSV)
{
// Pend the PendSV interrupt.
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV;
}
else if(ui32Interrupt == INT_SYSTICK)
{
// Pend the SysTick interrupt.
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET;
}
else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47))
{
// Pend the general interrupt.
HWREG(NVIC_PEND0) = 1 << (ui32Interrupt - 16);
}
else if(ui32Interrupt >= 48)
{
// Pend the general interrupt.
HWREG(NVIC_PEND1) = 1 << (ui32Interrupt - 48);
}
}
//*****************************************************************************
//
// Query whether an interrupt is pending
//
//*****************************************************************************
bool
IntPendGet(uint32_t ui32Interrupt)
{
uint32_t ui32IntPending;
// Check the arguments.
ASSERT(ui32Interrupt < NUM_INTERRUPTS);
// Assume no interrupts are pending.
ui32IntPending = 0;
// The lower 16 IRQ vectors are unsupported by this function
if (ui32Interrupt < 16)
{
return 0;
}
// Subtract lower 16 irq vectors
ui32Interrupt -= 16;
// Check if the interrupt is pending
ui32IntPending = HWREG(NVIC_PEND0 + (ui32Interrupt / 32));
ui32IntPending &= (1 << (ui32Interrupt & 31));
return ui32IntPending ? true : false;
}
//*****************************************************************************
//
// Unpends an interrupt
//
//*****************************************************************************
void
IntPendClear(uint32_t ui32Interrupt)
{
// Check the arguments.
ASSERT(ui32Interrupt < NUM_INTERRUPTS);
// Determine the interrupt to unpend.
if(ui32Interrupt == INT_PENDSV)
{
// Unpend the PendSV interrupt.
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV;
}
else if(ui32Interrupt == INT_SYSTICK)
{
// Unpend the SysTick interrupt.
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR;
}
else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47))
{
// Unpend the general interrupt.
HWREG(NVIC_UNPEND0) = 1 << (ui32Interrupt - 16);
}
else if(ui32Interrupt >= 48)
{
// Unpend the general interrupt.
HWREG(NVIC_UNPEND1) = 1 << (ui32Interrupt - 48);
}
}

718
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt.h
View file

@ -1,718 +0,0 @@
/******************************************************************************
* Filename: interrupt.h
* Revised: 2017-11-14 15:26:03 +0100 (Tue, 14 Nov 2017)
* Revision: 50272
*
* Description: Defines and prototypes for the NVIC Interrupt Controller
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup system_cpu_group
//! @{
//! \addtogroup interrupt_api
//! @{
//
//*****************************************************************************
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdbool.h>
#include <stdint.h>
#include "../inc/hw_ints.h"
#include "../inc/hw_types.h"
#include "../inc/hw_nvic.h"
#include "debug.h"
#include "cpu.h"
//*****************************************************************************
//
// Support for DriverLib in ROM:
// This section renames all functions that are not "static inline", so that
// calling these functions will default to implementation in flash. At the end
// of this file a second renaming will change the defaults to implementation in
// ROM for available functions.
//
// To force use of the implementation in flash, e.g. for debugging:
// - Globally: Define DRIVERLIB_NOROM at project level
// - Per function: Use prefix "NOROM_" when calling the function
//
//*****************************************************************************
#if !defined(DOXYGEN)
#define IntRegister NOROM_IntRegister
#define IntUnregister NOROM_IntUnregister
#define IntPriorityGroupingSet NOROM_IntPriorityGroupingSet
#define IntPriorityGroupingGet NOROM_IntPriorityGroupingGet
#define IntPrioritySet NOROM_IntPrioritySet
#define IntPriorityGet NOROM_IntPriorityGet
#define IntEnable NOROM_IntEnable
#define IntDisable NOROM_IntDisable
#define IntPendSet NOROM_IntPendSet
#define IntPendGet NOROM_IntPendGet
#define IntPendClear NOROM_IntPendClear
#endif
//*****************************************************************************
//
// Macro to generate an interrupt priority mask based on the number of bits
// of priority supported by the hardware. For CC26xx the number of priority
// bit is 3 as defined in <tt>hw_types.h</tt>. The priority mask is
// defined as
//
// INT_PRIORITY_MASK = ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
//
//*****************************************************************************
#define INT_PRIORITY_MASK 0x000000E0
#define INT_PRI_LEVEL0 0x00000000
#define INT_PRI_LEVEL1 0x00000020
#define INT_PRI_LEVEL2 0x00000040
#define INT_PRI_LEVEL3 0x00000060
#define INT_PRI_LEVEL4 0x00000080
#define INT_PRI_LEVEL5 0x000000A0
#define INT_PRI_LEVEL6 0x000000C0
#define INT_PRI_LEVEL7 0x000000E0
//*****************************************************************************
//
// API Functions and prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Registers a function as an interrupt handler in the dynamic vector table.
//!
//! \note Only use this function if you want to use the dynamic vector table (in SRAM)!
//!
//! This function writes a function pointer to the dynamic interrupt vector table
//! in SRAM to register the function as an interrupt handler (ISR). When the corresponding
//! interrupt occurs, and it has been enabled (see \ref IntEnable()), the function
//! pointer is fetched from the dynamic vector table, and the System CPU will
//! execute the interrupt handler.
//!
//! \note The first call to this function (directly or indirectly via a peripheral
//! driver interrupt register function) copies the interrupt vector table from
//! Flash to SRAM. NVIC uses the static vector table (in Flash) until this function
//! is called.
//!
//! \param ui32Interrupt specifies the index in the vector table to modify.
//! - System exceptions (vectors 0 to 15):
//! - INT_NMI_FAULT
//! - INT_HARD_FAULT
//! - INT_MEMMANAGE_FAULT
//! - INT_BUS_FAULT
//! - INT_USAGE_FAULT
//! - INT_SVCALL
//! - INT_DEBUG
//! - INT_PENDSV
//! - INT_SYSTICK
//! - Interrupts (vectors >15):
//! - INT_AON_GPIO_EDGE
//! - INT_I2C_IRQ
//! - INT_RFC_CPE_1
//! - INT_PKA_IRQ
//! - INT_AON_RTC_COMB
//! - INT_UART0_COMB
//! - INT_AUX_SWEV0
//! - INT_SSI0_COMB
//! - INT_SSI1_COMB
//! - INT_RFC_CPE_0
//! - INT_RFC_HW_COMB
//! - INT_RFC_CMD_ACK
//! - INT_I2S_IRQ
//! - INT_AUX_SWEV1
//! - INT_WDT_IRQ
//! - INT_GPT0A
//! - INT_GPT0B
//! - INT_GPT1A
//! - INT_GPT1B
//! - INT_GPT2A
//! - INT_GPT2B
//! - INT_GPT3A
//! - INT_GPT3B
//! - INT_CRYPTO_RESULT_AVAIL_IRQ
//! - INT_DMA_DONE_COMB
//! - INT_DMA_ERR
//! - INT_FLASH
//! - INT_SWEV0
//! - INT_AUX_COMB
//! - INT_AON_PROG0
//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister())
//! - INT_AUX_COMPA
//! - INT_AUX_ADC_IRQ
//! - INT_TRNG_IRQ
//! - INT_OSC_COMB
//! - INT_AUX_TIMER2_EV0
//! - INT_UART1_COMB
//! - INT_BATMON_COMB
//! \param pfnHandler is a pointer to the function to register as interrupt handler.
//!
//! \return None.
//!
//! \sa \ref IntUnregister(), \ref IntEnable()
//
//*****************************************************************************
extern void IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void));
//*****************************************************************************
//
//! \brief Unregisters an interrupt handler in the dynamic vector table.
//!
//! This function removes an interrupt handler from the dynamic vector table and
//! replaces it with the default interrupt handler \ref IntDefaultHandler().
//!
//! \note Remember to disable the interrupt before removing its interrupt handler
//! from the vector table.
//!
//! \param ui32Interrupt specifies the index in the vector table to modify.
//! - See \ref IntRegister() for list of valid arguments.
//!
//! \return None.
//!
//! \sa \ref IntRegister(), \ref IntDisable()
//
//*****************************************************************************
extern void IntUnregister(uint32_t ui32Interrupt);
//*****************************************************************************
//
//! \brief Sets the priority grouping of the interrupt controller.
//!
//! This function specifies the split between preemptable priority levels and
//! subpriority levels in the interrupt priority specification.
//!
//! Three bits are available for hardware interrupt prioritization thus priority
//! grouping values of three through seven have the same effect.
//!
//! \param ui32Bits specifies the number of bits of preemptable priority.
//! - 0 : No pre-emption priority, eight bits of subpriority.
//! - 1 : One bit of pre-emption priority, seven bits of subpriority
//! - 2 : Two bits of pre-emption priority, six bits of subpriority
//! - 3-7 : Three bits of pre-emption priority, five bits of subpriority
//!
//! \return None
//!
//! \sa \ref IntPrioritySet()
//
//*****************************************************************************
extern void IntPriorityGroupingSet(uint32_t ui32Bits);
//*****************************************************************************
//
//! \brief Gets the priority grouping of the interrupt controller.
//!
//! This function returns the split between preemptable priority levels and
//! subpriority levels in the interrupt priority specification.
//!
//! \return Returns the number of bits of preemptable priority.
//! - 0 : No pre-emption priority, eight bits of subpriority.
//! - 1 : One bit of pre-emption priority, seven bits of subpriority
//! - 2 : Two bits of pre-emption priority, six bits of subpriority
//! - 3-7 : Three bits of pre-emption priority, five bits of subpriority
//
//*****************************************************************************
extern uint32_t IntPriorityGroupingGet(void);
//*****************************************************************************
//
//! \brief Sets the priority of an interrupt.
//!
//! This function sets the priority of an interrupt, including system exceptions.
//! When multiple interrupts are asserted simultaneously, the ones with the highest
//! priority are processed before the lower priority interrupts. Smaller numbers
//! correspond to higher interrupt priorities thus priority 0 is the highest
//! interrupt priority.
//!
//! \warning This function does not support setting priority of interrupt vectors
//! one through three which are:
//! - 1: Reset handler
//! - 2: NMI handler
//! - 3: Hard fault handler
//!
//! \param ui32Interrupt specifies the index in the vector table to change priority for.
//! - System exceptions:
//! - INT_MEMMANAGE_FAULT
//! - INT_BUS_FAULT
//! - INT_USAGE_FAULT
//! - INT_SVCALL
//! - INT_DEBUG
//! - INT_PENDSV
//! - INT_SYSTICK
//! - Interrupts:
//! - INT_AON_GPIO_EDGE
//! - INT_I2C_IRQ
//! - INT_RFC_CPE_1
//! - INT_PKA_IRQ
//! - INT_AON_RTC_COMB
//! - INT_UART0_COMB
//! - INT_AUX_SWEV0
//! - INT_SSI0_COMB
//! - INT_SSI1_COMB
//! - INT_RFC_CPE_0
//! - INT_RFC_HW_COMB
//! - INT_RFC_CMD_ACK
//! - INT_I2S_IRQ
//! - INT_AUX_SWEV1
//! - INT_WDT_IRQ
//! - INT_GPT0A
//! - INT_GPT0B
//! - INT_GPT1A
//! - INT_GPT1B
//! - INT_GPT2A
//! - INT_GPT2B
//! - INT_GPT3A
//! - INT_GPT3B
//! - INT_CRYPTO_RESULT_AVAIL_IRQ
//! - INT_DMA_DONE_COMB
//! - INT_DMA_ERR
//! - INT_FLASH
//! - INT_SWEV0
//! - INT_AUX_COMB
//! - INT_AON_PROG0
//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister())
//! - INT_AUX_COMPA
//! - INT_AUX_ADC_IRQ
//! - INT_TRNG_IRQ
//! - INT_OSC_COMB
//! - INT_AUX_TIMER2_EV0
//! - INT_UART1_COMB
//! - INT_BATMON_COMB
//! \param ui8Priority specifies the priority of the interrupt.
//! - \ref INT_PRI_LEVEL0 : Highest priority.
//! - \ref INT_PRI_LEVEL1
//! - \ref INT_PRI_LEVEL2
//! - \ref INT_PRI_LEVEL3
//! - \ref INT_PRI_LEVEL4
//! - \ref INT_PRI_LEVEL5
//! - \ref INT_PRI_LEVEL6
//! - \ref INT_PRI_LEVEL7 : Lowest priority.
//!
//! \return None
//!
//! \sa \ref IntPriorityGroupingSet()
//
//*****************************************************************************
extern void IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority);
//*****************************************************************************
//
//! \brief Gets the priority of an interrupt.
//!
//! This function gets the priority of an interrupt.
//!
//! \warning This function does not support getting priority of interrupt vectors
//! one through three which are:
//! - 1: Reset handler
//! - 2: NMI handler
//! - 3: Hard fault handler
//!
//! \param ui32Interrupt specifies the index in the vector table to read priority of.
//! - See \ref IntPrioritySet() for list of valid arguments.
//!
//! \return Returns the interrupt priority:
//! - \ref INT_PRI_LEVEL0 : Highest priority.
//! - \ref INT_PRI_LEVEL1
//! - \ref INT_PRI_LEVEL2
//! - \ref INT_PRI_LEVEL3
//! - \ref INT_PRI_LEVEL4
//! - \ref INT_PRI_LEVEL5
//! - \ref INT_PRI_LEVEL6
//! - \ref INT_PRI_LEVEL7 : Lowest priority.
//
//*****************************************************************************
extern int32_t IntPriorityGet(uint32_t ui32Interrupt);
//*****************************************************************************
//
//! \brief Enables an interrupt or system exception.
//!
//! This function enables the specified interrupt in the interrupt controller.
//!
//! \note If a fault condition occurs while the corresponding system exception
//! is disabled, the fault is treated as a Hard Fault.
//!
//! \param ui32Interrupt specifies the index in the vector table to enable.
//! - System exceptions:
//! - INT_MEMMANAGE_FAULT
//! - INT_BUS_FAULT
//! - INT_USAGE_FAULT
//! - INT_SYSTICK
//! - Interrupts:
//! - INT_AON_GPIO_EDGE
//! - INT_I2C_IRQ
//! - INT_RFC_CPE_1
//! - INT_PKA_IRQ
//! - INT_AON_RTC_COMB
//! - INT_UART0_COMB
//! - INT_AUX_SWEV0
//! - INT_SSI0_COMB
//! - INT_SSI1_COMB
//! - INT_RFC_CPE_0
//! - INT_RFC_HW_COMB
//! - INT_RFC_CMD_ACK
//! - INT_I2S_IRQ
//! - INT_AUX_SWEV1
//! - INT_WDT_IRQ
//! - INT_GPT0A
//! - INT_GPT0B
//! - INT_GPT1A
//! - INT_GPT1B
//! - INT_GPT2A
//! - INT_GPT2B
//! - INT_GPT3A
//! - INT_GPT3B
//! - INT_CRYPTO_RESULT_AVAIL_IRQ
//! - INT_DMA_DONE_COMB
//! - INT_DMA_ERR
//! - INT_FLASH
//! - INT_SWEV0
//! - INT_AUX_COMB
//! - INT_AON_PROG0
//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister())
//! - INT_AUX_COMPA
//! - INT_AUX_ADC_IRQ
//! - INT_TRNG_IRQ
//! - INT_OSC_COMB
//! - INT_AUX_TIMER2_EV0
//! - INT_UART1_COMB
//! - INT_BATMON_COMB
//!
//! \return None
//!
//! \sa \ref IntDisable()
//
//*****************************************************************************
extern void IntEnable(uint32_t ui32Interrupt);
//*****************************************************************************
//
//! \brief Disables an interrupt or system exception.
//!
//! This function disables the specified interrupt in the interrupt controller.
//!
//! \param ui32Interrupt specifies the index in the vector table to disable.
//! - See \ref IntEnable() for list of valid arguments.
//!
//! \return None
//!
//! \sa \ref IntEnable()
//
//*****************************************************************************
extern void IntDisable(uint32_t ui32Interrupt);
//*****************************************************************************
//
//! \brief Pends an interrupt.
//!
//! This function pends the specified interrupt in the interrupt controller.
//! This causes the interrupt controller to execute the corresponding interrupt
//! handler at the next available time, based on the current interrupt state
//! priorities.
//!
//! This interrupt controller automatically clears the pending interrupt once the
//! interrupt handler is executed.
//!
//! \param ui32Interrupt specifies the index in the vector table to pend.
//! - System exceptions:
//! - INT_NMI_FAULT
//! - INT_PENDSV
//! - INT_SYSTICK
//! - Interrupts:
//! - INT_AON_GPIO_EDGE
//! - INT_I2C_IRQ
//! - INT_RFC_CPE_1
//! - INT_PKA_IRQ
//! - INT_AON_RTC_COMB
//! - INT_UART0_COMB
//! - INT_AUX_SWEV0
//! - INT_SSI0_COMB
//! - INT_SSI1_COMB
//! - INT_RFC_CPE_0
//! - INT_RFC_HW_COMB
//! - INT_RFC_CMD_ACK
//! - INT_I2S_IRQ
//! - INT_AUX_SWEV1
//! - INT_WDT_IRQ
//! - INT_GPT0A
//! - INT_GPT0B
//! - INT_GPT1A
//! - INT_GPT1B
//! - INT_GPT2A
//! - INT_GPT2B
//! - INT_GPT3A
//! - INT_GPT3B
//! - INT_CRYPTO_RESULT_AVAIL_IRQ
//! - INT_DMA_DONE_COMB
//! - INT_DMA_ERR
//! - INT_FLASH
//! - INT_SWEV0
//! - INT_AUX_COMB
//! - INT_AON_PROG0
//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister())
//! - INT_AUX_COMPA
//! - INT_AUX_ADC_IRQ
//! - INT_TRNG_IRQ
//! - INT_OSC_COMB
//! - INT_AUX_TIMER2_EV0
//! - INT_UART1_COMB
//! - INT_BATMON_COMB
//!
//! \return None
//!
//! \sa \ref IntEnable()
//
//*****************************************************************************
extern void IntPendSet(uint32_t ui32Interrupt);
//*****************************************************************************
//
//! \brief Checks if an interrupt is pending.
//!
//! This function checks the interrupt controller to see if an interrupt is pending.
//!
//! The interrupt must be enabled in order for the corresponding interrupt handler
//! to be executed, so an interrupt can be pending waiting to be enabled or waiting
//! for an interrupt of higher priority to be done executing.
//!
//! \note This function does not support reading pending status for system exceptions
//! (vector table indexes <16).
//!
//! \param ui32Interrupt specifies the index in the vector table to check pending
//! status for.
//! - See \ref IntPendSet() for list of valid arguments (except system exceptions).
//!
//! \return Returns:
//! - \c true : Specified interrupt is pending.
//! - \c false : Specified interrupt is not pending.
//
//*****************************************************************************
extern bool IntPendGet(uint32_t ui32Interrupt);
//*****************************************************************************
//
//! \brief Unpends an interrupt.
//!
//! This function unpends the specified interrupt in the interrupt controller.
//! This causes any previously generated interrupts that have not been handled yet
//! (due to higher priority interrupts or the interrupt no having been enabled
//! yet) to be discarded.
//!
//! \note It is not possible to unpend the NMI because it takes effect
//! immediately when being pended.
//!
//! \param ui32Interrupt specifies the index in the vector table to unpend.
//! - See \ref IntPendSet() for list of valid arguments (except NMI).
//!
//! \return None
//
//*****************************************************************************
extern void IntPendClear(uint32_t ui32Interrupt);
//*****************************************************************************
//
//! \brief Enables the CPU interrupt.
//!
//! Allows the CPU to respond to interrupts.
//!
//! \return Returns:
//! - \c true : Interrupts were disabled and are now enabled.
//! - \c false : Interrupts were already enabled when the function was called.
//
//*****************************************************************************
__STATIC_INLINE bool
IntMasterEnable(void)
{
// Enable CPU interrupts.
return(CPUcpsie());
}
//*****************************************************************************
//
//! \brief Disables the CPU interrupts with configurable priority.
//!
//! Prevents the CPU from receiving interrupts except NMI and hard fault. This
//! does not affect the set of interrupts enabled in the interrupt controller;
//! it just gates the interrupt from the interrupt controller to the CPU.
//!
//! \return Returns:
//! - \c true : Interrupts were already disabled when the function was called.
//! - \c false : Interrupts were enabled and are now disabled.
//
//*****************************************************************************
__STATIC_INLINE bool
IntMasterDisable(void)
{
// Disable CPU interrupts.
return(CPUcpsid());
}
//*****************************************************************************
//
//! \brief Sets the priority masking level.
//!
//! This function sets the interrupt priority masking level so that all
//! interrupts at the specified or lesser priority level are masked. This
//! can be used to globally disable a set of interrupts with priority below
//! a predetermined threshold. A value of 0 disables priority
//! masking.
//!
//! Smaller numbers correspond to higher interrupt priorities. So for example
//! a priority level mask of 4 will allow interrupts of priority level 0-3,
//! and interrupts with a numerical priority of 4 and greater will be blocked.
//! The device supports priority levels 0 through 7.
//!
//! \param ui32PriorityMask is the priority level that will be masked.
//! - 0 : Disable priority masking.
//! - 1 : Allow priority 0 interrupts, mask interrupts with priority 1-7.
//! - 2 : Allow priority 0-1 interrupts, mask interrupts with priority 2-7.
//! - 3 : Allow priority 0-2 interrupts, mask interrupts with priority 3-7.
//! - 4 : Allow priority 0-3 interrupts, mask interrupts with priority 4-7.
//! - 5 : Allow priority 0-4 interrupts, mask interrupts with priority 5-7.
//! - 6 : Allow priority 0-5 interrupts, mask interrupts with priority 6-7.
//! - 7 : Allow priority 0-6 interrupts, mask interrupts with priority 7.
//!
//! \return None.
//
//*****************************************************************************
__STATIC_INLINE void
IntPriorityMaskSet(uint32_t ui32PriorityMask)
{
CPUbasepriSet(ui32PriorityMask);
}
//*****************************************************************************
//
//! \brief Gets the priority masking level.
//!
//! This function gets the current setting of the interrupt priority masking
//! level. The value returned is the priority level such that all interrupts
//! of that and lesser priority are masked. A value of 0 means that priority
//! masking is disabled.
//!
//! Smaller numbers correspond to higher interrupt priorities. So for example
//! a priority level mask of 4 will allow interrupts of priority level 0-3,
//! and interrupts with a numerical priority of 4 and greater will be blocked.
//!
//! \return Returns the value of the interrupt priority level mask.
//
//*****************************************************************************
__STATIC_INLINE uint32_t
IntPriorityMaskGet(void)
{
return(CPUbasepriGet());
}
//*****************************************************************************
//
// Support for DriverLib in ROM:
// Redirect to implementation in ROM when available.
//
//*****************************************************************************
#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
#include "../driverlib/rom.h"
#ifdef ROM_IntRegister
#undef IntRegister
#define IntRegister ROM_IntRegister
#endif
#ifdef ROM_IntUnregister
#undef IntUnregister
#define IntUnregister ROM_IntUnregister
#endif
#ifdef ROM_IntPriorityGroupingSet
#undef IntPriorityGroupingSet
#define IntPriorityGroupingSet ROM_IntPriorityGroupingSet
#endif
#ifdef ROM_IntPriorityGroupingGet
#undef IntPriorityGroupingGet
#define IntPriorityGroupingGet ROM_IntPriorityGroupingGet
#endif
#ifdef ROM_IntPrioritySet
#undef IntPrioritySet
#define IntPrioritySet ROM_IntPrioritySet
#endif
#ifdef ROM_IntPriorityGet
#undef IntPriorityGet
#define IntPriorityGet ROM_IntPriorityGet
#endif
#ifdef ROM_IntEnable
#undef IntEnable
#define IntEnable ROM_IntEnable
#endif
#ifdef ROM_IntDisable
#undef IntDisable
#define IntDisable ROM_IntDisable
#endif
#ifdef ROM_IntPendSet
#undef IntPendSet
#define IntPendSet ROM_IntPendSet
#endif
#ifdef ROM_IntPendGet
#undef IntPendGet
#define IntPendGet ROM_IntPendGet
#endif
#ifdef ROM_IntPendClear
#undef IntPendClear
#define IntPendClear ROM_IntPendClear
#endif
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __INTERRUPT_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

162
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@ -1,162 +0,0 @@
/******************************************************************************
* Filename: interrupt_doc.h
* Revised: 2017-11-14 15:26:03 +0100 (Tue, 14 Nov 2017)
* Revision: 50272
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//! \addtogroup interrupt_api
//! @{
//! \section sec_interrupt Introduction
//!
//! The interrupt controller API provides a set of functions for dealing with the
//! Nested Vectored Interrupt Controller (NVIC). Functions are provided to enable
//! and disable interrupts, register interrupt handlers, and set the priority of
//! interrupts.
//!
//! The event sources that trigger the interrupt lines in the NVIC are controlled by
//! the MCU event fabric. All event sources are statically connected to the NVIC interrupt lines
//! except one which is programmable. For more information about the MCU event fabric, see the
//! [MCU event fabric API](\ref event_api).
//!
//! \section sec_interrupt_api API
//!
//! Interrupts and system exceptions must be individually enabled and disabled through:
//! - \ref IntEnable()
//! - \ref IntDisable()
//!
//! The global CPU interrupt can be enabled and disabled with the following functions:
//! - \ref IntMasterEnable()
//! - \ref IntMasterDisable()
//!
//! This does not affect the individual interrupt enable states. Masking of the CPU
//! interrupt can be used as a simple critical section (only an NMI can interrupt the
//! CPU while the CPU interrupt is disabled), although masking the CPU
//! interrupt can increase the interrupt response time.
//!
//! It is possible to access the NVIC to see if any interrupts are pending and manually
//! clear pending interrupts which have not yet been serviced or set a specific interrupt as
//! pending to be handled based on its priority. Pending interrupts are cleared automatically
//! when the interrupt is accepted and executed. However, the event source which caused the
//! interrupt might need to be cleared manually to avoid re-triggering the corresponding interrupt.
//! The functions to read, clear, and set pending interrupts are:
//! - \ref IntPendGet()
//! - \ref IntPendClear()
//! - \ref IntPendSet()
//!
//! The interrupt prioritization in the NVIC allows handling of higher priority interrupts
//! before lower priority interrupts, as well as allowing preemption of lower priority interrupt
//! handlers by higher priority interrupts.
//! The device supports eight priority levels from 0 to 7 with 0 being the highest priority.
//! The priority of each interrupt source can be set and examined using:
//! - \ref IntPrioritySet()
//! - \ref IntPriorityGet()
//!
//! Interrupts can be masked based on their priority such that interrupts with the same or lower
//! priority than the mask are effectively disabled. This can be configured with:
//! - \ref IntPriorityMaskSet()
//! - \ref IntPriorityMaskGet()
//!
//! Subprioritization is also possible. Instead of having three bits of preemptable
//! prioritization (eight levels), the NVIC can be configured for 3 - M bits of
//! preemptable prioritization and M bits of subpriority. In this scheme, two
//! interrupts with the same preemptable prioritization but different subpriorities
//! do not cause a preemption. Instead, tail chaining is used to process
//! the two interrupts back-to-back.
//! If two interrupts with the same priority (and subpriority if so configured) are
//! asserted at the same time, the one with the lower interrupt number is
//! processed first.
//! Subprioritization is handled by:
//! - \ref IntPriorityGroupingSet()
//! - \ref IntPriorityGroupingGet()
//!
//! \section sec_interrupt_table Interrupt Vector Table
//!
//! The interrupt vector table can be configured in one of two ways:
//! - Statically (at compile time): Vector table is placed in Flash and each entry has a fixed
//! pointer to an interrupt handler (ISR).
//! - Dynamically (at runtime): Vector table is placed in SRAM and each entry can be changed
//! (registered or unregistered) at runtime. This allows a single interrupt to trigger different
//! interrupt handlers (ISRs) depending on which interrupt handler is registered at the time the
//! System CPU responds to the interrupt.
//!
//! When configured, the interrupts must be explicitly enabled in the NVIC through \ref IntEnable()
//! before the CPU can respond to the interrupt (in addition to any interrupt enabling required
//! within the peripheral).
//!
//! \subsection sec_interrupt_table_static Static Vector Table
//!
//! Static registration of interrupt handlers is accomplished by editing the interrupt handler
//! table in the startup code of the application. Texas Instruments provides startup files for
//! each supported compiler ( \ti_code{startup_<compiler>.c} ) and these startup files include
//! a default static interrupt vector table.
//! All entries, except ResetISR, are declared as \c extern with weak assignment to a default
//! interrupt handler. This allows the user to declare and define a function (in the user's code)
//! with the same name as an entry in the vector table. At compile time, the linker then replaces
//! the pointer to the default interrupt handler in the vector table with the pointer to the
//! interrupt handler defined by the user.
//!
//! Statically configuring the interrupt table provides the fastest interrupt response time
//! because the stacking operation (a write to SRAM on the data bus) is performed in parallel
//! with the interrupt handler table fetch (a read from Flash on the instruction bus), as well
//! as the prefetch of the interrupt handler (assuming it is also in Flash).
//!
//! \subsection sec_interrupt_table_dynamic Dynamic Vector Table
//!
//! Alternatively, interrupts can be registered in the vector table at runtime, thus dynamically.
//! The dynamic vector table is placed in SRAM and the code can then modify the pointers to
//! interrupt handlers throughout the application.
//!
//! DriverLib uses these two functions to modify the dynamic vector table:
//! - \ref IntRegister() : Write a pointer to an interrupt handler into the vector table.
//! - \ref IntUnregister() : Write pointer to default interrupt handler into the vector table.
//!
//! \note First call to \ref IntRegister() initializes the vector table in SRAM by copying the
//! static vector table from Flash and forcing the NVIC to use the dynamic vector table from
//! this point forward. If using the dynamic vector table it is highly recommended to
//! initialize it during the setup phase of the application. The NVIC uses the static vector
//! table in Flash until the application initializes the dynamic vector table in SRAM.
//!
//! Runtime configuration of interrupts adds a small latency to the interrupt response time
//! because the stacking operation (a write to SRAM on the data bus) and the interrupt handler
//! fetch from the vector table (a read from SRAM on the instruction bus) must be performed
//! sequentially.
//!
//! The dynamic vector table, \ref g_pfnRAMVectors, is placed in SRAM in the section called
//! \c vtable_ram which is a section defined in the linker file. By default the linker file
//! places this section at the start of the SRAM but this is configurable by the user.
//!
//! \warning Runtime configuration of interrupt handlers requires that the interrupt
//! handler table is placed on a 256-byte boundary in SRAM (typically, this is
//! at the beginning of SRAM). Failure to do so results in an incorrect vector
//! address being fetched in response to an interrupt.
//!
//! @}

683
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.c
View file

@ -1,683 +0,0 @@
/******************************************************************************
* Filename: ioc.c
* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017)
* Revision: 49096
*
* Description: Driver for the IOC.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "ioc.h"
//*****************************************************************************
//
// Handle support for DriverLib in ROM:
// This section will undo prototype renaming made in the header file
//
//*****************************************************************************
#if !defined(DOXYGEN)
#undef IOCPortConfigureSet
#define IOCPortConfigureSet NOROM_IOCPortConfigureSet
#undef IOCPortConfigureGet
#define IOCPortConfigureGet NOROM_IOCPortConfigureGet
#undef IOCIOShutdownSet
#define IOCIOShutdownSet NOROM_IOCIOShutdownSet
#undef IOCIOModeSet
#define IOCIOModeSet NOROM_IOCIOModeSet
#undef IOCIOIntSet
#define IOCIOIntSet NOROM_IOCIOIntSet
#undef IOCIOEvtSet
#define IOCIOEvtSet NOROM_IOCIOEvtSet
#undef IOCIOPortPullSet
#define IOCIOPortPullSet NOROM_IOCIOPortPullSet
#undef IOCIOHystSet
#define IOCIOHystSet NOROM_IOCIOHystSet
#undef IOCIOInputSet
#define IOCIOInputSet NOROM_IOCIOInputSet
#undef IOCIOSlewCtrlSet
#define IOCIOSlewCtrlSet NOROM_IOCIOSlewCtrlSet
#undef IOCIODrvStrengthSet
#define IOCIODrvStrengthSet NOROM_IOCIODrvStrengthSet
#undef IOCIOPortIdSet
#define IOCIOPortIdSet NOROM_IOCIOPortIdSet
#undef IOCIntEnable
#define IOCIntEnable NOROM_IOCIntEnable
#undef IOCIntDisable
#define IOCIntDisable NOROM_IOCIntDisable
#undef IOCPinTypeGpioInput
#define IOCPinTypeGpioInput NOROM_IOCPinTypeGpioInput
#undef IOCPinTypeGpioOutput
#define IOCPinTypeGpioOutput NOROM_IOCPinTypeGpioOutput
#undef IOCPinTypeUart
#define IOCPinTypeUart NOROM_IOCPinTypeUart
#undef IOCPinTypeSsiMaster
#define IOCPinTypeSsiMaster NOROM_IOCPinTypeSsiMaster
#undef IOCPinTypeSsiSlave
#define IOCPinTypeSsiSlave NOROM_IOCPinTypeSsiSlave
#undef IOCPinTypeI2c
#define IOCPinTypeI2c NOROM_IOCPinTypeI2c
#undef IOCPinTypeAux
#define IOCPinTypeAux NOROM_IOCPinTypeAux
#endif
//*****************************************************************************
//
// Set the configuration of an IO port
//
//*****************************************************************************
void
IOCPortConfigureSet(uint32_t ui32IOId, uint32_t ui32PortId,
uint32_t ui32IOConfig)
{
uint32_t ui32Reg;
// Check the arguments.
ASSERT(ui32IOId <= IOID_31);
ASSERT(ui32PortId <= IOC_PORT_RFC_GPI1);
// Get the register address.
ui32Reg = IOC_BASE + ( ui32IOId << 2 );
// Configure the port.
HWREG(ui32Reg) = ui32IOConfig | ui32PortId;
}
//*****************************************************************************
//
// Get the configuration of an IO port
//
//*****************************************************************************
uint32_t
IOCPortConfigureGet(uint32_t ui32IOId)
{
uint32_t ui32Reg;
// Check the arguments.
ASSERT(ui32IOId <= IOID_31);
// Get the register address.
ui32Reg = IOC_BASE + ( ui32IOId << 2 );
// Return the IO configuration.
return HWREG(ui32Reg);
}
//*****************************************************************************
//
// Set wake-up on an IO port
//
//*****************************************************************************
void
IOCIOShutdownSet(uint32_t ui32IOId, uint32_t ui32IOShutdown)
{
uint32_t ui32Reg;
uint32_t ui32Config;
// Check the arguments.
ASSERT(ui32IOId <= IOID_31);
ASSERT((ui32IOShutdown == IOC_NO_WAKE_UP) ||
(ui32IOShutdown == IOC_WAKE_ON_LOW) ||
(ui32IOShutdown == IOC_WAKE_ON_HIGH));
// Get the register address.
ui32Reg = IOC_BASE + ( ui32IOId << 2 );
// Configure the IO.
ui32Config = HWREG(ui32Reg);
ui32Config &= ~IOC_IOCFG0_WU_CFG_M;
HWREG(ui32Reg) = ui32Config | ui32IOShutdown;
}
//*****************************************************************************
//
// Set the IO Mode of an IO Port
//
//*****************************************************************************
void
IOCIOModeSet(uint32_t ui32IOId, uint32_t ui32IOMode)
{
uint32_t ui32Reg;
uint32_t ui32Config;
// Check the arguments.
ASSERT(ui32IOId <= IOID_31);
ASSERT((ui32IOMode == IOC_IOMODE_NORMAL) ||
(ui32IOMode == IOC_IOMODE_INV) ||
(ui32IOMode == IOC_IOMODE_OPEN_DRAIN_NORMAL) ||
(ui32IOMode == IOC_IOMODE_OPEN_DRAIN_INV) ||
(ui32IOMode == IOC_IOMODE_OPEN_SRC_NORMAL) ||
(ui32IOMode == IOC_IOMODE_OPEN_SRC_INV));
// Get the register address.
ui32Reg = IOC_BASE + ( ui32IOId << 2 );
// Configure the IO.
ui32Config = HWREG(ui32Reg);
ui32Config &= ~IOC_IOCFG0_IOMODE_M;
HWREG(ui32Reg) = ui32Config | ui32IOMode;
}
//*****************************************************************************
//
// Setup interrupt detection on an IO Port
//
//*****************************************************************************
void
IOCIOIntSet(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet)
{
uint32_t ui32IOReg;
uint32_t ui32Config;
// Check the arguments.
ASSERT(ui32IOId <= IOID_31);
ASSERT((ui32Int == IOC_INT_ENABLE) ||
(ui32Int == IOC_INT_DISABLE));
ASSERT((ui32EdgeDet == IOC_NO_EDGE) ||
(ui32EdgeDet == IOC_FALLING_EDGE) ||
(ui32EdgeDet == IOC_RISING_EDGE) ||
(ui32EdgeDet == IOC_BOTH_EDGES));
// Get the register address.
ui32IOReg = IOC_BASE + ( ui32IOId << 2 );
// Configure the IO.
ui32Config = HWREG(ui32IOReg);
ui32Config &= ~(IOC_IOCFG0_EDGE_IRQ_EN | IOC_IOCFG0_EDGE_DET_M);
HWREG(ui32IOReg) = ui32Config | ((ui32Int ? IOC_IOCFG0_EDGE_IRQ_EN : 0) | ui32EdgeDet);
}
//*****************************************************************************
//
// Setup event generation on IO edge detection
//
//*****************************************************************************
void
IOCIOEvtSet(uint32_t ui32IOId, uint32_t ui32Evt)
{
uint32_t ui32IOReg;
uint32_t ui32Config;
// Check the arguments.
ASSERT(ui32IOId <= IOID_31);
ASSERT( (ui32Evt & ~(IOC_IOCFG0_IOEV_AON_PROG2_EN_M |
IOC_IOCFG0_IOEV_AON_PROG1_EN_M |
IOC_IOCFG0_IOEV_AON_PROG0_EN_M |
IOC_IOCFG0_IOEV_RTC_EN_M |
IOC_IOCFG0_IOEV_MCU_WU_EN_M) ) == 0x00000000);
// Get the register address.
ui32IOReg = IOC_BASE + ( ui32IOId << 2 );
// Read current configuration.
ui32Config = HWREG(ui32IOReg);
// Disable generation of all events.
ui32Config &= ~(IOC_IOCFG0_IOEV_AON_PROG2_EN_M |
IOC_IOCFG0_IOEV_AON_PROG1_EN_M |
IOC_IOCFG0_IOEV_AON_PROG0_EN_M |
IOC_IOCFG0_IOEV_RTC_EN_M |
IOC_IOCFG0_IOEV_MCU_WU_EN_M);
// Enable the required events.
HWREG(ui32IOReg) = ui32Config | ui32Evt;
}
//*****************************************************************************
//
// Set the pull on an IO port
//
//*****************************************************************************
void
IOCIOPortPullSet(uint32_t ui32IOId, uint32_t ui32Pull)
{
uint32_t ui32IOReg;
uint32_t ui32Config;
// Check the argument.
ASSERT(ui32IOId <= IOID_31);
ASSERT((ui32Pull == IOC_NO_IOPULL) ||
(ui32Pull == IOC_IOPULL_UP) ||
(ui32Pull == IOC_IOPULL_DOWN));
// Get the register address.
ui32IOReg = IOC_BASE + ( ui32IOId << 2 );
// Configure the IO.
ui32Config = HWREG(ui32IOReg);
ui32Config &= ~IOC_IOCFG0_PULL_CTL_M;
HWREG(ui32IOReg) = ui32Config | ui32Pull;
}
//*****************************************************************************
//
// Configure hysteresis on and IO port
//
//*****************************************************************************
void
IOCIOHystSet(uint32_t ui32IOId, uint32_t ui32Hysteresis)
{
uint32_t ui32IOReg;
uint32_t ui32Config;
// Check the arguments.
ASSERT(ui32IOId <= IOID_31);
ASSERT((ui32Hysteresis == IOC_HYST_ENABLE) ||
(ui32Hysteresis == IOC_HYST_DISABLE));
// Get the register address.
ui32IOReg = IOC_BASE + ( ui32IOId << 2 );
// Configure the IO.
ui32Config = HWREG(ui32IOReg);
ui32Config &= ~IOC_IOCFG0_HYST_EN;
HWREG(ui32IOReg) = ui32Config | ui32Hysteresis;
}
//*****************************************************************************
//
// Enable/disable IO port as input
//
//*****************************************************************************
void
IOCIOInputSet(uint32_t ui32IOId, uint32_t ui32Input)
{
uint32_t ui32IOReg;
uint32_t ui32Config;
// Check the arguments.
ASSERT(ui32IOId <= IOID_31);
ASSERT((ui32Input == IOC_INPUT_ENABLE) ||
(ui32Input == IOC_INPUT_DISABLE));
// Get the register address.
ui32IOReg = IOC_BASE + ( ui32IOId << 2 );
// Configure the IO.
ui32Config = HWREG(ui32IOReg);
ui32Config &= ~IOC_IOCFG0_IE;
HWREG(ui32IOReg) = ui32Config | ui32Input;
}
//*****************************************************************************
//
// Enable/disable the slew control on an IO port
//
//*****************************************************************************
void
IOCIOSlewCtrlSet(uint32_t ui32IOId, uint32_t ui32SlewEnable)
{
uint32_t ui32IOReg;
uint32_t ui32Config;
// Check the arguments.
ASSERT(ui32IOId <= IOID_31);
ASSERT((ui32SlewEnable == IOC_SLEW_ENABLE) ||
(ui32SlewEnable == IOC_SLEW_DISABLE));
// Get the register address.
ui32IOReg = IOC_BASE + ( ui32IOId << 2 );
// Configure the IO.
ui32Config = HWREG(ui32IOReg);
ui32Config &= ~IOC_IOCFG0_SLEW_RED;
HWREG(ui32IOReg) = ui32Config | ui32SlewEnable;
}
//*****************************************************************************
//
// Configure the drive strength and maximum current of an IO port
//
//*****************************************************************************
void
IOCIODrvStrengthSet(uint32_t ui32IOId, uint32_t ui32IOCurrent,
uint32_t ui32DrvStrength)
{
uint32_t ui32IOReg;
uint32_t ui32Config;
// Check the arguments.
ASSERT(ui32IOId <= IOID_31);
ASSERT((ui32IOCurrent == IOC_CURRENT_2MA) ||
(ui32IOCurrent == IOC_CURRENT_4MA) ||
(ui32IOCurrent == IOC_CURRENT_8MA));
ASSERT((ui32DrvStrength == IOC_STRENGTH_MIN) ||
(ui32DrvStrength == IOC_STRENGTH_MAX) ||
(ui32DrvStrength == IOC_STRENGTH_MED) ||
(ui32DrvStrength == IOC_STRENGTH_AUTO));
// Get the register address.
ui32IOReg = IOC_BASE + ( ui32IOId << 2 );
// Configure the IO.
ui32Config = HWREG(ui32IOReg);
ui32Config &= ~(IOC_IOCFG0_IOCURR_M | IOC_IOCFG0_IOSTR_M);
HWREG(ui32IOReg) = ui32Config | (ui32IOCurrent | ui32DrvStrength);
}
//*****************************************************************************
//
// Setup the Port ID for this IO
//
//*****************************************************************************
void
IOCIOPortIdSet(uint32_t ui32IOId, uint32_t ui32PortId)
{
uint32_t ui32IOReg;
uint32_t ui32Config;
// Check the arguments.
ASSERT(ui32IOId <= IOID_31);
ASSERT(ui32PortId <= IOC_PORT_RFC_GPI1);
// Get the register address.
ui32IOReg = IOC_BASE + ( ui32IOId << 2 );
// Configure the IO.
ui32Config = HWREG(ui32IOReg);
ui32Config &= ~IOC_IOCFG0_PORT_ID_M;
HWREG(ui32IOReg) = ui32Config | ui32PortId;
}
//*****************************************************************************
//
// Enables individual IO edge detect interrupt
//
//*****************************************************************************
void
IOCIntEnable(uint32_t ui32IOId)
{
uint32_t ui32IOReg;
uint32_t ui32Config;
// Check the arguments.
ASSERT(ui32IOId <= IOID_31);
// Get the register address.
ui32IOReg = IOC_BASE + ( ui32IOId << 2 );
// Enable the specified interrupt.
ui32Config = HWREG(ui32IOReg);
ui32Config |= IOC_IOCFG0_EDGE_IRQ_EN;
HWREG(ui32IOReg) = ui32Config;
}
//*****************************************************************************
//
// Disables individual IO edge interrupt sources
//
//*****************************************************************************
void
IOCIntDisable(uint32_t ui32IOId)
{
uint32_t ui32IOReg;
uint32_t ui32Config;
// Check the arguments.
ASSERT(ui32IOId <= IOID_31);
// Get the register address.
ui32IOReg = IOC_BASE + ( ui32IOId << 2 );
// Disable the specified interrupt.
ui32Config = HWREG(ui32IOReg);
ui32Config &= ~IOC_IOCFG0_EDGE_IRQ_EN;
HWREG(ui32IOReg) = ui32Config;
}
//*****************************************************************************
//
// Setup an IO for standard GPIO input
//
//*****************************************************************************
void
IOCPinTypeGpioInput(uint32_t ui32IOId)
{
// Check the arguments.
ASSERT(ui32IOId <= IOID_31);
// Setup the IO for standard input.
IOCPortConfigureSet(ui32IOId, IOC_PORT_GPIO, IOC_STD_INPUT);
// Enable input mode in the GPIO module.
GPIO_setOutputEnableDio(ui32IOId, GPIO_OUTPUT_DISABLE);
}
//*****************************************************************************
//
// Setup an IO for standard GPIO output
//
//*****************************************************************************
void
IOCPinTypeGpioOutput(uint32_t ui32IOId)
{
// Check the arguments.
ASSERT(ui32IOId <= IOID_31);
// Setup the IO for standard input.
IOCPortConfigureSet(ui32IOId, IOC_PORT_GPIO, IOC_STD_OUTPUT);
// Enable output mode in the GPIO module.
GPIO_setOutputEnableDio(ui32IOId, GPIO_OUTPUT_ENABLE);
}
//*****************************************************************************
//
// Configure a set of IOs for standard UART peripheral control
//
//*****************************************************************************
void
IOCPinTypeUart(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx,
uint32_t ui32Cts, uint32_t ui32Rts)
{
// Check the arguments.
ASSERT(ui32Base == UART0_BASE);
ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED));
ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED));
ASSERT((ui32Cts <= IOID_31) || (ui32Cts == IOID_UNUSED));
ASSERT((ui32Rts <= IOID_31) || (ui32Rts == IOID_UNUSED));
// Setup the IOs in the desired configuration.
if(ui32Rx != IOID_UNUSED)
{
IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_UART0_RX, IOC_STD_INPUT);
}
if(ui32Tx != IOID_UNUSED)
{
IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_UART0_TX, IOC_STD_OUTPUT);
}
if(ui32Cts != IOID_UNUSED)
{
IOCPortConfigureSet(ui32Cts, IOC_PORT_MCU_UART0_CTS, IOC_STD_INPUT);
}
if(ui32Rts != IOID_UNUSED)
{
IOCPortConfigureSet(ui32Rts, IOC_PORT_MCU_UART0_RTS, IOC_STD_OUTPUT);
}
}
//*****************************************************************************
//
// Configure a set of IOs for standard SSI peripheral master control
//
//*****************************************************************************
void
IOCPinTypeSsiMaster(uint32_t ui32Base, uint32_t ui32Rx,
uint32_t ui32Tx, uint32_t ui32Fss,
uint32_t ui32Clk)
{
// Check the arguments.
ASSERT((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE));
ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED));
ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED));
ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED));
ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED));
// Setup the IOs in the desired configuration.
if(ui32Base == SSI0_BASE)
{
if(ui32Rx != IOID_UNUSED)
{
IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI0_RX, IOC_STD_INPUT);
}
if(ui32Tx != IOID_UNUSED)
{
IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI0_TX, IOC_STD_OUTPUT);
}
if(ui32Fss != IOID_UNUSED)
{
IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI0_FSS, IOC_STD_OUTPUT);
}
if(ui32Clk != IOID_UNUSED)
{
IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI0_CLK, IOC_STD_OUTPUT);
}
}
else
{
if(ui32Rx != IOID_UNUSED)
{
IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI1_RX, IOC_STD_INPUT);
}
if(ui32Tx != IOID_UNUSED)
{
IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI1_TX, IOC_STD_OUTPUT);
}
if(ui32Fss != IOID_UNUSED)
{
IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI1_FSS, IOC_STD_OUTPUT);
}
if(ui32Clk != IOID_UNUSED)
{
IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI1_CLK, IOC_STD_OUTPUT);
}
}
}
//*****************************************************************************
//
// Configure a set of IOs for standard SSI peripheral slave control
//
//*****************************************************************************
void
IOCPinTypeSsiSlave(uint32_t ui32Base, uint32_t ui32Rx,
uint32_t ui32Tx, uint32_t ui32Fss,
uint32_t ui32Clk)
{
// Check the arguments.
ASSERT((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE));
ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED));
ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED));
ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED));
ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED));
// Setup the IOs in the desired configuration.
if(ui32Base == SSI0_BASE)
{
if(ui32Rx != IOID_UNUSED)
{
IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI0_RX, IOC_STD_INPUT);
}
if(ui32Tx != IOID_UNUSED)
{
IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI0_TX, IOC_STD_OUTPUT);
}
if(ui32Fss != IOID_UNUSED)
{
IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI0_FSS, IOC_STD_INPUT);
}
if(ui32Clk != IOID_UNUSED)
{
IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI0_CLK, IOC_STD_INPUT);
}
}
else
{
if(ui32Rx != IOID_UNUSED)
{
IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI1_RX, IOC_STD_INPUT);
}
if(ui32Tx != IOID_UNUSED)
{
IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI1_TX, IOC_STD_OUTPUT);
}
if(ui32Fss != IOID_UNUSED)
{
IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI1_FSS, IOC_STD_INPUT);
}
if(ui32Clk != IOID_UNUSED)
{
IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI1_CLK, IOC_STD_INPUT);
}
}
}
//*****************************************************************************
//
// Configure a set of IOs for standard I2C peripheral control
//
//*****************************************************************************
void
IOCPinTypeI2c(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk)
{
uint32_t ui32IOConfig;
// Check the arguments.
ASSERT((ui32Data <= IOID_31) || (ui32Data == IOID_UNUSED));
ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED));
// Define the IO configuration parameters.
ui32IOConfig = IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_IOPULL_UP |
IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE |
IOC_INT_DISABLE | IOC_IOMODE_OPEN_DRAIN_NORMAL |
IOC_NO_WAKE_UP | IOC_INPUT_ENABLE;
// Setup the IOs in the desired configuration.
IOCPortConfigureSet(ui32Data, IOC_PORT_MCU_I2C_MSSDA, ui32IOConfig);
IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_I2C_MSSCL, ui32IOConfig);
}
//*****************************************************************************
//
// Configure an IO for AUX control
//
//*****************************************************************************
void
IOCPinTypeAux(uint32_t ui32IOId)
{
// Check the arguments.
ASSERT((ui32IOId <= IOID_31) || (ui32IOId == IOID_UNUSED));
// Setup the IO.
IOCPortConfigureSet(ui32IOId, IOC_PORT_AUX_IO, IOC_STD_INPUT);
}

1225
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.h
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ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ioc_doc.h
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@ -1,92 +0,0 @@
/******************************************************************************
* Filename: ioc_doc.h
* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016)
* Revision: 45971
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//! \addtogroup ioc_api
//! @{
//! \section sec_ioc Introduction
//!
//! The Input/Output Controller (IOC) controls the functionality of the pins (called DIO).
//! The IOC consists of two APIs:
//! - MCU IOC API selects which peripheral module is connected to the individual DIO and thus allowed to control it.
//! It also controls individual drive strength, slew rate, pull-up/pull-down, edge detection, etc.
//! - AON IOC API controls the general drive strength definitions, IO latches, and if the LF clock is
//! routed to a DIO for external use.
//!
//! For more information on the AON IOC see the [AON IOC API](\ref aonioc_api).
//!
//! \note The output driver of a DIO is not configured by the IOC API (except for drive strength); instead, it is controlled by the
//! peripheral module which is selected to control the DIO.
//!
//! A DIO is considered "software controlled" if it is configured for GPIO control which allows the
//! System CPU to set the value of the DIO via the [GPIO API](\ref gpio_api). Alternatively, a DIO
//! can be "hardware controlled" if it is controlled by other modules than GPIO.
//!
//! \section sec_ioc_api API
//!
//! The API functions can be grouped like this:
//!
//! Configure all settings at the same time:
//! - \ref IOCPortConfigureSet()
//! - \ref IOCPortConfigureGet()
//!
//! Configure individual settings:
//! - \ref IOCIODrvStrengthSet()
//! - \ref IOCIOHystSet()
//! - \ref IOCIOInputSet()
//! - \ref IOCIOIntSet()
//! - \ref IOCIOModeSet()
//! - \ref IOCIOPortIdSet()
//! - \ref IOCIOPortPullSet()
//! - \ref IOCIOShutdownSet()
//! - \ref IOCIOSlewCtrlSet()
//!
//! Handle edge detection events:
//! - \ref IOCIntEnable()
//! - \ref IOCIntDisable()
//! - \ref IOCIntClear()
//! - \ref IOCIntStatus()
//! - \ref IOCIntRegister()
//! - \ref IOCIntUnregister()
//!
//! Configure IOCs for typical use cases (can also be used as example code):
//! - \ref IOCPinTypeAux()
//! - \ref IOCPinTypeGpioInput()
//! - \ref IOCPinTypeGpioOutput()
//! - \ref IOCPinTypeI2c()
//! - \ref IOCPinTypeSsiMaster()
//! - \ref IOCPinTypeSsiSlave()
//! - \ref IOCPinTypeUart()
//!
//! @}

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ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/osc.c
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@ -1,625 +0,0 @@
/******************************************************************************
* Filename: osc.c
* Revised: 2019-02-14 09:35:31 +0100 (Thu, 14 Feb 2019)
* Revision: 54539
*
* Description: Driver for setting up the system Oscillators
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "../inc/hw_types.h"
#include "../inc/hw_ccfg.h"
#include "../inc/hw_fcfg1.h"
#include "aon_batmon.h"
#include "aon_rtc.h"
#include "osc.h"
#include "setup_rom.h"
//*****************************************************************************
//
// Handle support for DriverLib in ROM:
// This section will undo prototype renaming made in the header file
//
//*****************************************************************************
#if !defined(DOXYGEN)
#undef OSCClockSourceSet
#define OSCClockSourceSet NOROM_OSCClockSourceSet
#undef OSCClockSourceGet
#define OSCClockSourceGet NOROM_OSCClockSourceGet
#undef OSCHF_GetStartupTime
#define OSCHF_GetStartupTime NOROM_OSCHF_GetStartupTime
#undef OSCHF_TurnOnXosc
#define OSCHF_TurnOnXosc NOROM_OSCHF_TurnOnXosc
#undef OSCHF_AttemptToSwitchToXosc
#define OSCHF_AttemptToSwitchToXosc NOROM_OSCHF_AttemptToSwitchToXosc
#undef OSCHF_SwitchToRcOscTurnOffXosc
#define OSCHF_SwitchToRcOscTurnOffXosc NOROM_OSCHF_SwitchToRcOscTurnOffXosc
#undef OSCHF_DebugGetCrystalAmplitude
#define OSCHF_DebugGetCrystalAmplitude NOROM_OSCHF_DebugGetCrystalAmplitude
#undef OSCHF_DebugGetExpectedAverageCrystalAmplitude
#define OSCHF_DebugGetExpectedAverageCrystalAmplitude NOROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude
#undef OSC_HPOSC_Debug_InitFreqOffsetParams
#define OSC_HPOSC_Debug_InitFreqOffsetParams NOROM_OSC_HPOSC_Debug_InitFreqOffsetParams
#undef OSC_HPOSCInitializeFrequencyOffsetParameters
#define OSC_HPOSCInitializeFrequencyOffsetParameters NOROM_OSC_HPOSCInitializeFrequencyOffsetParameters
#undef OSC_HPOSCRelativeFrequencyOffsetGet
#define OSC_HPOSCRelativeFrequencyOffsetGet NOROM_OSC_HPOSCRelativeFrequencyOffsetGet
#undef OSC_AdjustXoscHfCapArray
#define OSC_AdjustXoscHfCapArray NOROM_OSC_AdjustXoscHfCapArray
#undef OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert
#define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert NOROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert
#undef OSC_HPOSCRtcCompensate
#define OSC_HPOSCRtcCompensate NOROM_OSC_HPOSCRtcCompensate
#endif
//*****************************************************************************
//
// Global HPOSC curve fitting polynomials
// Parameters found/calculated when calling function
// OSC_HPOSCInitializeFrequencyOffsetParameters()
// (or OSC_HPOSC_Debug_InitFreqOffsetParams() used for debugging only)
// These global variables must be updated before using HPOSC
//
//*****************************************************************************
static int16_t _hpOscPolynomials[ 4 ];
//*****************************************************************************
//
// OSCHF switch time calculator defines and globals
//
//*****************************************************************************
#define RTC_CV_TO_MS(x) (( 1000 * ( x )) >> 16 )
#define RTC_CV_TO_US(x) (( 1000000 * ( x )) >> 16 )
typedef struct {
uint32_t previousStartupTimeInUs ;
uint32_t timeXoscOff_CV ;
uint32_t timeXoscOn_CV ;
uint32_t timeXoscStable_CV ;
int32_t tempXoscOff ;
} OscHfGlobals_t;
static OscHfGlobals_t oscHfGlobals;
//*****************************************************************************
//
// Configure the oscillator input to the a source clock.
//
//*****************************************************************************
void
OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc)
{
// Check the arguments.
ASSERT((ui32SrcClk & OSC_SRC_CLK_LF) ||
(ui32SrcClk & OSC_SRC_CLK_HF));
ASSERT((ui32Osc == OSC_RCOSC_HF) ||
(ui32Osc == OSC_RCOSC_LF) ||
(ui32Osc == OSC_XOSC_HF) ||
(ui32Osc == OSC_XOSC_LF));
// Request the high frequency source clock (using 24 MHz XTAL)
if(ui32SrcClk & OSC_SRC_CLK_HF)
{
// Enable the HF XTAL as HF clock source
DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0,
DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M,
DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S,
ui32Osc);
}
// Configure the low frequency source clock.
if(ui32SrcClk & OSC_SRC_CLK_LF)
{
// Change the clock source.
DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0,
DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M,
DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S,
ui32Osc);
}
}
//*****************************************************************************
//
// Get the source clock settings
//
//*****************************************************************************
uint32_t
OSCClockSourceGet(uint32_t ui32SrcClk)
{
uint32_t ui32ClockSource;
// Check the arguments.
ASSERT((ui32SrcClk & OSC_SRC_CLK_LF) ||
(ui32SrcClk & OSC_SRC_CLK_HF));
// Return the source for the selected clock.
if(ui32SrcClk == OSC_SRC_CLK_LF)
{
ui32ClockSource = DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0,
DDI_0_OSC_STAT0_SCLK_LF_SRC_M,
DDI_0_OSC_STAT0_SCLK_LF_SRC_S);
}
else
{
ui32ClockSource = DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0,
DDI_0_OSC_STAT0_SCLK_HF_SRC_M,
DDI_0_OSC_STAT0_SCLK_HF_SRC_S);
}
return (ui32ClockSource);
}
//*****************************************************************************
//
// Returns maximum startup time (in microseconds) of XOSC_HF
//
//*****************************************************************************
uint32_t
OSCHF_GetStartupTime( uint32_t timeUntilWakeupInMs )
{
uint32_t deltaTimeSinceXoscOnInMs ;
int32_t deltaTempSinceXoscOn ;
uint32_t newStartupTimeInUs ;
deltaTimeSinceXoscOnInMs = RTC_CV_TO_MS( AONRTCCurrentCompareValueGet() - oscHfGlobals.timeXoscOn_CV );
deltaTempSinceXoscOn = AONBatMonTemperatureGetDegC() - oscHfGlobals.tempXoscOff;
if ( deltaTempSinceXoscOn < 0 ) {
deltaTempSinceXoscOn = -deltaTempSinceXoscOn;
}
if ( (( timeUntilWakeupInMs + deltaTimeSinceXoscOnInMs ) > 3000 ) ||
( deltaTempSinceXoscOn > 5 ) ||
( oscHfGlobals.timeXoscStable_CV < oscHfGlobals.timeXoscOn_CV ) ||
( oscHfGlobals.previousStartupTimeInUs == 0 ) )
{
newStartupTimeInUs = 2000;
if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) == 0 ) {
newStartupTimeInUs = (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) &
CCFG_MODE_CONF_1_XOSC_MAX_START_M ) >>
CCFG_MODE_CONF_1_XOSC_MAX_START_S ) * 125;
// Note: CCFG startup time is "in units of 100us" adding 25% margin results in *125
}
} else {
newStartupTimeInUs = RTC_CV_TO_US( oscHfGlobals.timeXoscStable_CV - oscHfGlobals.timeXoscOn_CV );
newStartupTimeInUs += ( newStartupTimeInUs >> 2 ); // Add 25 percent margin
if ( newStartupTimeInUs < oscHfGlobals.previousStartupTimeInUs ) {
newStartupTimeInUs = oscHfGlobals.previousStartupTimeInUs;
}
}
if ( newStartupTimeInUs < 200 ) {
newStartupTimeInUs = 200;
}
if ( newStartupTimeInUs > 4000 ) {
newStartupTimeInUs = 4000;
}
return ( newStartupTimeInUs );
}
//*****************************************************************************
//
// Turns on XOSC_HF (but without switching to XOSC_HF)
//
//*****************************************************************************
void
OSCHF_TurnOnXosc( void )
{
#if ( defined( ROM_OSCClockSourceSet ))
ROM_OSCClockSourceSet( OSC_SRC_CLK_HF, OSC_XOSC_HF );
#else
OSCClockSourceSet( OSC_SRC_CLK_HF, OSC_XOSC_HF );
#endif
oscHfGlobals.timeXoscOn_CV = AONRTCCurrentCompareValueGet();
}
//*****************************************************************************
//
// Switch to XOSC_HF if XOSC_HF is ready.
//
//*****************************************************************************
bool
OSCHF_AttemptToSwitchToXosc( void )
{
uint32_t startupTimeInUs;
uint32_t prevLimmit25InUs;
#if ( defined( ROM_OSCClockSourceGet ))
if ( ROM_OSCClockSourceGet( OSC_SRC_CLK_HF ) == OSC_XOSC_HF )
#else
if ( OSCClockSourceGet( OSC_SRC_CLK_HF ) == OSC_XOSC_HF )
#endif
{
// Already on XOSC - nothing to do
return ( 1 );
}
if ( OSCHfSourceReady()) {
OSCHfSourceSwitch();
// Store startup time, but limit to 25 percent reduction each time.
oscHfGlobals.timeXoscStable_CV = AONRTCCurrentCompareValueGet();
startupTimeInUs = RTC_CV_TO_US( oscHfGlobals.timeXoscStable_CV - oscHfGlobals.timeXoscOn_CV );
prevLimmit25InUs = oscHfGlobals.previousStartupTimeInUs;
prevLimmit25InUs -= ( prevLimmit25InUs >> 2 ); // 25 percent margin
oscHfGlobals.previousStartupTimeInUs = startupTimeInUs;
if ( prevLimmit25InUs > startupTimeInUs ) {
oscHfGlobals.previousStartupTimeInUs = prevLimmit25InUs;
}
return ( 1 );
}
return ( 0 );
}
//*****************************************************************************
//
// Switch to RCOSC_HF and turn off XOSC_HF
//
//*****************************************************************************
void
OSCHF_SwitchToRcOscTurnOffXosc( void )
{
#if ( defined( ROM_OSCClockSourceSet ))
ROM_OSCClockSourceSet( OSC_SRC_CLK_HF, OSC_RCOSC_HF );
#else
OSCClockSourceSet( OSC_SRC_CLK_HF, OSC_RCOSC_HF );
#endif
// Do the switching if not already running on RCOSC_HF
#if ( defined( ROM_OSCClockSourceGet ))
if ( ROM_OSCClockSourceGet( OSC_SRC_CLK_HF ) != OSC_RCOSC_HF )
#else
if ( OSCClockSourceGet( OSC_SRC_CLK_HF ) != OSC_RCOSC_HF )
#endif
{
OSCHfSourceSwitch();
}
oscHfGlobals.timeXoscOff_CV = AONRTCCurrentCompareValueGet();
oscHfGlobals.tempXoscOff = AONBatMonTemperatureGetDegC();
}
//*****************************************************************************
//
// Adjust the XOSC HF cap array relative to the factory setting
//
//*****************************************************************************
void
OSC_AdjustXoscHfCapArray( int32_t capArrDelta )
{
// read the MODE_CONF register in CCFG
uint32_t ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF );
// Clear CAP_MODE and the CAPARRAY_DELATA field
ccfg_ModeConfReg &= ~( CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M | CCFG_MODE_CONF_XOSC_CAP_MOD_M );
// Insert new delta value
ccfg_ModeConfReg |= ((((uint32_t)capArrDelta) << CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ) & CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M );
// Update the HW register with the new delta value
DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, SetupGetTrimForAnabypassValue1( ccfg_ModeConfReg ));
}
//*****************************************************************************
//
// Initialize the frequency offset curve fitting parameters
// These are either picked diretly from FCFG1:FREQ_OFFSET & FCFG1:MISC_CONF_2 or
// calculated based on the FCFG1:HPOSC_MEAS_x parameters.
//
//*****************************************************************************
// Using the following hardcoded constants (Using temporary constants for now)
#define D1OFFSET_p25C -24
#define D2OFFSET_p85C -36
#define D3OFFSET_m40C 18
#define P3_POLYNOMIAL -47
#define N_INSERTIONS 3
typedef struct {
int32_t dFreq ;
int32_t temp ;
} insertion_t ;
static void
InitializeMeasurmentSet( insertion_t * pInsertion, uint32_t registerAddress, int32_t deltaOffset, int32_t p3PolOffset )
{
// Doing the following adjustment to the deltaFrequence before finding the polynomials P0, P1, P2
// Dx = Dx + DxOFFSET - ((P3*Tx^3)/2^18)
uint32_t insertionData = HWREG( registerAddress );
pInsertion->dFreq = (((int32_t)( insertionData << ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_D1_W - FCFG1_HPOSC_MEAS_1_HPOSC_D1_S )))
>> ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_D1_W ));
pInsertion->temp = (((int32_t)( insertionData << ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_T1_W - FCFG1_HPOSC_MEAS_1_HPOSC_T1_S )))
>> ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_T1_W ));
pInsertion->dFreq = pInsertion->dFreq + deltaOffset - (( p3PolOffset * pInsertion->temp * pInsertion->temp * pInsertion->temp ) >> 18 );
}
static void
FindPolynomialsAndUpdateGlobals( insertion_t * pMeasurment )
{
uint32_t loopCount ;
int32_t polynomial_0 ;
int32_t polynomial_1 ;
int32_t polynomial_2 ;
int32_t Syi_ = 0 ;
int32_t Sxi_ = 0 ;
int32_t Sxi2_ = 0 ;
int32_t Sxiyi_ = 0 ;
int32_t Sxi2yi_ = 0 ;
int32_t Sxi3_ = 0 ;
int32_t Sxi4_ = 0 ;
for ( loopCount = 0 ; loopCount < N_INSERTIONS ; loopCount++ ) {
int32_t x ;
int32_t x2 ;
int32_t y ;
x = pMeasurment[ loopCount ].temp ;
x2 = ( x * x );
y = pMeasurment[ loopCount ].dFreq ;
Syi_ += ( y );
Sxi_ += ( x );
Sxi2_ += ( x2 );
Sxiyi_ += ( x * y );
Sxi2yi_ += ( x2 * y );
Sxi3_ += ( x2 * x );
Sxi4_ += ( x2 * x2 );
}
int32_t Sxx_ = ( Sxi2_ * N_INSERTIONS ) - ( Sxi_ * Sxi_ );
int32_t Sxy_ = ( Sxiyi_ * N_INSERTIONS ) - ( Sxi_ * Syi_ );
int32_t Sxx2_ = ( Sxi3_ * N_INSERTIONS ) - ( Sxi_ * Sxi2_ );
int32_t Sx2y_ = ( Sxi2yi_ * N_INSERTIONS ) - ( Sxi2_ * Syi_ );
int32_t Sx2x2_ = ( Sxi4_ * N_INSERTIONS ) - ( Sxi2_ * Sxi2_ );
int32_t divisor = ((((int64_t) Sxx_ * Sx2x2_ ) - ((int64_t) Sxx2_ * Sxx2_ )) + (1<<9)) >> 10 ;
if ( divisor == 0 ) {
polynomial_2 = 0 ;
polynomial_1 = 0 ;
} else {
polynomial_2 = (((int64_t) Sx2y_ * Sxx_ ) - ((int64_t) Sxy_ * Sxx2_ )) / divisor ;
polynomial_1 = (((int64_t) Sxy_ * Sx2x2_ ) - ((int64_t) Sx2y_ * Sxx2_ )) / divisor ;
}
polynomial_0 = ( Syi_ - (((( polynomial_1 * Sxi_ ) + ( polynomial_2 * Sxi2_ )) + (1<<9)) >> 10 )) / N_INSERTIONS ;
polynomial_1 = ( polynomial_1 + (1<<6)) >> 7 ;
_hpOscPolynomials[ 0 ] = polynomial_0 ;
_hpOscPolynomials[ 1 ] = polynomial_1 ;
_hpOscPolynomials[ 2 ] = polynomial_2 ;
_hpOscPolynomials[ 3 ] = P3_POLYNOMIAL ;
}
//*****************************************************************************
// Degub function to calculate the HPOSC polynomials for experimental data sets.
//*****************************************************************************
void
OSC_HPOSC_Debug_InitFreqOffsetParams( HposcDebugData_t * pDebugData )
{
// Calculate the curve fitting parameters from temp insertion measurements
// But first adjust the measurements with constants found in characterization
insertion_t pMeasurment[ 3 ];
InitializeMeasurmentSet( &pMeasurment[ 0 ], (uint32_t)&pDebugData->meas_1, pDebugData->offsetD1, pDebugData->polyP3 );
InitializeMeasurmentSet( &pMeasurment[ 1 ], (uint32_t)&pDebugData->meas_2, pDebugData->offsetD2, pDebugData->polyP3 );
InitializeMeasurmentSet( &pMeasurment[ 2 ], (uint32_t)&pDebugData->meas_3, pDebugData->offsetD3, pDebugData->polyP3 );
FindPolynomialsAndUpdateGlobals( pMeasurment );
}
//*****************************************************************************
// The general HPOSC initialization function - Must always be called before using HPOSC
//*****************************************************************************
void
OSC_HPOSCInitializeFrequencyOffsetParameters( void )
{
{
// Calculate the curve fitting parameters from temp insertion measurements
// But first adjust the measurements with constants found in characterization
insertion_t pMeasurment[ 3 ];
InitializeMeasurmentSet( &pMeasurment[ 0 ], FCFG1_BASE + FCFG1_O_HPOSC_MEAS_1, D1OFFSET_p25C, P3_POLYNOMIAL );
InitializeMeasurmentSet( &pMeasurment[ 1 ], FCFG1_BASE + FCFG1_O_HPOSC_MEAS_2, D2OFFSET_p85C, P3_POLYNOMIAL );
InitializeMeasurmentSet( &pMeasurment[ 2 ], FCFG1_BASE + FCFG1_O_HPOSC_MEAS_3, D3OFFSET_m40C, P3_POLYNOMIAL );
FindPolynomialsAndUpdateGlobals( pMeasurment );
}
}
//*****************************************************************************
//
// Calculate the temperature dependent relative frequency offset of HPOSC
//
//*****************************************************************************
int32_t
OSC_HPOSCRelativeFrequencyOffsetGet( int32_t tempDegC )
{
// Estimate HPOSC frequency, using temperature and curve fitting parameters
int32_t paramP0 = _hpOscPolynomials[ 0 ];
int32_t paramP1 = _hpOscPolynomials[ 1 ];
int32_t paramP2 = _hpOscPolynomials[ 2 ];
int32_t paramP3 = _hpOscPolynomials[ 3 ];
// Now we can find the HPOSC freq offset, given as a signed variable d, expressed by:
//
// F_HPOSC = F_nom * (1 + d/(2^22)) , where: F_HPOSC = HPOSC frequency
// F_nom = nominal clock source frequency (e.g. 48.000 MHz)
// d = describes relative freq offset
// We can estimate the d variable, using temperature compensation parameters:
//
// d = P0 + P1*(t - T0) + P2*(t - T0)^2 + P3*(t - T0)^3, where: P0,P1,P2,P3 are curve fitting parameters from FCFG1
// t = current temperature (from temp sensor) in deg C
// T0 = 27 deg C (fixed temperature constant)
int32_t tempDelta = (tempDegC - 27);
int32_t tempDeltaX2 = tempDelta * tempDelta;
int32_t d = paramP0 + ((tempDelta*paramP1)>>3) + ((tempDeltaX2*paramP2)>>10) + ((tempDeltaX2*tempDelta*paramP3)>>18);
return ( d );
}
//*****************************************************************************
//
// Converts the relative frequency offset of HPOSC to the RF Core parameter format.
//
//*****************************************************************************
int16_t
OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HPOSC_RelFreqOffset )
{
// The input argument, hereby referred to simply as "d", describes the frequency offset
// of the HPOSC relative to the nominal frequency in this way:
//
// F_HPOSC = F_nom * (1 + d/(2^22))
//
// But for use by the radio, to compensate the frequency error, we need to find the
// frequency offset "rfcFreqOffset" defined in the following format:
//
// F_nom = F_HPOSC * (1 + rfCoreFreqOffset/(2^22))
//
// To derive "rfCoreFreqOffset" from "d" we combine the two above equations and get:
//
// (1 + rfCoreFreqOffset/(2^22)) = (1 + d/(2^22))^-1
//
// Which can be rewritten into:
//
// rfCoreFreqOffset = -d*(2^22) / ((2^22) + d)
//
// = -d * [ 1 / (1 + d/(2^22)) ]
//
// To avoid doing a 64-bit division due to the (1 + d/(2^22))^-1 expression,
// we can use Taylor series (Maclaurin series) to approximate it:
//
// 1 / (1 - x) ~= 1 + x + x^2 + x^3 + x^4 + ... etc (Maclaurin series)
//
// In our case, we have x = - d/(2^22), and we only include up to the first
// order term of the series, as the second order term ((d^2)/(2^44)) is very small:
//
// freqError ~= -d + d^2/(2^22) (+ small approximation error)
//
// The approximation error is negligible for our use.
int32_t rfCoreFreqOffset = -HPOSC_RelFreqOffset + (( HPOSC_RelFreqOffset * HPOSC_RelFreqOffset ) >> 22 );
return ( rfCoreFreqOffset );
}
//*****************************************************************************
//
// Compensate the RTC increment based on the relative frequency offset of HPOSC
//
//*****************************************************************************
void
OSC_HPOSCRtcCompensate( int32_t relFreqOffset )
{
uint32_t rtcSubSecInc;
uint32_t lfClkFrequency;
uint32_t hfFreq;
int64_t calcFactor;
// Calculate SCLK_HF frequency, defined as:
// hfFreq = 48000000 * (1 + relFreqOffset/(2^22))
if( relFreqOffset >= 0 )
{
calcFactor = ( ( 48000000 * (int64_t)relFreqOffset ) + 0x200000 ) / 0x400000;
}
else
{
calcFactor = ( ( 48000000 * (int64_t)relFreqOffset ) - 0x200000 ) / 0x400000;
}
hfFreq = 48000000 + calcFactor;
// Calculate SCLK_LF frequency, defined as SCLK_LF_FREQ = SCLK_HF_FREQ / 1536
lfClkFrequency = ( hfFreq + 768 ) / 1536;
// Calculate SUBSECINC, defined as: SUBSECINC = 2^38 / SCLK_LF_FREQ
rtcSubSecInc = 0x4000000000 / lfClkFrequency;
/* Update SUBSECINC value */
SetupSetAonRtcSubSecInc(rtcSubSecInc);
}
//*****************************************************************************
//
// Get crystal amplitude (assuming crystal is running).
//
//*****************************************************************************
uint32_t
OSCHF_DebugGetCrystalAmplitude( void )
{
uint32_t oscCfgRegCopy ;
uint32_t startTime ;
uint32_t deltaTime ;
uint32_t ampValue ;
// The specified method is as follows:
// 1. Set minimum interval between oscillator amplitude calibrations.
// (Done by setting PER_M=0 and PER_E=1)
// 2. Wait approximately 4 milliseconds in order to measure over a
// moderately large number of calibrations.
// 3. Read out the crystal amplitude value from the peek detector.
// 4. Restore original oscillator amplitude calibrations interval.
// 5. Return crystal amplitude value converted to millivolt.
oscCfgRegCopy = HWREG( AON_PMCTL_BASE + AON_PMCTL_O_OSCCFG );
HWREG( AON_PMCTL_BASE + AON_PMCTL_O_OSCCFG ) = ( 1 << AON_PMCTL_OSCCFG_PER_E_S );
startTime = AONRTCCurrentCompareValueGet();
do {
deltaTime = AONRTCCurrentCompareValueGet() - startTime;
} while ( deltaTime < ((uint32_t)( 0.004 * FACTOR_SEC_TO_COMP_VAL_FORMAT )));
ampValue = ( HWREG( AUX_DDI0_OSC_BASE + DDI_0_OSC_O_STAT1 ) &
DDI_0_OSC_STAT1_HPM_UPDATE_AMP_M ) >>
DDI_0_OSC_STAT1_HPM_UPDATE_AMP_S ;
HWREG( AON_PMCTL_BASE + AON_PMCTL_O_OSCCFG ) = oscCfgRegCopy;
return ( ampValue * 15 );
}
//*****************************************************************************
//
// Get the expected average crystal amplitude.
//
//*****************************************************************************
uint32_t
OSCHF_DebugGetExpectedAverageCrystalAmplitude( void )
{
uint32_t ampCompTh1 ;
uint32_t highThreshold ;
uint32_t lowThreshold ;
ampCompTh1 = HWREG( AUX_DDI0_OSC_BASE + DDI_0_OSC_O_AMPCOMPTH1 );
highThreshold = ( ampCompTh1 & DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_M ) >>
DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S ;
lowThreshold = ( ampCompTh1 & DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_M ) >>
DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S ;
return ((( highThreshold + lowThreshold ) * 15 ) >> 1 );
}

730
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/osc.h
View file

@ -1,730 +0,0 @@
/******************************************************************************
* Filename: osc.h
* Revised: 2019-02-14 09:35:31 +0100 (Thu, 14 Feb 2019)
* Revision: 54539
*
* Description: Defines and prototypes for the system oscillator control.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup system_control_group
//! @{
//! \addtogroup osc_api
//! @{
//
//*****************************************************************************
#ifndef __OSC_H__
#define __OSC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdbool.h>
#include <stdint.h>
#include "../inc/hw_aon_pmctl.h"
#include "../inc/hw_ccfg.h"
#include "../inc/hw_fcfg1.h"
#include "../inc/hw_types.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_ddi.h"
#include "../inc/hw_ddi_0_osc.h"
#include "rom.h"
#include "ddi.h"
#include "debug.h"
//*****************************************************************************
//
// Support for DriverLib in ROM:
// This section renames all functions that are not "static inline", so that
// calling these functions will default to implementation in flash. At the end
// of this file a second renaming will change the defaults to implementation in
// ROM for available functions.
//
// To force use of the implementation in flash, e.g. for debugging:
// - Globally: Define DRIVERLIB_NOROM at project level
// - Per function: Use prefix "NOROM_" when calling the function
//
//*****************************************************************************
#if !defined(DOXYGEN)
#define OSCClockSourceSet NOROM_OSCClockSourceSet
#define OSCClockSourceGet NOROM_OSCClockSourceGet
#define OSCHF_GetStartupTime NOROM_OSCHF_GetStartupTime
#define OSCHF_TurnOnXosc NOROM_OSCHF_TurnOnXosc
#define OSCHF_AttemptToSwitchToXosc NOROM_OSCHF_AttemptToSwitchToXosc
#define OSCHF_SwitchToRcOscTurnOffXosc NOROM_OSCHF_SwitchToRcOscTurnOffXosc
#define OSCHF_DebugGetCrystalAmplitude NOROM_OSCHF_DebugGetCrystalAmplitude
#define OSCHF_DebugGetExpectedAverageCrystalAmplitude NOROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude
#define OSC_HPOSC_Debug_InitFreqOffsetParams NOROM_OSC_HPOSC_Debug_InitFreqOffsetParams
#define OSC_HPOSCInitializeFrequencyOffsetParameters NOROM_OSC_HPOSCInitializeFrequencyOffsetParameters
#define OSC_HPOSCRelativeFrequencyOffsetGet NOROM_OSC_HPOSCRelativeFrequencyOffsetGet
#define OSC_AdjustXoscHfCapArray NOROM_OSC_AdjustXoscHfCapArray
#define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert NOROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert
#define OSC_HPOSCRtcCompensate NOROM_OSC_HPOSCRtcCompensate
#endif
//*****************************************************************************
//
// Defines for the High Frequency XTAL Power mode
//
//*****************************************************************************
#define LOW_POWER_XOSC 1
#define HIGH_POWER_XOSC 0
//*****************************************************************************
//
// Defines for the High Frequency XTAL Power mode
//
//*****************************************************************************
#define OSC_SRC_CLK_HF 0x00000001
#define OSC_SRC_CLK_LF 0x00000004
#define OSC_RCOSC_HF 0x00000000
#define OSC_XOSC_HF 0x00000001
#define OSC_RCOSC_LF 0x00000002
#define OSC_XOSC_LF 0x00000003
#define SCLK_HF_RCOSC_HF 0
#define SCLK_HF_XOSC_HF 1
#define SCLK_LF_FROM_RCOSC_HF 0
#define SCLK_LF_FROM_XOSC_HF 1
#define SCLK_LF_FROM_RCOSC_LF 2
#define SCLK_LF_FROM_XOSC_LF 3
//*****************************************************************************
//
// API Functions and prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Set Power Mode for High Frequency XTAL Oscillator.
//!
//! \param ui32Mode is the power mode for the HF XTAL.
//! - \ref LOW_POWER_XOSC
//! - \ref HIGH_POWER_XOSC
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
OSCXHfPowerModeSet(uint32_t ui32Mode)
{
// Check the arguments.
ASSERT((ui32Mode == LOW_POWER_XOSC) ||
(ui32Mode == HIGH_POWER_XOSC));
// Change the power mode.
DDI16BitWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE,
ui32Mode);
}
//*****************************************************************************
//
//! \brief Enables OSC clock loss event detection.
//!
//! Enables the clock loss event flag to be raised if a clock loss is detected.
//!
//! \note OSC clock loss event must be disabled before SCLK_LF clock source is
//! changed (by calling \ref OSCClockSourceSet()) and remain disabled until the
//! change is confirmed (by calling \ref OSCClockSourceGet()).
//!
//! \return None
//!
//! \sa \ref OSCClockLossEventDisable()
//
//*****************************************************************************
__STATIC_INLINE void
OSCClockLossEventEnable( void )
{
DDI16BitfieldWrite( AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0,
DDI_0_OSC_CTL0_CLK_LOSS_EN_M,
DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 1 );
}
//*****************************************************************************
//
//! \brief Disables OSC clock loss event detection.
//!
//! Disabling the OSC clock loss event does also clear the clock loss event flag.
//!
//! \note OSC clock loss event must be disabled before SCLK_LF clock source is
//! changed (by calling \ref OSCClockSourceSet()) and remain disabled until the
//! change is confirmed (by calling \ref OSCClockSourceGet()).
//!
//! \return None
//!
//! \sa \ref OSCClockLossEventEnable()
//
//*****************************************************************************
__STATIC_INLINE void
OSCClockLossEventDisable( void )
{
DDI16BitfieldWrite( AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0,
DDI_0_OSC_CTL0_CLK_LOSS_EN_M,
DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 0 );
}
//*****************************************************************************
//
//! \brief Configure the oscillator input to the a source clock.
//!
//! Use this function to set the oscillator source for one or more of the
//! system source clocks.
//!
//! When selecting the high frequency clock source (OSC_SRC_CLK_HF), this function will not do
//! the actual switch. Enabling the high frequency XTAL can take several hundred
//! micro seconds, so the actual switch is done in a separate function, \ref OSCHfSourceSwitch(),
//! leaving System CPU free to perform other tasks as the XTAL starts up.
//!
//! \note The High Frequency (\ref OSC_SRC_CLK_HF) can only be derived from the
//! high frequency oscillator. The Low Frequency source clock (\ref OSC_SRC_CLK_LF)
//! can be derived from all 4 oscillators.
//!
//! \note If enabling \ref OSC_XOSC_LF it is not safe to go to powerdown/shutdown
//! until the LF clock is running which can be checked using \ref OSCClockSourceGet().
//!
//! \note Clock loss reset generation must be disabled before SCLK_LF (\ref OSC_SRC_CLK_LF)
//! clock source is changed and remain disabled until the change is confirmed.
//!
//! \param ui32SrcClk is the source clocks to configure.
//! - \ref OSC_SRC_CLK_HF
//! - \ref OSC_SRC_CLK_LF
//! \param ui32Osc is the oscillator that drives the source clock.
//! - \ref OSC_RCOSC_HF
//! - \ref OSC_XOSC_HF
//! - \ref OSC_RCOSC_LF (only when ui32SrcClk is \ref OSC_SRC_CLK_LF)
//! - \ref OSC_XOSC_LF (only when ui32SrcClk is \ref OSC_SRC_CLK_LF)
//!
//! \sa \ref OSCClockSourceGet(), \ref OSCHfSourceSwitch()
//!
//! \return None
//
//*****************************************************************************
extern void OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc);
//*****************************************************************************
//
//! \brief Get the source clock settings.
//!
//! Use this function to get the oscillator source for one of the system source
//! clocks.
//!
//! \param ui32SrcClk is the source clock to check.
//! - \ref OSC_SRC_CLK_HF
//! - \ref OSC_SRC_CLK_LF
//!
//! \return Returns the type of oscillator that drives the clock source.
//! - \ref OSC_RCOSC_HF
//! - \ref OSC_XOSC_HF
//! - \ref OSC_RCOSC_LF
//! - \ref OSC_XOSC_LF
//!
//! \sa \ref OSCClockSourceSet(), \ref OSCHfSourceSwitch()
//
//*****************************************************************************
extern uint32_t OSCClockSourceGet(uint32_t ui32SrcClk);
//*****************************************************************************
//
//! \brief Check if the HF clock source is ready to be switched.
//!
//! If a request to switch the HF clock source has been made, this function
//! can be used to check if the clock source is ready to be switched.
//!
//! Once the HF clock source is ready the switch can be performed by calling
//! the \ref OSCHfSourceSwitch()
//!
//! \return Returns status of HF clock source:
//! - \c true : HF clock source is ready.
//! - \c false : HF clock source is \b not ready.
//
//*****************************************************************************
__STATIC_INLINE bool
OSCHfSourceReady(void)
{
// Return the readiness of the HF clock source
return (DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0,
DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M,
DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S)) ?
true : false;
}
//*****************************************************************************
//
//! \brief Switch the high frequency clock.
//!
//! When switching the HF clock source the clock period might be prolonged
//! leaving the clock 'stuck-at' high or low for a few cycles. To ensure that
//! this does not coincide with a read access to the Flash, potentially
//! freezing the device, the HF clock source switch must be executed from ROM.
//!
//! \note This function will not return until the clock source has been
//! switched. It is left to the programmer to ensure, that there is a pending
//! request for a HF clock source switch before this function is called.
//!
//! \return None
//!
//! \sa \ref OSCClockSourceSet()
//
//*****************************************************************************
__STATIC_INLINE void
OSCHfSourceSwitch(void)
{
// Read target clock (lower half of the 32-bit CTL0 register)
uint16_t hfSrc = HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0) & DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M;
// If target clock source is RCOSC, change clock source for DCDC to RCOSC
if(hfSrc == DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC)
{
// Force DCDC to use RCOSC before switching SCLK_HF to RCOSC
HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M | (DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M >> 16);
// Dummy read to ensure that the write has propagated
HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0);
}
// Switch the HF clock source
HapiHFSourceSafeSwitch();
// If target clock source is XOSC, change clock source for DCDC to "auto"
if(hfSrc == DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC)
{
// Set DCDC clock source back to "auto" after SCLK_HF was switched to XOSC
HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M;
}
}
//*****************************************************************************
//
//! \brief Identifies if HPOSC is enabled.
//!
//! This function checks if the device supports HPOSC and that HPOSC is selected
//! as HF oscillator for use when the radio is active.
//!
//! \return Returns status of HPOSC functionality:
//! - \c true : HPOSC is enabled.
//! - \c false : HPOSC is not enabled.
//
//*****************************************************************************
__STATIC_INLINE bool
OSC_IsHPOSCEnabled(void)
{
bool enabled = false;
if((( HWREG(CCFG_BASE + CCFG_O_MODE_CONF) & CCFG_MODE_CONF_XOSC_FREQ_M) == CCFG_MODE_CONF_XOSC_FREQ_HPOSC) &&
(( HWREG(FCFG1_BASE + FCFG1_O_OSC_CONF) & FCFG1_OSC_CONF_HPOSC_OPTION) == 0))
{
enabled = true;
}
return (enabled);
}
//*****************************************************************************
//
//! \brief Identifies if HPOSC is enabled and that SCLK_LF is derived from XOSC_HF.
//!
//! This function checks if the device supports HPOSC and that HPOSC is selected
//! as HF oscillator for use when the radio is active and also that SCLK_LF is
//! derived from XOSC_HF.
//!
//! \return Returns status of HPOSC and SCLK_LF configuration:
//! - \c true : HPOSC is enabled and SCLK_LF is derived from XOSC_HF.
//! - \c false : Either HPOSC not enabled or SCLK_LF is not derived from XOSC_HF.
//
//*****************************************************************************
__STATIC_INLINE bool
OSC_IsHPOSCEnabledWithHfDerivedLfClock(void)
{
bool enabled = false;
// Check configuration by reading lower half of the 32-bit CTL0 register
uint16_t regVal = HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0);
if( ( ( regVal & DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M ) == DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF ) &&
( ( regVal & DDI_0_OSC_CTL0_HPOSC_MODE_EN_M ) == DDI_0_OSC_CTL0_HPOSC_MODE_EN ) )
{
enabled = true;
}
return (enabled);
}
//*****************************************************************************
//
//! \brief Returns maximum startup time (in microseconds) of XOSC_HF.
//!
//! The startup time depends on several factors. This function calculates the
//! maximum startup time based on statistical information.
//!
//! \param timeUntilWakeupInMs indicates how long time (milliseconds) to the
//! startup will occur.
//!
//! \return Time margin to use in microseconds.
//
//*****************************************************************************
extern uint32_t OSCHF_GetStartupTime( uint32_t timeUntilWakeupInMs );
//*****************************************************************************
//
//! \brief Turns on XOSC_HF (but without switching to XOSC_HF).
//!
//! This function simply indicates the need for XOSC_HF to the hardware which
//! initiates the XOSC_HF startup.
//!
//! \return None
//
//*****************************************************************************
extern void OSCHF_TurnOnXosc( void );
//*****************************************************************************
//
//! \brief Switch to XOSC_HF if XOSC_HF is ready.
//!
//! This is a non-blocking function checking if the XOSC_HF is ready and
//! performs the switching if ready. The function is somewhat blocking in the
//! case where switching is performed.
//!
//! \return Returns status of the XOSC_HF switching:
//! - \c true : Switching to XOSC_HF has occurred.
//! - \c false : Switching has not occurred.
//
//*****************************************************************************
extern bool OSCHF_AttemptToSwitchToXosc( void );
//*****************************************************************************
//
//! \brief Switch to RCOSC_HF and turn off XOSC_HF.
//!
//! This operation takes approximately 50 microseconds (can be shorter if
//! RCOSC_HF already was running).
//!
//! \return None
//
//*****************************************************************************
extern void OSCHF_SwitchToRcOscTurnOffXosc( void );
//*****************************************************************************
//
//! \brief Get crystal amplitude (assuming crystal is running).
//!
//! \note This is a debug function only.
//! It is hence not recommended to call this function in normal operation.
//!
//! This function uses an on-chip ADC and peak detector for reading the crystal
//! amplitude. The measurement time is set to 4 milliseconds and this function
//! does not return before the measurement is done.
//!
//! Expected value is \ref OSCHF_DebugGetExpectedAverageCrystalAmplitude +/- 50 millivolt.
//!
//! \return Returns crystal amplitude in millivolt.
//!
//! \sa OSCHF_DebugGetExpectedAverageCrystalAmplitude()
//
//*****************************************************************************
extern uint32_t OSCHF_DebugGetCrystalAmplitude( void );
//*****************************************************************************
//
//! \brief Get the expected average crystal amplitude.
//!
//! \note This is a debug function only.
//! It is hence not recommended to call this function in normal operation.
//!
//! This function read the configured high and low thresholds and returns
//! the mean value converted to millivolt.
//!
//! \return Returns expected average crystal amplitude in millivolt.
//!
//! \sa OSCHF_DebugGetCrystalAmplitude()
//
//*****************************************************************************
extern uint32_t OSCHF_DebugGetExpectedAverageCrystalAmplitude( void );
//*****************************************************************************
//
//! \brief Data structure for experimental HPOSC polynomials calculation.
//!
//! The structure of the meas_1, meas_2 and meas_3 parameter is
//! as defined in FCFG1_O_HPOSC_MEAS_1, 2 and 3.
//!
//! \sa OSC_HPOSC_Debug_InitFreqOffsetParams()
//
//*****************************************************************************
typedef struct {
uint32_t meas_1 ; //!< Measurement set 1 (typically at room temp)
uint32_t meas_2 ; //!< Measurement set 2 (typically at high temp)
uint32_t meas_3 ; //!< Measurement set 3 (typically at low temp)
int32_t offsetD1 ; //!< Offset to measurement set 1
int32_t offsetD2 ; //!< Offset to measurement set 2
int32_t offsetD3 ; //!< Offset to measurement set 3
int32_t polyP3 ; //!< The P3 polynomial
} HposcDebugData_t;
//*****************************************************************************
//
//! \brief Debug function to calculate the HPOSC polynomials for experimental data sets.
//!
//! \param pDebugData pointer to the input data collected in \ref HposcDebugData_t
//!
//! \return None
//!
//! \sa OSC_HPOSCInitializeFrequencyOffsetParameters()
//
//*****************************************************************************
extern void OSC_HPOSC_Debug_InitFreqOffsetParams( HposcDebugData_t * pDebugData );
//*****************************************************************************
//
//! \brief HPOSC initialization function. Must always be called before using HPOSC.
//!
//! Calculates the fitting curve parameters (polynomials) to used by the
//! HPOSC temperature compensation.
//!
//! \return None
//!
//! \sa OSC_HPOSC_Debug_InitFreqOffsetParams()
//
//*****************************************************************************
extern void OSC_HPOSCInitializeFrequencyOffsetParameters( void );
//*****************************************************************************
//
//! \brief Calculate the temperature dependent relative frequency offset of HPOSC
//!
//! The HPOSC (High Precision Oscillator) frequency will vary slightly with chip temperature.
//! The frequency offset from the nominal value can be predicted based on
//! second order linear interpolation using coefficients measured in chip
//! production and stored as factory configuration parameters.
//!
//! This function calculates the relative frequency offset, defined as:
//! <pre>
//! F_HPOSC = F_nom * (1 + d/(2^22))
//! </pre>
//! where
//! - F_HPOSC is the current HPOSC frequency.
//! - F_nom is the nominal oscillator frequency, assumed to be 48.000 MHz.
//! - d is the relative frequency offset (the value returned).
//!
//! By knowing the relative frequency offset it is then possible to compensate
//! any timing related values accordingly.
//!
//! \param tempDegC is the chip temperature in degrees Celsius. Use the
//! function \ref AONBatMonTemperatureGetDegC() to get current chip temperature.
//!
//! \return Returns the relative frequency offset parameter d.
//!
//! \sa OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert(), AONBatMonTemperatureGetDegC()
//
//*****************************************************************************
extern int32_t OSC_HPOSCRelativeFrequencyOffsetGet( int32_t tempDegC );
//*****************************************************************************
//
//! \brief Adjust the XOSC HF cap array relative to the factory setting
//!
//! The cap array factory setting (FCFG) can be converted to a number in the range 0 - 63.
//! Both this function and the customer configuration (CCFG) setting can apply a delta to the FCFG setting.
//! The CCFG setting is automatically applied at boot time (See ../startup_files/ccfg.c).
//! Calling this function will discard the CCFG setting and adjust relative to the FCFG setting.
//!
//! \note Adjusted value will not take effect before XOSC_HF is stopped and restarted
//!
//! \param capArrDelta specifies number of step to adjust the cap array relative to the factory setting.
//!
//! \return None
//
//*****************************************************************************
extern void OSC_AdjustXoscHfCapArray( int32_t capArrDelta );
//*****************************************************************************
//
//! \brief Converts the relative frequency offset of HPOSC to the RF Core parameter format.
//!
//! The HPOSC (High Precision Oscillator) clock is used by the RF Core.
//! To compensate for a frequency offset in the frequency of the clock source,
//! a frequency offset parameter can be provided as part of the radio configuration
//! override setting list to enable compensation of the RF synthesizer frequency,
//! symbol timing, and radio timer to still achieve correct frequencies.
//!
//! The RF Core takes a relative frequency offset parameter defined differently
//! compared to the relative frequency offset parameter returned from function
//! \ref OSC_HPOSCRelativeFrequencyOffsetGet() and thus needs to be converted:
//! <pre>
//! F_nom = F_HPOSC * (1 + RfCoreRelFreqOffset/(2^22))
//! </pre>
//! where
//! - F_nom is the nominal oscillator frequency, assumed to be 48.000 MHz.
//! - F_HPOSC is the current HPOSC frequency.
//! - RfCoreRelFreqOffset is the relative frequency offset in the "RF Core" format (the value returned).
//!
//! \param HPOSC_RelFreqOffset is the relative frequency offset parameter d returned from \ref OSC_HPOSCRelativeFrequencyOffsetGet()
//!
//! \return Returns the relative frequency offset in RF Core format.
//!
//! \sa OSC_HPOSCRelativeFrequencyOffsetGet()
//
//*****************************************************************************
extern int16_t OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HPOSC_RelFreqOffset );
//*****************************************************************************
//
//! \brief Compensate the RTC increment based on the relative frequency offset of HPOSC
//!
//! The HPOSC (High Precision Oscillator) frequency will vary slightly with chip temperature.
//! This variation forces the RTC increment to be compensated if SCLK_LF is configured
//! to be derived from the HF clock of HPOSC.
//! This function must only be called if SCLK_LF is configured to be derived from
//! the HF clock of HPOSC. The status of this configuration can be determined
//! by calling the \ref OSC_IsHPOSCEnabledWithHfDerivedLfClock() function.
//!
//! This function first calculates the HPOSC frequency, defined as:
//! <pre>
//! F_HPOSC = F_nom * (1 + d/(2^22))
//! </pre>
//! where
//! - F_HPOSC is the current HPOSC frequency.
//! - F_nom is the nominal oscillator frequency, assumed to be 48.000 MHz.
//! - d is the relative frequency offset given by the input argument relFreqOffset.
//! Then the SCLK_LF frequency is calculated, defined as:
//! <pre>
//! F_SCLK_LF = F_HPOSC / 1536
//! </pre>
//! Then the RTC increment SUBSECINC is calculated, defined as;
//! <pre>
//! SUBSECINC = (2^38) / F_SCLK_LF
//! </pre>
//! Finally the RTC module is updated with the calculated SUBSECINC value.
//!
//! \param relFreqOffset is the relative frequency offset parameter d returned from \ref OSC_HPOSCRelativeFrequencyOffsetGet()
//!
//! \return None
//!
//
//*****************************************************************************
extern void OSC_HPOSCRtcCompensate( int32_t relFreqOffset );
//*****************************************************************************
//
// Support for DriverLib in ROM:
// Redirect to implementation in ROM when available.
//
//*****************************************************************************
#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
#include "../driverlib/rom.h"
#ifdef ROM_OSCClockSourceSet
#undef OSCClockSourceSet
#define OSCClockSourceSet ROM_OSCClockSourceSet
#endif
#ifdef ROM_OSCClockSourceGet
#undef OSCClockSourceGet
#define OSCClockSourceGet ROM_OSCClockSourceGet
#endif
#ifdef ROM_OSCHF_GetStartupTime
#undef OSCHF_GetStartupTime
#define OSCHF_GetStartupTime ROM_OSCHF_GetStartupTime
#endif
#ifdef ROM_OSCHF_TurnOnXosc
#undef OSCHF_TurnOnXosc
#define OSCHF_TurnOnXosc ROM_OSCHF_TurnOnXosc
#endif
#ifdef ROM_OSCHF_AttemptToSwitchToXosc
#undef OSCHF_AttemptToSwitchToXosc
#define OSCHF_AttemptToSwitchToXosc ROM_OSCHF_AttemptToSwitchToXosc
#endif
#ifdef ROM_OSCHF_SwitchToRcOscTurnOffXosc
#undef OSCHF_SwitchToRcOscTurnOffXosc
#define OSCHF_SwitchToRcOscTurnOffXosc ROM_OSCHF_SwitchToRcOscTurnOffXosc
#endif
#ifdef ROM_OSCHF_DebugGetCrystalAmplitude
#undef OSCHF_DebugGetCrystalAmplitude
#define OSCHF_DebugGetCrystalAmplitude ROM_OSCHF_DebugGetCrystalAmplitude
#endif
#ifdef ROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude
#undef OSCHF_DebugGetExpectedAverageCrystalAmplitude
#define OSCHF_DebugGetExpectedAverageCrystalAmplitude ROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude
#endif
#ifdef ROM_OSC_HPOSC_Debug_InitFreqOffsetParams
#undef OSC_HPOSC_Debug_InitFreqOffsetParams
#define OSC_HPOSC_Debug_InitFreqOffsetParams ROM_OSC_HPOSC_Debug_InitFreqOffsetParams
#endif
#ifdef ROM_OSC_HPOSCInitializeFrequencyOffsetParameters
#undef OSC_HPOSCInitializeFrequencyOffsetParameters
#define OSC_HPOSCInitializeFrequencyOffsetParameters ROM_OSC_HPOSCInitializeFrequencyOffsetParameters
#endif
#ifdef ROM_OSC_HPOSCRelativeFrequencyOffsetGet
#undef OSC_HPOSCRelativeFrequencyOffsetGet
#define OSC_HPOSCRelativeFrequencyOffsetGet ROM_OSC_HPOSCRelativeFrequencyOffsetGet
#endif
#ifdef ROM_OSC_AdjustXoscHfCapArray
#undef OSC_AdjustXoscHfCapArray
#define OSC_AdjustXoscHfCapArray ROM_OSC_AdjustXoscHfCapArray
#endif
#ifdef ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert
#undef OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert
#define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert
#endif
#ifdef ROM_OSC_HPOSCRtcCompensate
#undef OSC_HPOSCRtcCompensate
#define OSC_HPOSCRtcCompensate ROM_OSC_HPOSCRtcCompensate
#endif
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __OSC_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

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/******************************************************************************
* Filename: pka_doc.h
* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017)
* Revision: 49096
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//! \addtogroup pka_api
//! @{
//! \section sec_pka Introduction
//!
//! The PKA (Public Key Accelerator) API provides access to the Large Number
//! Engine (LNME). The LNME allows for efficient math operations on numbers
//! larger than those that fit within the ALU of the system CPU. It is significantly faster
//! to perform these operations using the LNME than implementing the same
//! functionality in software using regular word-wise math operations. While the
//! LNME runs in the background, the system CPU may perform other operations
//! or be turned off.
//!
//! The LNME supports both primitive math operations and serialized primitive
//! operations (sequencer operations).
//! - Addition
//! - Multiplication
//! - Comparison
//! - Modulo
//! - Inverse Modulo
//! - ECC Point Addition (including point doubling)
//! - ECC Scalar Multiplication
//!
//! These primitives and sequencer operations can be used to implement various
//! public key encryption schemes.
//! It is possible to implement the following schemes using the operations mentioned above:
//! - RSA encryption and decryption
//! - RSA sign and verify
//! - DHE (Diffie-Hellman Key Exchange)
//! - ECDH (Elliptic Curve Diffie-Hellman Key Exchange)
//! - ECDSA (Elliptic Curve Digital Signature Algorithm)
//! - ECIES (Elliptic Curve Integrated Encryption Scheme)
//!
//! The DriverLib PKA functions copy the relevant parameters into the dedicated
//! PKA RAM. The LNME requires these parameters be present and correctly
//! formatted in the PKA RAM and not system RAM. They are copied word-wise as
//! the PKA RAM does not support byte-wise access. The CPU handles the alignment differences
//! during the memory copy operation. Forcing buffer alignment in system RAM results
//! in a significant speedup of the copy operation compared to unaligned buffers.
//!
//! When the operation completes, the result is copied back into
//! a buffer in system RAM specified by the application. The PKA RAM is then cleared
//! to prevent sensitive keying material from remaining in PKA RAM.
//!
//!
//! @}

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/******************************************************************************
* Filename: prcm.c
* Revised: 2018-10-18 17:33:32 +0200 (Thu, 18 Oct 2018)
* Revision: 52954
*
* Description: Driver for the PRCM.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "prcm.h"
//*****************************************************************************
//
// Handle support for DriverLib in ROM:
// This section will undo prototype renaming made in the header file
//
//*****************************************************************************
#if !defined(DOXYGEN)
#undef PRCMInfClockConfigureSet
#define PRCMInfClockConfigureSet NOROM_PRCMInfClockConfigureSet
#undef PRCMInfClockConfigureGet
#define PRCMInfClockConfigureGet NOROM_PRCMInfClockConfigureGet
#undef PRCMAudioClockConfigSet
#define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet
#undef PRCMAudioClockConfigSetOverride
#define PRCMAudioClockConfigSetOverride NOROM_PRCMAudioClockConfigSetOverride
#undef PRCMAudioClockInternalSource
#define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource
#undef PRCMAudioClockExternalSource
#define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource
#undef PRCMPowerDomainOn
#define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn
#undef PRCMPowerDomainOff
#define PRCMPowerDomainOff NOROM_PRCMPowerDomainOff
#undef PRCMPeripheralRunEnable
#define PRCMPeripheralRunEnable NOROM_PRCMPeripheralRunEnable
#undef PRCMPeripheralRunDisable
#define PRCMPeripheralRunDisable NOROM_PRCMPeripheralRunDisable
#undef PRCMPeripheralSleepEnable
#define PRCMPeripheralSleepEnable NOROM_PRCMPeripheralSleepEnable
#undef PRCMPeripheralSleepDisable
#define PRCMPeripheralSleepDisable NOROM_PRCMPeripheralSleepDisable
#undef PRCMPeripheralDeepSleepEnable
#define PRCMPeripheralDeepSleepEnable NOROM_PRCMPeripheralDeepSleepEnable
#undef PRCMPeripheralDeepSleepDisable
#define PRCMPeripheralDeepSleepDisable NOROM_PRCMPeripheralDeepSleepDisable
#undef PRCMPowerDomainStatus
#define PRCMPowerDomainStatus NOROM_PRCMPowerDomainStatus
#undef PRCMDeepSleep
#define PRCMDeepSleep NOROM_PRCMDeepSleep
#endif
//*****************************************************************************
//
// Arrays that maps the "peripheral set" number (which is stored in
// bits[11:8] of the PRCM_PERIPH_* defines) to the PRCM register that
// contains the relevant bit for that peripheral.
//
//*****************************************************************************
// Run mode registers
static const uint32_t g_pui32RCGCRegs[] =
{
PRCM_O_GPTCLKGR , // Index 0
PRCM_O_SSICLKGR , // Index 1
PRCM_O_UARTCLKGR , // Index 2
PRCM_O_I2CCLKGR , // Index 3
PRCM_O_SECDMACLKGR , // Index 4
PRCM_O_GPIOCLKGR , // Index 5
PRCM_O_I2SCLKGR // Index 6
};
// Sleep mode registers
static const uint32_t g_pui32SCGCRegs[] =
{
PRCM_O_GPTCLKGS , // Index 0
PRCM_O_SSICLKGS , // Index 1
PRCM_O_UARTCLKGS , // Index 2
PRCM_O_I2CCLKGS , // Index 3
PRCM_O_SECDMACLKGS , // Index 4
PRCM_O_GPIOCLKGS , // Index 5
PRCM_O_I2SCLKGS // Index 6
};
// Deep sleep mode registers
static const uint32_t g_pui32DCGCRegs[] =
{
PRCM_O_GPTCLKGDS , // Index 0
PRCM_O_SSICLKGDS , // Index 1
PRCM_O_UARTCLKGDS , // Index 2
PRCM_O_I2CCLKGDS , // Index 3
PRCM_O_SECDMACLKGDS , // Index 4
PRCM_O_GPIOCLKGDS , // Index 5
PRCM_O_I2SCLKGDS // Index 6
};
//*****************************************************************************
//
// This macro extracts the array index out of the peripheral number
//
//*****************************************************************************
#define PRCM_PERIPH_INDEX(a) (((a) >> 8) & 0xf)
//*****************************************************************************
//
// This macro extracts the peripheral instance number and generates bit mask
//
//*****************************************************************************
#define PRCM_PERIPH_MASKBIT(a) (0x00000001 << ((a) & 0x1f))
//*****************************************************************************
//
// Configure the infrastructure clock.
//
//*****************************************************************************
void
PRCMInfClockConfigureSet(uint32_t ui32ClkDiv, uint32_t ui32PowerMode)
{
uint32_t ui32Divisor;
// Check the arguments.
ASSERT((ui32ClkDiv == PRCM_CLOCK_DIV_1) ||
(ui32ClkDiv == PRCM_CLOCK_DIV_2) ||
(ui32ClkDiv == PRCM_CLOCK_DIV_8) ||
(ui32ClkDiv == PRCM_CLOCK_DIV_32));
ASSERT((ui32PowerMode == PRCM_RUN_MODE) ||
(ui32PowerMode == PRCM_SLEEP_MODE) ||
(ui32PowerMode == PRCM_DEEP_SLEEP_MODE));
ui32Divisor = 0;
// Find the correct division factor.
if(ui32ClkDiv == PRCM_CLOCK_DIV_1)
{
ui32Divisor = 0x0;
}
else if(ui32ClkDiv == PRCM_CLOCK_DIV_2)
{
ui32Divisor = 0x1;
}
else if(ui32ClkDiv == PRCM_CLOCK_DIV_8)
{
ui32Divisor = 0x2;
}
else if(ui32ClkDiv == PRCM_CLOCK_DIV_32)
{
ui32Divisor = 0x3;
}
// Determine the correct power mode set the division factor accordingly.
if(ui32PowerMode == PRCM_RUN_MODE)
{
HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR) = ui32Divisor;
}
else if(ui32PowerMode == PRCM_SLEEP_MODE)
{
HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS) = ui32Divisor;
}
else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE)
{
HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS) = ui32Divisor;
}
}
//*****************************************************************************
//
// Use this function to get the infrastructure clock configuration
//
//*****************************************************************************
uint32_t
PRCMInfClockConfigureGet(uint32_t ui32PowerMode)
{
uint32_t ui32ClkDiv;
uint32_t ui32Divisor;
// Check the arguments.
ASSERT((ui32PowerMode == PRCM_RUN_MODE) ||
(ui32PowerMode == PRCM_SLEEP_MODE) ||
(ui32PowerMode == PRCM_DEEP_SLEEP_MODE));
ui32ClkDiv = 0;
ui32Divisor = 0;
// Determine the correct power mode.
if(ui32PowerMode == PRCM_RUN_MODE)
{
ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR);
}
else if(ui32PowerMode == PRCM_SLEEP_MODE)
{
ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS);
}
else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE)
{
ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS);
}
// Find the correct division factor.
if(ui32ClkDiv == 0x0)
{
ui32Divisor = PRCM_CLOCK_DIV_1;
}
else if(ui32ClkDiv == 0x1)
{
ui32Divisor = PRCM_CLOCK_DIV_2;
}
else if(ui32ClkDiv == 0x2)
{
ui32Divisor = PRCM_CLOCK_DIV_8;
}
else if(ui32ClkDiv == 0x3)
{
ui32Divisor = PRCM_CLOCK_DIV_32;
}
// Return the clock division factor.
return ui32Divisor;
}
//*****************************************************************************
//
// Configure the audio clock generation
//
//*****************************************************************************
void
PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, uint32_t ui32SampleRate)
{
uint32_t ui32Reg;
uint32_t ui32MstDiv;
uint32_t ui32BitDiv;
uint32_t ui32WordDiv;
// Check the arguments.
ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M)));
ASSERT((ui32SampleRate == I2S_SAMPLE_RATE_16K) ||
(ui32SampleRate == I2S_SAMPLE_RATE_24K) ||
(ui32SampleRate == I2S_SAMPLE_RATE_32K) ||
(ui32SampleRate == I2S_SAMPLE_RATE_48K));
ui32MstDiv = 0;
ui32BitDiv = 0;
ui32WordDiv = 0;
// Make sure the audio clock generation is disabled before reconfiguring.
PRCMAudioClockDisable();
// Define the clock division factors for the audio interface.
switch(ui32SampleRate)
{
case I2S_SAMPLE_RATE_16K :
ui32MstDiv = 6;
ui32BitDiv = 60;
ui32WordDiv = 25;
break;
case I2S_SAMPLE_RATE_24K :
ui32MstDiv = 4;
ui32BitDiv = 40;
ui32WordDiv = 25;
break;
case I2S_SAMPLE_RATE_32K :
ui32MstDiv = 3;
ui32BitDiv = 30;
ui32WordDiv = 25;
break;
case I2S_SAMPLE_RATE_48K :
ui32MstDiv = 2;
ui32BitDiv = 20;
ui32WordDiv = 25;
break;
}
// Make sure to compensate the Frame clock division factor if using single
// phase format.
if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE)
{
ui32WordDiv -= 1;
}
// Write the clock division factors.
HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv;
HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv;
HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv;
// Configure the Word clock format and polarity.
ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M |
PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M);
HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig;
}
//*****************************************************************************
//
// Configure the audio clock generation with manual setting of clock divider.
//
//*****************************************************************************
void
PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv,
uint32_t ui32BitDiv, uint32_t ui32WordDiv)
{
uint32_t ui32Reg;
// Check the arguments.
ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M)));
// Make sure the audio clock generation is disabled before reconfiguring.
PRCMAudioClockDisable();
// Make sure to compensate the Frame clock division factor if using single
// phase format.
if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE)
{
ui32WordDiv -= 1;
}
// Write the clock division factors.
HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv;
HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv;
HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv;
// Configure the Word clock format and polarity.
ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M |
PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M);
HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig;
}
//*****************************************************************************
//
// Configure the audio clocks for I2S module
//
//*****************************************************************************
void
PRCMAudioClockConfigOverride(uint8_t ui8SamplingEdge,
uint8_t ui8WCLKPhase,
uint32_t ui32MstDiv,
uint32_t ui32BitDiv,
uint32_t ui32WordDiv)
{
// Check the arguments.
ASSERT( ui8BitsPerSample == PRCM_WCLK_SINGLE_PHASE
|| ui8BitsPerSample == PRCM_WCLK_DUAL_PHASE
|| ui8BitsPerSample == PRCM_WCLK_USER_DEF);
// Make sure the audio clock generation is disabled before reconfiguring.
PRCMAudioClockDisable();
// Make sure to compensate the Frame clock division factor if using single
// phase format.
if((ui8WCLKPhase) == PRCM_WCLK_SINGLE_PHASE)
{
ui32WordDiv -= 1;
}
// Write the clock division factors.
HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv;
HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv;
HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv;
// Configure the Word clock format and polarity and enable it.
HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = (ui8SamplingEdge << PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S) |
(ui8WCLKPhase << PRCM_I2SCLKCTL_WCLK_PHASE_S ) |
(1 << PRCM_I2SCLKCTL_EN_S );
}
//*****************************************************************************
//
// Configure the clocks as "internally generated".
//
//*****************************************************************************
void PRCMAudioClockInternalSource(void)
{
HWREGBITW(PRCM_BASE + PRCM_O_I2SBCLKSEL, PRCM_I2SBCLKSEL_SRC_BITN) = 1;
}
//*****************************************************************************
//
// Configure the clocks as "externally generated".
//
//*****************************************************************************
void PRCMAudioClockExternalSource(void)
{
HWREGBITW(PRCM_BASE + PRCM_O_I2SBCLKSEL, PRCM_I2SBCLKSEL_SRC_BITN) = 0;
}
//*****************************************************************************
//
// Turn power on in power domains in the MCU domain
//
//*****************************************************************************
void
PRCMPowerDomainOn(uint32_t ui32Domains)
{
// Check the arguments.
ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) ||
(ui32Domains & PRCM_DOMAIN_SERIAL) ||
(ui32Domains & PRCM_DOMAIN_PERIPH) ||
(ui32Domains & PRCM_DOMAIN_CPU) ||
(ui32Domains & PRCM_DOMAIN_VIMS));
// Assert the request to power on the right domains.
if(ui32Domains & PRCM_DOMAIN_RFCORE)
{
HWREG(PRCM_BASE + PRCM_O_PDCTL0RFC ) = 1;
}
if(ui32Domains & PRCM_DOMAIN_SERIAL)
{
HWREG(PRCM_BASE + PRCM_O_PDCTL0SERIAL) = 1;
}
if(ui32Domains & PRCM_DOMAIN_PERIPH)
{
HWREG(PRCM_BASE + PRCM_O_PDCTL0PERIPH) = 1;
}
if(ui32Domains & PRCM_DOMAIN_VIMS)
{
HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 1;
}
if(ui32Domains & PRCM_DOMAIN_CPU)
{
HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU ) = 1;
}
}
//*****************************************************************************
//
// Turn off a specific power domain
//
//*****************************************************************************
void
PRCMPowerDomainOff(uint32_t ui32Domains)
{
// Check the arguments.
ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) ||
(ui32Domains & PRCM_DOMAIN_SERIAL) ||
(ui32Domains & PRCM_DOMAIN_PERIPH) ||
(ui32Domains & PRCM_DOMAIN_CPU) ||
(ui32Domains & PRCM_DOMAIN_VIMS));
// Assert the request to power off the right domains.
if(ui32Domains & PRCM_DOMAIN_RFCORE)
{
HWREG(PRCM_BASE + PRCM_O_PDCTL0RFC ) = 0;
}
if(ui32Domains & PRCM_DOMAIN_SERIAL)
{
HWREG(PRCM_BASE + PRCM_O_PDCTL0SERIAL) = 0;
}
if(ui32Domains & PRCM_DOMAIN_PERIPH)
{
HWREG(PRCM_BASE + PRCM_O_PDCTL0PERIPH) = 0;
}
if(ui32Domains & PRCM_DOMAIN_VIMS)
{
// Write bits ui32Domains[17:16] to the VIMS_MODE alias register.
// PRCM_DOMAIN_VIMS sets VIMS_MODE=0b00, PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP sets VIMS_MODE=0b10.
ASSERT(!(ui32Domains & 0x00010000));
HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS ) = ( ui32Domains >> 16 ) & 3;
}
if(ui32Domains & PRCM_DOMAIN_CPU)
{
HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU ) = 0;
}
}
//*****************************************************************************
//
// Enables a peripheral in Run mode
//
//*****************************************************************************
void
PRCMPeripheralRunEnable(uint32_t ui32Peripheral)
{
// Check the arguments.
ASSERT(PRCMPeripheralValid(ui32Peripheral));
// Enable module in Run Mode.
HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |=
PRCM_PERIPH_MASKBIT(ui32Peripheral);
}
//*****************************************************************************
//
// Disables a peripheral in Run mode
//
//*****************************************************************************
void
PRCMPeripheralRunDisable(uint32_t ui32Peripheral)
{
// Check the arguments.
ASSERT(PRCMPeripheralValid(ui32Peripheral));
// Disable module in Run Mode.
HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &=
~PRCM_PERIPH_MASKBIT(ui32Peripheral);
}
//*****************************************************************************
//
// Enables a peripheral in sleep mode
//
//*****************************************************************************
void
PRCMPeripheralSleepEnable(uint32_t ui32Peripheral)
{
// Check the arguments.
ASSERT(PRCMPeripheralValid(ui32Peripheral));
// Enable this peripheral in sleep mode.
HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |=
PRCM_PERIPH_MASKBIT(ui32Peripheral);
}
//*****************************************************************************
//
// Disables a peripheral in sleep mode
//
//*****************************************************************************
void
PRCMPeripheralSleepDisable(uint32_t ui32Peripheral)
{
// Check the arguments.
ASSERT(PRCMPeripheralValid(ui32Peripheral));
// Disable this peripheral in sleep mode
HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &=
~PRCM_PERIPH_MASKBIT(ui32Peripheral);
}
//*****************************************************************************
//
// Enables a peripheral in deep-sleep mode
//
//*****************************************************************************
void
PRCMPeripheralDeepSleepEnable(uint32_t ui32Peripheral)
{
// Check the arguments.
ASSERT(PRCMPeripheralValid(ui32Peripheral));
// Enable this peripheral in deep-sleep mode.
HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |=
PRCM_PERIPH_MASKBIT(ui32Peripheral);
}
//*****************************************************************************
//
// Disables a peripheral in deep-sleep mode
//
//*****************************************************************************
void
PRCMPeripheralDeepSleepDisable(uint32_t ui32Peripheral)
{
// Check the arguments.
ASSERT(PRCMPeripheralValid(ui32Peripheral));
// Disable this peripheral in Deep Sleep mode.
HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &=
~PRCM_PERIPH_MASKBIT(ui32Peripheral);
}
//*****************************************************************************
//
// Get the status for a specific power domain
//
//*****************************************************************************
uint32_t
PRCMPowerDomainStatus(uint32_t ui32Domains)
{
bool bStatus;
uint32_t ui32StatusRegister0;
uint32_t ui32StatusRegister1;
// Check the arguments.
ASSERT((ui32Domains & (PRCM_DOMAIN_RFCORE |
PRCM_DOMAIN_SERIAL |
PRCM_DOMAIN_PERIPH)));
bStatus = true;
ui32StatusRegister0 = HWREG(PRCM_BASE + PRCM_O_PDSTAT0);
ui32StatusRegister1 = HWREG(PRCM_BASE + PRCM_O_PDSTAT1);
// Return the correct power status.
if(ui32Domains & PRCM_DOMAIN_RFCORE)
{
bStatus = bStatus &&
((ui32StatusRegister0 & PRCM_PDSTAT0_RFC_ON) ||
(ui32StatusRegister1 & PRCM_PDSTAT1_RFC_ON));
}
if(ui32Domains & PRCM_DOMAIN_SERIAL)
{
bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_SERIAL_ON);
}
if(ui32Domains & PRCM_DOMAIN_PERIPH)
{
bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_PERIPH_ON);
}
// Return the status.
return (bStatus ? PRCM_DOMAIN_POWER_ON : PRCM_DOMAIN_POWER_OFF);
}
//*****************************************************************************
//
// Put the processor into deep-sleep mode
//
//*****************************************************************************
void
PRCMDeepSleep(void)
{
// Enable deep-sleep.
HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP;
// Wait for an interrupt.
CPUwfi();
// Disable deep-sleep so that a future sleep will work correctly.
HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP);
}

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ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/prcm.h
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ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pwr_ctrl.c
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/******************************************************************************
* Filename: pwr_ctrl.c
* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017)
* Revision: 49096
*
* Description: Power Control driver.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include "pwr_ctrl.h"
//*****************************************************************************
//
// Handle support for DriverLib in ROM:
// This section will undo prototype renaming made in the header file
//
//*****************************************************************************
#if !defined(DOXYGEN)
#undef PowerCtrlSourceSet
#define PowerCtrlSourceSet NOROM_PowerCtrlSourceSet
#endif
//*****************************************************************************
//
// Set (Request) the main power source
//
//*****************************************************************************
void
PowerCtrlSourceSet(uint32_t ui32PowerConfig)
{
// Check the arguments.
ASSERT((ui32PowerConfig == PWRCTRL_PWRSRC_DCDC) ||
(ui32PowerConfig == PWRCTRL_PWRSRC_GLDO) ||
(ui32PowerConfig == PWRCTRL_PWRSRC_ULDO));
// Configure the power.
if(ui32PowerConfig == PWRCTRL_PWRSRC_DCDC) {
HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) |=
(AON_PMCTL_PWRCTL_DCDC_EN | AON_PMCTL_PWRCTL_DCDC_ACTIVE);
}
else if (ui32PowerConfig == PWRCTRL_PWRSRC_GLDO)
{
HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) &=
~(AON_PMCTL_PWRCTL_DCDC_EN | AON_PMCTL_PWRCTL_DCDC_ACTIVE);
}
else
{
PRCMMcuUldoConfigure(true);
}
}

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ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pwr_ctrl.h
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/******************************************************************************
* Filename: pwr_ctrl.h
* Revised: 2017-11-02 15:41:14 +0100 (Thu, 02 Nov 2017)
* Revision: 50165
*
* Description: Defines and prototypes for the System Power Control.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//*****************************************************************************
//
//! \addtogroup system_control_group
//! @{
//! \addtogroup pwrctrl_api
//! @{
//
//*****************************************************************************
#ifndef __PWR_CTRL_H__
#define __PWR_CTRL_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdbool.h>
#include <stdint.h>
#include "../inc/hw_types.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_ints.h"
#include "../inc/hw_aon_pmctl.h"
#include "../inc/hw_aon_rtc.h"
#include "../inc/hw_adi_2_refsys.h"
#include "debug.h"
#include "interrupt.h"
#include "osc.h"
#include "cpu.h"
#include "prcm.h"
#include "aon_ioc.h"
#include "adi.h"
//*****************************************************************************
//
// Support for DriverLib in ROM:
// This section renames all functions that are not "static inline", so that
// calling these functions will default to implementation in flash. At the end
// of this file a second renaming will change the defaults to implementation in
// ROM for available functions.
//
// To force use of the implementation in flash, e.g. for debugging:
// - Globally: Define DRIVERLIB_NOROM at project level
// - Per function: Use prefix "NOROM_" when calling the function
//
//*****************************************************************************
#if !defined(DOXYGEN)
#define PowerCtrlSourceSet NOROM_PowerCtrlSourceSet
#endif
//*****************************************************************************
//
// Defines for the system power states
//
//*****************************************************************************
#define PWRCTRL_ACTIVE 0x00000001
#define PWRCTRL_STANDBY 0x00000002
#define PWRCTRL_POWER_DOWN 0x00000004
#define PWRCTRL_SHUTDOWN 0x00000008
//*****************************************************************************
//
// Defines for the power configuration in the AON System Control 1.2 V
//
//*****************************************************************************
#define PWRCTRL_IOSEG3_ENABLE 0x00000800
#define PWRCTRL_IOSEG2_ENABLE 0x00000400
#define PWRCTRL_IOSEG3_DISABLE 0x00000200
#define PWRCTRL_IOSEG2_DISABLE 0x00000100
#define PWRCTRL_PWRSRC_DCDC 0x00000001
#define PWRCTRL_PWRSRC_GLDO 0x00000000
#define PWRCTRL_PWRSRC_ULDO 0x00000002
//*****************************************************************************
//
// The following are defines for the various reset source for the device.
//
//*****************************************************************************
#define PWRCTRL_RST_POWER_ON 0x00000000 // Reset by power on
#define PWRCTRL_RST_PIN 0x00000001 // Pin reset
#define PWRCTRL_RST_VDDS_BOD 0x00000002 // VDDS Brown Out Detect
#define PWRCTRL_RST_VDD_BOD 0x00000003 // VDD Brown Out Detect
#define PWRCTRL_RST_VDDR_BOD 0x00000004 // VDDR Brown Out Detect
#define PWRCTRL_RST_CLK_LOSS 0x00000005 // Clock loss Reset
#define PWRCTRL_RST_SW_PIN 0x00000006 // SYSRESET or pin reset
#define PWRCTRL_RST_WARM 0x00000007 // Reset via PRCM warm reset request
//*****************************************************************************
//
// API Functions and prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Set (Request) the main power source.
//!
//! \note The system will never allow a switch to the \ref PWRCTRL_PWRSRC_ULDO
//! when in active mode. This is only allowed when the system is in lower power
//! mode where no code is executing and no peripherals are active.
//! Assuming that there is an external capacitor available for the
//! \ref PWRCTRL_PWRSRC_DCDC the system can dynamically switch back and forth
//! between the two when in active mode.
//!
//! \note The system will automatically switch to the GLDO / DCDC when waking
//! up from a low power mode.
//!
//! \param ui32PowerConfig is a bitmask indicating the target power source.
//! - \ref PWRCTRL_PWRSRC_DCDC
//! - \ref PWRCTRL_PWRSRC_GLDO
//! - \ref PWRCTRL_PWRSRC_ULDO
//!
//! \return None
//
//*****************************************************************************
extern void PowerCtrlSourceSet(uint32_t ui32PowerConfig);
//*****************************************************************************
//
//! \brief Get the main power source.
//!
//! Use this function to retrieve the current active power source.
//!
//! When the System CPU is active it can never be powered by uLDO as this
//! is too weak a power source.
//!
//! \note Using the DCDC power supply requires an external inductor.
//!
//! \return Returns the main power source.
//! - \ref PWRCTRL_PWRSRC_DCDC
//! - \ref PWRCTRL_PWRSRC_GLDO
//
//*****************************************************************************
__STATIC_INLINE uint32_t
PowerCtrlSourceGet(void)
{
uint32_t ui32PowerConfig;
// Return the current power source
ui32PowerConfig = HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL);
if(ui32PowerConfig & AON_PMCTL_PWRCTL_DCDC_ACTIVE)
{
return (PWRCTRL_PWRSRC_DCDC);
}
else
{
return (PWRCTRL_PWRSRC_GLDO);
}
}
//*****************************************************************************
//
//! \brief OBSOLETE: Get the last known reset source of the system.
//!
//! \deprecated This function will be removed in a future release.
//! Use \ref SysCtrlResetSourceGet() instead.
//!
//! This function returns reset source but does not cover if waking up from shutdown.
//! This function can be seen as a subset of function \ref SysCtrlResetSourceGet()
//! and will be removed in a future release.
//!
//! \return Returns one of the known reset values.
//! The possible reset sources are:
//! - \ref PWRCTRL_RST_POWER_ON
//! - \ref PWRCTRL_RST_PIN
//! - \ref PWRCTRL_RST_VDDS_BOD
//! - \ref PWRCTRL_RST_VDD_BOD
//! - \ref PWRCTRL_RST_VDDR_BOD
//! - \ref PWRCTRL_RST_CLK_LOSS
//! - \ref PWRCTRL_RST_SW_PIN
//! - \ref PWRCTRL_RST_WARM
//!
//! \sa \ref SysCtrlResetSourceGet()
//
//*****************************************************************************
__STATIC_INLINE uint32_t
PowerCtrlResetSourceGet(void)
{
// Get the reset source.
return (( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) &
AON_PMCTL_RESETCTL_RESET_SRC_M ) >>
AON_PMCTL_RESETCTL_RESET_SRC_S ) ;
}
//*****************************************************************************
//
//! \brief Enables pad sleep in order to latch device outputs before shutdown.
//!
//! See \ref SysCtrlShutdown() for more information about how to enter
//! shutdown and how to wake up from shutdown.
//!
//! \return None
//!
//! \sa \ref PowerCtrlPadSleepDisable()
//
//*****************************************************************************
__STATIC_INLINE void
PowerCtrlPadSleepEnable(void)
{
HWREG(AON_PMCTL_BASE + AON_PMCTL_O_SLEEPCTL) = 0;
HWREG(AON_RTC_BASE + AON_RTC_O_SYNC);
}
//*****************************************************************************
//
//! \brief Disables pad sleep in order to unlatch device outputs after wakeup from shutdown.
//!
//! This function must be called by the application after the device wakes up
//! from shutdown.
//!
//! See \ref SysCtrlShutdown() for more information about how to enter
//! shutdown and how to wake up from shutdown.
//!
//! \return None
//!
//! \sa \ref PowerCtrlPadSleepEnable()
//
//*****************************************************************************
__STATIC_INLINE void
PowerCtrlPadSleepDisable(void)
{
HWREG(AON_PMCTL_BASE + AON_PMCTL_O_SLEEPCTL) = 1;
HWREG(AON_RTC_BASE + AON_RTC_O_SYNC);
}
//*****************************************************************************
//
// Support for DriverLib in ROM:
// Redirect to implementation in ROM when available.
//
//*****************************************************************************
#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
#include "../driverlib/rom.h"
#ifdef ROM_PowerCtrlSourceSet
#undef PowerCtrlSourceSet
#define PowerCtrlSourceSet ROM_PowerCtrlSourceSet
#endif
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __PWR_CTRL_H__
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************

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ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_cmd.h
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ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_mailbox.h
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/******************************************************************************
* Filename: rf_ble_mailbox.h
* Revised: 2018-01-15 15:58:36 +0100 (Mon, 15 Jan 2018)
* Revision: 18171
*
* Description: Definitions for BLE interface
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef _BLE_MAILBOX_H
#define _BLE_MAILBOX_H
/// \name Radio operation status
///@{
/// \name Operation finished normally
///@{
#define BLE_DONE_OK 0x1400 ///< Operation ended normally
#define BLE_DONE_RXTIMEOUT 0x1401 ///< Timeout of first Rx of slave operation or end of scan window
#define BLE_DONE_NOSYNC 0x1402 ///< Timeout of subsequent Rx
#define BLE_DONE_RXERR 0x1403 ///< Operation ended because of receive error (CRC or other)
#define BLE_DONE_CONNECT 0x1404 ///< CONNECT_IND or AUX_CONNECT_RSP received or transmitted
#define BLE_DONE_MAXNACK 0x1405 ///< Maximum number of retransmissions exceeded
#define BLE_DONE_ENDED 0x1406 ///< Operation stopped after end trigger
#define BLE_DONE_ABORT 0x1407 ///< Operation aborted by command
#define BLE_DONE_STOPPED 0x1408 ///< Operation stopped after stop command
#define BLE_DONE_AUX 0x1409 ///< Operation ended after following aux pointer pointing far ahead
#define BLE_DONE_CONNECT_CHSEL0 0x140A ///< CONNECT_IND received or transmitted; peer does not support channel selection algorithm #2
#define BLE_DONE_SCAN_RSP 0x140B ///< SCAN_RSP or AUX_SCAN_RSP transmitted
///@}
/// \name Operation finished with error
///@{
#define BLE_ERROR_PAR 0x1800 ///< Illegal parameter
#define BLE_ERROR_RXBUF 0x1801 ///< No available Rx buffer (Advertiser, Scanner, Initiator)
#define BLE_ERROR_NO_SETUP 0x1802 ///< Operation using Rx or Tx attempted when not in BLE mode
#define BLE_ERROR_NO_FS 0x1803 ///< Operation using Rx or Tx attempted without frequency synth configured
#define BLE_ERROR_SYNTH_PROG 0x1804 ///< Synthesizer programming failed to complete on time
#define BLE_ERROR_RXOVF 0x1805 ///< Receiver overflowed during operation
#define BLE_ERROR_TXUNF 0x1806 ///< Transmitter underflowed during operation
#define BLE_ERROR_AUX 0x1807 ///< Calculated AUX pointer was too far into the future or in the past
///@}
///@}
/// Special trigger for BLE slave command
#define BLE_TRIG_REL_SYNC 15
#endif

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ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_common_cmd.h
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219
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_data_entry.h
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/******************************************************************************
* Filename: rf_data_entry.h
* Revised: 2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018)
* Revision: 18170
*
* Description: Definition of API for data exchange
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __DATA_ENTRY_H
#define __DATA_ENTRY_H
#ifndef __RFC_STRUCT
#define __RFC_STRUCT
#endif
#ifndef __RFC_STRUCT_ATTR
#if defined(__GNUC__)
#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4)))
#elif defined(__TI_ARM__)
#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4)))
#else
#define __RFC_STRUCT_ATTR
#endif
#endif
//! \addtogroup rfc
//! @{
//! \addtogroup data_entry
//! @{
#include <stdint.h>
#include "rf_mailbox.h"
typedef struct __RFC_STRUCT rfc_dataEntry_s rfc_dataEntry_t;
typedef struct __RFC_STRUCT rfc_dataEntryGeneral_s rfc_dataEntryGeneral_t;
typedef struct __RFC_STRUCT rfc_dataEntryMulti_s rfc_dataEntryMulti_t;
typedef struct __RFC_STRUCT rfc_dataEntryPointer_s rfc_dataEntryPointer_t;
typedef struct __RFC_STRUCT rfc_dataEntryPartial_s rfc_dataEntryPartial_t;
//! \addtogroup dataEntry
//! @{
struct __RFC_STRUCT rfc_dataEntry_s {
uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry
uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to
struct {
uint8_t type:2; //!< \brief Type of data entry structure<br>
//!< 0: General data entry <br>
//!< 1: Multi-element Rx entry<br>
//!< 2: Pointer entry<br>
//!< 3: Partial read Rx entry
uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element<br>
//!< 0: No length indicator<br>
//!< 1: One byte length indicator<br>
//!< 2: Two bytes length indicator<br>
//!< 3: <i>Reserved</i>
uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated
//!< by the radio CPU (0: 16 bytes)
} config;
uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to<br>
//!< For other entries: Number of bytes following this length field
} __RFC_STRUCT_ATTR;
//! @}
//! \addtogroup dataEntryGeneral
//! @{
//! General data entry structure (type = 0)
struct __RFC_STRUCT rfc_dataEntryGeneral_s {
uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry
uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to
struct {
uint8_t type:2; //!< \brief Type of data entry structure<br>
//!< 0: General data entry <br>
//!< 1: Multi-element Rx entry<br>
//!< 2: Pointer entry<br>
//!< 3: Partial read Rx entry
uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element<br>
//!< 0: No length indicator<br>
//!< 1: One byte length indicator<br>
//!< 2: Two bytes length indicator<br>
//!< 3: <i>Reserved</i>
uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated
//!< by the radio CPU (0: 16 bytes)
} config;
uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to<br>
//!< For other entries: Number of bytes following this length field
uint8_t data; //!< First byte of the data array to be received or transmitted
} __RFC_STRUCT_ATTR;
//! @}
//! \addtogroup dataEntryMulti
//! @{
//! Multi-element data entry structure (type = 1)
struct __RFC_STRUCT rfc_dataEntryMulti_s {
uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry
uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to
struct {
uint8_t type:2; //!< \brief Type of data entry structure<br>
//!< 0: General data entry <br>
//!< 1: Multi-element Rx entry<br>
//!< 2: Pointer entry<br>
//!< 3: Partial read Rx entry
uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element<br>
//!< 0: No length indicator<br>
//!< 1: One byte length indicator<br>
//!< 2: Two bytes length indicator<br>
//!< 3: <i>Reserved</i>
uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated
//!< by the radio CPU (0: 16 bytes)
} config;
uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to<br>
//!< For other entries: Number of bytes following this length field
uint16_t numElements; //!< Number of entry elements committed in the entry
uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU
uint8_t rxData; //!< First byte of the data array of received data entry elements
} __RFC_STRUCT_ATTR;
//! @}
//! \addtogroup dataEntryPointer
//! @{
//! Pointer data entry structure (type = 2)
struct __RFC_STRUCT rfc_dataEntryPointer_s {
uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry
uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to
struct {
uint8_t type:2; //!< \brief Type of data entry structure<br>
//!< 0: General data entry <br>
//!< 1: Multi-element Rx entry<br>
//!< 2: Pointer entry<br>
//!< 3: Partial read Rx entry
uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element<br>
//!< 0: No length indicator<br>
//!< 1: One byte length indicator<br>
//!< 2: Two bytes length indicator<br>
//!< 3: <i>Reserved</i>
uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated
//!< by the radio CPU (0: 16 bytes)
} config;
uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to<br>
//!< For other entries: Number of bytes following this length field
uint8_t* pData; //!< Pointer to data buffer of data to be received ro transmitted
} __RFC_STRUCT_ATTR;
//! @}
//! \addtogroup dataEntryPartial
//! @{
//! Partial read data entry structure (type = 3)
struct __RFC_STRUCT rfc_dataEntryPartial_s {
uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry
uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to
struct {
uint8_t type:2; //!< \brief Type of data entry structure<br>
//!< 0: General data entry <br>
//!< 1: Multi-element Rx entry<br>
//!< 2: Pointer entry<br>
//!< 3: Partial read Rx entry
uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element<br>
//!< 0: No length indicator<br>
//!< 1: One byte length indicator<br>
//!< 2: Two bytes length indicator<br>
//!< 3: <i>Reserved</i>
uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated
//!< by the radio CPU (0: 16 bytes)
} config;
uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to<br>
//!< For other entries: Number of bytes following this length field
struct {
uint16_t numElements:13; //!< Number of entry elements committed in the entry
uint16_t bEntryOpen:1; //!< 1 if the entry contains an element that is still open for appending data
uint16_t bFirstCont:1; //!< 1 if the first element is a continuation of the last packet from the previous entry
uint16_t bLastCont:1; //!< 1 if the packet in the last element continues in the next entry
} pktStatus;
uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU
uint8_t rxData; //!< First byte of the data array of received data entry elements
} __RFC_STRUCT_ATTR;
//! @}
//! @}
//! @}
#endif

210
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_cmd.h
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@ -1,210 +0,0 @@
/******************************************************************************
* Filename: rf_hs_cmd.h
* Revised: 2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018)
* Revision: 18170
*
* Description: CC13x2/CC26x2 API for high-speed mode commands
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __HS_CMD_H
#define __HS_CMD_H
#ifndef __RFC_STRUCT
#define __RFC_STRUCT
#endif
#ifndef __RFC_STRUCT_ATTR
#if defined(__GNUC__)
#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4)))
#elif defined(__TI_ARM__)
#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4)))
#else
#define __RFC_STRUCT_ATTR
#endif
#endif
//! \addtogroup rfc
//! @{
//! \addtogroup hs_cmd
//! @{
#include <stdint.h>
#include "rf_mailbox.h"
#include "rf_common_cmd.h"
typedef struct __RFC_STRUCT rfc_CMD_HS_TX_s rfc_CMD_HS_TX_t;
typedef struct __RFC_STRUCT rfc_CMD_HS_RX_s rfc_CMD_HS_RX_t;
typedef struct __RFC_STRUCT rfc_hsRxOutput_s rfc_hsRxOutput_t;
typedef struct __RFC_STRUCT rfc_hsRxStatus_s rfc_hsRxStatus_t;
//! \addtogroup CMD_HS_TX
//! @{
#define CMD_HS_TX 0x3841
//! High-Speed Transmit Command
struct __RFC_STRUCT rfc_CMD_HS_TX_s {
uint16_t commandNo; //!< The command ID number 0x3841
uint16_t status; //!< \brief An integer telling the status of the command. This value is
//!< updated by the radio CPU during operation and may be read by the
//!< system CPU at any time.
rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
struct {
uint8_t triggerType:4; //!< The type of trigger
uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
//!< 1: CMD_TRIGGER can be used as an alternative trigger
uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
//!< 1: A trigger in the past is triggered as soon as possible
} startTrigger; //!< Identification of the trigger that starts the operation
struct {
uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
} condition;
struct {
uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command<br>
//!< 1: Turn frequency synth off after command
uint8_t bUseCrc:1; //!< \brief 0: Do not append CRC<br>
//!< 1: Append CRC
uint8_t bVarLen:1; //!< \brief 0: Fixed length<br>
//!< 1: Transmit length as first half-word
uint8_t bCheckQAtEnd:1; //!< \brief 0: Always end with HS_DONE_OK when packet has been transmitted<br>
//!< 1: Check if Tx queue is empty when packet has been transmitted
} pktConf;
uint8_t __dummy0;
dataQueue_t* pQueue; //!< Pointer to Tx queue
} __RFC_STRUCT_ATTR;
//! @}
//! \addtogroup CMD_HS_RX
//! @{
#define CMD_HS_RX 0x3842
//! High-Speed Receive Command
struct __RFC_STRUCT rfc_CMD_HS_RX_s {
uint16_t commandNo; //!< The command ID number 0x3842
uint16_t status; //!< \brief An integer telling the status of the command. This value is
//!< updated by the radio CPU during operation and may be read by the
//!< system CPU at any time.
rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
struct {
uint8_t triggerType:4; //!< The type of trigger
uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
//!< 1: CMD_TRIGGER can be used as an alternative trigger
uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
//!< 1: A trigger in the past is triggered as soon as possible
} startTrigger; //!< Identification of the trigger that starts the operation
struct {
uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
} condition;
struct {
uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command<br>
//!< 1: Turn frequency synth off after command
uint8_t bUseCrc:1; //!< \brief 0: Do not receive or check CRC<br>
//!< 1: Receive and check CRC
uint8_t bVarLen:1; //!< \brief 0: Fixed length<br>
//!< 1: Receive length as first byte
uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly<br>
//!< 1: Go back to sync search after receiving a packet correctly
uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error<br>
//!< 1: Go back to sync search after receiving a packet with CRC error
uint8_t addressMode:2; //!< \brief 0: No address check<br>
//!< 1: Accept <code>address0</code> and <code>address1</code><br>
//!< 2: Accept <code>address0</code>, <code>address1</code>, and 0x0000<br>
//!< 3: Accept <code>address0</code>, <code>address1</code>, 0x0000, and 0xFFFF
} pktConf;
struct {
uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue
uint8_t bIncludeLen:1; //!< If 1, include the received length field in the stored packet; otherwise discard it
uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise 3scard it
uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue
uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue
} rxConf;
uint16_t maxPktLen; //!< Packet length for fixed length; maximum packet length for variable length
uint16_t address0; //!< Address
uint16_t address1; //!< Address (set equal to <code>address0</code> to accept only one address)
uint8_t __dummy0;
struct {
uint8_t triggerType:4; //!< The type of trigger
uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
//!< 1: CMD_TRIGGER can be used as an alternative trigger
uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
//!< 1: A trigger in the past is triggered as soon as possible
} endTrigger; //!< Trigger classifier for ending the operation
ratmr_t endTime; //!< Time used together with <code>endTrigger</code> for ending the operation
dataQueue_t* pQueue; //!< Pointer to receive queue
rfc_hsRxOutput_t *pOutput; //!< Pointer to output structure
} __RFC_STRUCT_ATTR;
//! @}
//! \addtogroup hsRxOutput
//! @{
//! Output structure for CMD_HS_RX
struct __RFC_STRUCT rfc_hsRxOutput_s {
uint16_t nRxOk; //!< Number of packets that have been received with CRC OK
uint16_t nRxNok; //!< Number of packets that have been received with CRC error
uint16_t nRxAborted; //!< Number of packets not received due to illegal length or address mismatch
uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space
int8_t lastRssi; //!< RSSI of last received packet
ratmr_t timeStamp; //!< Time stamp of last received packet
} __RFC_STRUCT_ATTR;
//! @}
//! \addtogroup hsRxStatus
//! @{
//! Receive status word that may be appended to message in receive buffer
struct __RFC_STRUCT rfc_hsRxStatus_s {
struct {
uint16_t rssi:8; //!< RSSI of the received packet in dBm (signed)
uint16_t bCrcErr:1; //!< \brief 0: Packet received OK<br>
//!< 1: Packet received with CRC error
uint16_t addressInd:2; //!< \brief 0: Received <code>address0</code> (or no address check)<br>
//!< 1: Received <code>address1</code><br>
//!< 2: Received address 0x0000<br>
//!< 3: Received address 0xFFFF
} status;
} __RFC_STRUCT_ATTR;
//! @}
//! @}
//! @}
#endif

65
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_mailbox.h
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@ -1,65 +0,0 @@
/******************************************************************************
* Filename: rf_hs_mailbox.h
* Revised: 2018-01-15 15:58:36 +0100 (Mon, 15 Jan 2018)
* Revision: 18171
*
* Description: Definitions for high-speed mode radio interface
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef _HS_MAILBOX_H
#define _HS_MAILBOX_H
/// \name Radio operation status
///@{
/// \name Operation finished normally
///@{
#define HS_DONE_OK 0x3440 ///< Operation ended normally
#define HS_DONE_RXTIMEOUT 0x3441 ///< Operation stopped after end trigger while waiting for sync
#define HS_DONE_RXERR 0x3442 ///< Operation ended after CRC error
#define HS_DONE_TXBUF 0x3443 ///< Tx queue was empty at start of operation
#define HS_DONE_ENDED 0x3444 ///< Operation stopped after end trigger during reception
#define HS_DONE_STOPPED 0x3445 ///< Operation stopped after stop command
#define HS_DONE_ABORT 0x3446 ///< Operation aborted by abort command
///@}
/// \name Operation finished with error
///@{
#define HS_ERROR_PAR 0x3840 ///< Illegal parameter
#define HS_ERROR_RXBUF 0x3841 ///< No available Rx buffer at the start of a packet
#define HS_ERROR_NO_SETUP 0x3842 ///< Radio was not set up in a compatible mode
#define HS_ERROR_NO_FS 0x3843 ///< Synth was not programmed when running Rx or Tx
#define HS_ERROR_RXOVF 0x3844 ///< Rx overflow observed during operation
#define HS_ERROR_TXUNF 0x3845 ///< Tx underflow observed during operation
///@}
///@}
#endif

628
ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_cmd.h
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@ -1,628 +0,0 @@
/******************************************************************************
* Filename: rf_ieee_cmd.h
* Revised: 2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018)
* Revision: 18170
*
* Description: CC13x2/CC26x2 API for IEEE 802.15.4 commands
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __IEEE_CMD_H
#define __IEEE_CMD_H
#ifndef __RFC_STRUCT
#define __RFC_STRUCT
#endif
#ifndef __RFC_STRUCT_ATTR
#if defined(__GNUC__)
#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4)))
#elif defined(__TI_ARM__)
#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4)))
#else
#define __RFC_STRUCT_ATTR
#endif
#endif
//! \addtogroup rfc
//! @{
//! \addtogroup ieee_cmd
//! @{
#include <stdint.h>
#include "rf_mailbox.h"
#include "rf_common_cmd.h"
typedef struct __RFC_STRUCT rfc_CMD_IEEE_RX_s rfc_CMD_IEEE_RX_t;
typedef struct __RFC_STRUCT rfc_CMD_IEEE_ED_SCAN_s rfc_CMD_IEEE_ED_SCAN_t;
typedef struct __RFC_STRUCT rfc_CMD_IEEE_TX_s rfc_CMD_IEEE_TX_t;
typedef struct __RFC_STRUCT rfc_CMD_IEEE_CSMA_s rfc_CMD_IEEE_CSMA_t;
typedef struct __RFC_STRUCT rfc_CMD_IEEE_RX_ACK_s rfc_CMD_IEEE_RX_ACK_t;
typedef struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_BG_s rfc_CMD_IEEE_ABORT_BG_t;
typedef struct __RFC_STRUCT rfc_CMD_IEEE_MOD_CCA_s rfc_CMD_IEEE_MOD_CCA_t;
typedef struct __RFC_STRUCT rfc_CMD_IEEE_MOD_FILT_s rfc_CMD_IEEE_MOD_FILT_t;
typedef struct __RFC_STRUCT rfc_CMD_IEEE_MOD_SRC_MATCH_s rfc_CMD_IEEE_MOD_SRC_MATCH_t;
typedef struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_FG_s rfc_CMD_IEEE_ABORT_FG_t;
typedef struct __RFC_STRUCT rfc_CMD_IEEE_STOP_FG_s rfc_CMD_IEEE_STOP_FG_t;
typedef struct __RFC_STRUCT rfc_CMD_IEEE_CCA_REQ_s rfc_CMD_IEEE_CCA_REQ_t;
typedef struct __RFC_STRUCT rfc_ieeeRxOutput_s rfc_ieeeRxOutput_t;
typedef struct __RFC_STRUCT rfc_shortAddrEntry_s rfc_shortAddrEntry_t;
typedef struct __RFC_STRUCT rfc_ieeeRxCorrCrc_s rfc_ieeeRxCorrCrc_t;
//! \addtogroup CMD_IEEE_RX
//! @{
#define CMD_IEEE_RX 0x2801
//! IEEE 802.15.4 Receive Command
struct __RFC_STRUCT rfc_CMD_IEEE_RX_s {
uint16_t commandNo; //!< The command ID number 0x2801
uint16_t status; //!< \brief An integer telling the status of the command. This value is
//!< updated by the radio CPU during operation and may be read by the
//!< system CPU at any time.
rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
struct {
uint8_t triggerType:4; //!< The type of trigger
uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
//!< 1: CMD_TRIGGER can be used as an alternative trigger
uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
//!< 1: A trigger in the past is triggered as soon as possible
} startTrigger; //!< Identification of the trigger that starts the operation
struct {
uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
} condition;
uint8_t channel; //!< \brief Channel to tune to in the start of the operation<br>
//!< 0: Use existing channel<br>
//!< 11--26: Use as IEEE 802.15.4 channel, i.e. frequency is (2405 + 5 &times; (channel - 11)) MHz<br>
//!< 60--207: Frequency is (2300 + channel) MHz<br>
//!< Others: <i>Reserved</i>
struct {
uint8_t bAutoFlushCrc:1; //!< If 1, automatically remove packets with CRC error from Rx queue
uint8_t bAutoFlushIgn:1; //!< If 1, automatically remove packets that can be ignored according to frame filtering from Rx queue
uint8_t bIncludePhyHdr:1; //!< If 1, include the received PHY header field in the stored packet; otherwise discard it
uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it
uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue
uint8_t bAppendCorrCrc:1; //!< If 1, append a correlation value and CRC result byte to the packet in the Rx queue
uint8_t bAppendSrcInd:1; //!< If 1, append an index from the source matching algorithm
uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue
} rxConfig;
dataQueue_t* pRxQ; //!< Pointer to receive queue
rfc_ieeeRxOutput_t *pOutput; //!< Pointer to output structure (NULL: Do not store results)
struct {
uint16_t frameFiltEn:1; //!< \brief 0: Disable frame filtering<br>
//!< 1: Enable frame filtering
uint16_t frameFiltStop:1; //!< \brief 0: Receive all packets to the end<br>
//!< 1: Stop receiving frame once frame filtering has caused the frame to be rejected.
uint16_t autoAckEn:1; //!< \brief 0: Disable auto ACK<br>
//!< 1: Enable auto ACK.
uint16_t slottedAckEn:1; //!< \brief 0: Non-slotted ACK<br>
//!< 1: Slotted ACK.
uint16_t autoPendEn:1; //!< \brief 0: Auto-pend disabled<br>
//!< 1: Auto-pend enabled
uint16_t defaultPend:1; //!< The value of the pending data bit in auto ACK packets that are not subject to auto-pend
uint16_t bPendDataReqOnly:1; //!< \brief 0: Use auto-pend for any packet<br>
//!< 1: Use auto-pend for data request packets only
uint16_t bPanCoord:1; //!< \brief 0: Device is not PAN coordinator<br>
//!< 1: Device is PAN coordinator
uint16_t maxFrameVersion:2; //!< Reject frames where the frame version field in the FCF is greater than this value
uint16_t fcfReservedMask:3; //!< Value to be AND-ed with the reserved part of the FCF; frame rejected if result is non-zero
uint16_t modifyFtFilter:2; //!< \brief Treatment of MSB of frame type field before frame-type filtering:<br>
//!< 0: No modification<br>
//!< 1: Invert MSB<br>
//!< 2: Set MSB to 0<br>
//!< 3: Set MSB to 1
uint16_t bStrictLenFilter:1; //!< \brief 0: Accept acknowledgement frames of any length >= 5<br>
//!< 1: Accept only acknowledgement frames of length 5
} frameFiltOpt; //!< Frame filtering options
struct {
uint8_t bAcceptFt0Beacon:1; //!< \brief Treatment of frames with frame type 000 (beacon):<br>
//!< 0: Reject<br>
//!< 1: Accept
uint8_t bAcceptFt1Data:1; //!< \brief Treatment of frames with frame type 001 (data):<br>
//!< 0: Reject<br>
//!< 1: Accept
uint8_t bAcceptFt2Ack:1; //!< \brief Treatment of frames with frame type 010 (ACK):<br>
//!< 0: Reject, unless running ACK receive command<br>
//!< 1: Always accept
uint8_t bAcceptFt3MacCmd:1; //!< \brief Treatment of frames with frame type 011 (MAC command):<br>
//!< 0: Reject<br>
//!< 1: Accept
uint8_t bAcceptFt4Reserved:1; //!< \brief Treatment of frames with frame type 100 (reserved):<br>
//!< 0: Reject<br>
//!< 1: Accept
uint8_t bAcceptFt5Reserved:1; //!< \brief Treatment of frames with frame type 101 (reserved):<br>
//!< 0: Reject<br>
//!< 1: Accept
uint8_t bAcceptFt6Reserved:1; //!< \brief Treatment of frames with frame type 110 (reserved):<br>
//!< 0: Reject<br>
//!< 1: Accept
uint8_t bAcceptFt7Reserved:1; //!< \brief Treatment of frames with frame type 111 (reserved):<br>
//!< 0: Reject<br>
//!< 1: Accept
} frameTypes; //!< Frame types to receive in frame filtering
struct {
uint8_t ccaEnEnergy:1; //!< Enable energy scan as CCA source
uint8_t ccaEnCorr:1; //!< Enable correlator based carrier sense as CCA source
uint8_t ccaEnSync:1; //!< Enable sync found based carrier sense as CCA source
uint8_t ccaCorrOp:1; //!< \brief Operator to use between energy based and correlator based CCA<br>
//!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy<br>
//!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy
uint8_t ccaSyncOp:1; //!< \brief Operator to use between sync found based CCA and the others<br>
//!< 0: Always report busy channel if ccaSync is busy<br>
//!< 1: Always report idle channel if ccaSync is idle
uint8_t ccaCorrThr:2; //!< Threshold for number of correlation peaks in correlator based carrier sense
} ccaOpt; //!< CCA options
int8_t ccaRssiThr; //!< RSSI threshold for CCA
uint8_t __dummy0;
uint8_t numExtEntries; //!< Number of extended address entries
uint8_t numShortEntries; //!< Number of short address entries
uint32_t* pExtEntryList; //!< Pointer to list of extended address entries
uint32_t* pShortEntryList; //!< Pointer to list of short address entries
uint64_t localExtAddr; //!< The extended address of the local device
uint16_t localShortAddr; //!< The short address of the local device
uint16_t localPanID; //!< The PAN ID of the local device
uint16_t __dummy1;
uint8_t __dummy2;
struct {
uint8_t triggerType:4; //!< The type of trigger
uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
//!< 1: CMD_TRIGGER can be used as an alternative trigger
uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
//!< 1: A trigger in the past is triggered as soon as possible
} endTrigger; //!< Trigger that causes the device to end the Rx operation
ratmr_t endTime; //!< \brief Time used together with <code>endTrigger</code> that causes the device to end the Rx
//!< operation
} __RFC_STRUCT_ATTR;
//! @}
//! \addtogroup CMD_IEEE_ED_SCAN
//! @{
#define CMD_IEEE_ED_SCAN 0x2802
//! IEEE 802.15.4 Energy Detect Scan Command
struct __RFC_STRUCT rfc_CMD_IEEE_ED_SCAN_s {
uint16_t commandNo; //!< The command ID number 0x2802
uint16_t status; //!< \brief An integer telling the status of the command. This value is
//!< updated by the radio CPU during operation and may be read by the
//!< system CPU at any time.
rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
struct {
uint8_t triggerType:4; //!< The type of trigger
uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
//!< 1: CMD_TRIGGER can be used as an alternative trigger
uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
//!< 1: A trigger in the past is triggered as soon as possible
} startTrigger; //!< Identification of the trigger that starts the operation
struct {
uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
} condition;
uint8_t channel; //!< \brief Channel to tune to in the start of the operation<br>
//!< 0: Use existing channel<br>
//!< 11--26: Use as IEEE 802.15.4 channel, i.e. frequency is (2405 + 5 &times; (channel - 11)) MHz<br>
//!< 60--207: Frequency is (2300 + channel) MHz<br>
//!< Others: <i>Reserved</i>
struct {
uint8_t ccaEnEnergy:1; //!< Enable energy scan as CCA source
uint8_t ccaEnCorr:1; //!< Enable correlator based carrier sense as CCA source
uint8_t ccaEnSync:1; //!< Enable sync found based carrier sense as CCA source
uint8_t ccaCorrOp:1; //!< \brief Operator to use between energy based and correlator based CCA<br>
//!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy<br>
//!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy
uint8_t ccaSyncOp:1; //!< \brief Operator to use between sync found based CCA and the others<br>
//!< 0: Always report busy channel if ccaSync is busy<br>
//!< 1: Always report idle channel if ccaSync is idle
uint8_t ccaCorrThr:2; //!< Threshold for number of correlation peaks in correlator based carrier sense
} ccaOpt; //!< CCA options
int8_t ccaRssiThr; //!< RSSI threshold for CCA
uint8_t __dummy0;
int8_t maxRssi; //!< The maximum RSSI recorded during the ED scan
struct {
uint8_t triggerType:4; //!< The type of trigger
uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
//!< 1: CMD_TRIGGER can be used as an alternative trigger
uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
//!< 1: A trigger in the past is triggered as soon as possible
} endTrigger; //!< Trigger that causes the device to end the Rx operation
ratmr_t endTime; //!< \brief Time used together with <code>endTrigger</code> that causes the device to end the Rx
//!< operation
} __RFC_STRUCT_ATTR;
//! @}
//! \addtogroup CMD_IEEE_TX
//! @{
#define CMD_IEEE_TX 0x2C01
//! IEEE 802.15.4 Transmit Command
struct __RFC_STRUCT rfc_CMD_IEEE_TX_s {
uint16_t commandNo; //!< The command ID number 0x2C01
uint16_t status; //!< \brief An integer telling the status of the command. This value is
//!< updated by the radio CPU during operation and may be read by the
//!< system CPU at any time.
rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
struct {
uint8_t triggerType:4; //!< The type of trigger
uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
//!< 1: CMD_TRIGGER can be used as an alternative trigger
uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
//!< 1: A trigger in the past is triggered as soon as possible
} startTrigger; //!< Identification of the trigger that starts the operation
struct {
uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
} condition;
struct {
uint8_t bIncludePhyHdr:1; //!< \brief 0: Find PHY header automatically<br>
//!< 1: Insert PHY header from the buffer
uint8_t bIncludeCrc:1; //!< \brief 0: Append automatically calculated CRC<br>
//!< 1: Insert FCS (CRC) from the buffer
uint8_t :1;
uint8_t payloadLenMsb:5; //!< \brief Most significant bits of payload length. Should only be non-zero to create long
//!< non-standard packets for test purposes
} txOpt;
uint8_t payloadLen; //!< Number of bytes in the payload
uint8_t* pPayload; //!< Pointer to payload buffer of size <code>payloadLen</code>
ratmr_t timeStamp; //!< Time stamp of transmitted frame
} __RFC_STRUCT_ATTR;
//! @}
//! \addtogroup CMD_IEEE_CSMA
//! @{
#define CMD_IEEE_CSMA 0x2C02
//! IEEE 802.15.4 CSMA-CA Command
struct __RFC_STRUCT rfc_CMD_IEEE_CSMA_s {
uint16_t commandNo; //!< The command ID number 0x2C02
uint16_t status; //!< \brief An integer telling the status of the command. This value is
//!< updated by the radio CPU during operation and may be read by the
//!< system CPU at any time.
rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
struct {
uint8_t triggerType:4; //!< The type of trigger
uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
//!< 1: CMD_TRIGGER can be used as an alternative trigger
uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
//!< 1: A trigger in the past is triggered as soon as possible
} startTrigger; //!< Identification of the trigger that starts the operation
struct {
uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
} condition;
uint16_t randomState; //!< The state of the pseudo-random generator
uint8_t macMaxBE; //!< The IEEE 802.15.4 MAC parameter <i>macMaxBE</i>
uint8_t macMaxCSMABackoffs; //!< The IEEE 802.15.4 MAC parameter <i>macMaxCSMABackoffs</i>
struct {
uint8_t initCW:5; //!< The initialization value for the CW parameter
uint8_t bSlotted:1; //!< \brief 0: non-slotted CSMA<br>
//!< 1: slotted CSMA
uint8_t rxOffMode:2; //!< \brief 0: RX stays on during CSMA backoffs<br>
//!< 1: The CSMA-CA algorithm will suspend the receiver if no frame is being received<br>
//!< 2: The CSMA-CA algorithm will suspend the receiver if no frame is being received,
//!< or after finishing it (including auto ACK) otherwise<br>
//!< 3: The CSMA-CA algorithm will suspend the receiver immediately during back-offs
} csmaConfig;
uint8_t NB; //!< The NB parameter from the IEEE 802.15.4 CSMA-CA algorithm
uint8_t BE; //!< The BE parameter from the IEEE 802.15.4 CSMA-CA algorithm
uint8_t remainingPeriods; //!< The number of remaining periods from a paused backoff countdown
int8_t lastRssi; //!< RSSI measured at the last CCA operation
struct {
uint8_t triggerType:4; //!< The type of trigger
uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
//!< 1: CMD_TRIGGER can be used as an alternative trigger
uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
//!< 1: A trigger in the past is triggered as soon as possible
} endTrigger; //!< Trigger that causes the device to end the CSMA-CA operation
ratmr_t lastTimeStamp; //!< Time of the last CCA operation
ratmr_t endTime; //!< \brief Time used together with <code>endTrigger</code> that causes the device to end the
//!< CSMA-CA operation
} __RFC_STRUCT_ATTR;
//! @}
//! \addtogroup CMD_IEEE_RX_ACK
//! @{
#define CMD_IEEE_RX_ACK 0x2C03
//! IEEE 802.15.4 Receive Acknowledgement Command
struct __RFC_STRUCT rfc_CMD_IEEE_RX_ACK_s {
uint16_t commandNo; //!< The command ID number 0x2C03
uint16_t status; //!< \brief An integer telling the status of the command. This value is
//!< updated by the radio CPU during operation and may be read by the
//!< system CPU at any time.
rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
struct {
uint8_t triggerType:4; //!< The type of trigger
uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
//!< 1: CMD_TRIGGER can be used as an alternative trigger
uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
//!< 1: A trigger in the past is triggered as soon as possible
} startTrigger; //!< Identification of the trigger that starts the operation
struct {
uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
} condition;
uint8_t seqNo; //!< Sequence number to expect
struct {
uint8_t triggerType:4; //!< The type of trigger
uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
//!< 1: CMD_TRIGGER can be used as an alternative trigger
uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
//!< 1: A trigger in the past is triggered as soon as possible
} endTrigger; //!< Trigger that causes the device to give up acknowledgement reception
ratmr_t endTime; //!< \brief Time used together with <code>endTrigger</code> that causes the device to give up
//!< acknowledgement reception
} __RFC_STRUCT_ATTR;
//! @}
//! \addtogroup CMD_IEEE_ABORT_BG
//! @{
#define CMD_IEEE_ABORT_BG 0x2C04
//! IEEE 802.15.4 Abort Background Level Command
struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_BG_s {
uint16_t commandNo; //!< The command ID number 0x2C04
uint16_t status; //!< \brief An integer telling the status of the command. This value is
//!< updated by the radio CPU during operation and may be read by the
//!< system CPU at any time.
rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
struct {
uint8_t triggerType:4; //!< The type of trigger
uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
//!< 1: CMD_TRIGGER can be used as an alternative trigger
uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
//!< 1: A trigger in the past is triggered as soon as possible
} startTrigger; //!< Identification of the trigger that starts the operation
struct {
uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
} condition;
} __RFC_STRUCT_ATTR;
//! @}
//! \addtogroup CMD_IEEE_MOD_CCA
//! @{
#define CMD_IEEE_MOD_CCA 0x2001
//! IEEE 802.15.4 Modify CCA Parameter Command
struct __RFC_STRUCT rfc_CMD_IEEE_MOD_CCA_s {
uint16_t commandNo; //!< The command ID number 0x2001
struct {
uint8_t ccaEnEnergy:1; //!< Enable energy scan as CCA source
uint8_t ccaEnCorr:1; //!< Enable correlator based carrier sense as CCA source
uint8_t ccaEnSync:1; //!< Enable sync found based carrier sense as CCA source
uint8_t ccaCorrOp:1; //!< \brief Operator to use between energy based and correlator based CCA<br>
//!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy<br>
//!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy
uint8_t ccaSyncOp:1; //!< \brief Operator to use between sync found based CCA and the others<br>
//!< 0: Always report busy channel if ccaSync is busy<br>
//!< 1: Always report idle channel if ccaSync is idle
uint8_t ccaCorrThr:2; //!< Threshold for number of correlation peaks in correlator based carrier sense
} newCcaOpt; //!< New value of <code>ccaOpt</code> for the running background level operation
int8_t newCcaRssiThr; //!< New value of <code>ccaRssiThr</code> for the running background level operation
} __RFC_STRUCT_ATTR;
//! @}
//! \addtogroup CMD_IEEE_MOD_FILT
//! @{
#define CMD_IEEE_MOD_FILT 0x2002
//! IEEE 802.15.4 Modify Frame Filtering Parameter Command
struct __RFC_STRUCT rfc_CMD_IEEE_MOD_FILT_s {
uint16_t commandNo; //!< The command ID number 0x2002
struct {
uint16_t frameFiltEn:1; //!< \brief 0: Disable frame filtering<br>
//!< 1: Enable frame filtering
uint16_t frameFiltStop:1; //!< \brief 0: Receive all packets to the end<br>
//!< 1: Stop receiving frame once frame filtering has caused the frame to be rejected.
uint16_t autoAckEn:1; //!< \brief 0: Disable auto ACK<br>
//!< 1: Enable auto ACK.
uint16_t slottedAckEn:1; //!< \brief 0: Non-slotted ACK<br>
//!< 1: Slotted ACK.
uint16_t autoPendEn:1; //!< \brief 0: Auto-pend disabled<br>
//!< 1: Auto-pend enabled
uint16_t defaultPend:1; //!< The value of the pending data bit in auto ACK packets that are not subject to auto-pend
uint16_t bPendDataReqOnly:1; //!< \brief 0: Use auto-pend for any packet<br>
//!< 1: Use auto-pend for data request packets only
uint16_t bPanCoord:1; //!< \brief 0: Device is not PAN coordinator<br>
//!< 1: Device is PAN coordinator
uint16_t maxFrameVersion:2; //!< Reject frames where the frame version field in the FCF is greater than this value
uint16_t fcfReservedMask:3; //!< Value to be AND-ed with the reserved part of the FCF; frame rejected if result is non-zero
uint16_t modifyFtFilter:2; //!< \brief Treatment of MSB of frame type field before frame-type filtering:<br>
//!< 0: No modification<br>
//!< 1: Invert MSB<br>
//!< 2: Set MSB to 0<br>
//!< 3: Set MSB to 1
uint16_t bStrictLenFilter:1; //!< \brief 0: Accept acknowledgement frames of any length >= 5<br>
//!< 1: Accept only acknowledgement frames of length 5
} newFrameFiltOpt; //!< New value of <code>frameFiltOpt</code> for the running background level operation
struct {
uint8_t bAcceptFt0Beacon:1; //!< \brief Treatment of frames with frame type 000 (beacon):<br>
//!< 0: Reject<br>
//!< 1: Accept
uint8_t bAcceptFt1Data:1; //!< \brief Treatment of frames with frame type 001 (data):<br>
//!< 0: Reject<br>
//!< 1: Accept
uint8_t bAcceptFt2Ack:1; //!< \brief Treatment of frames with frame type 010 (ACK):<br>
//!< 0: Reject, unless running ACK receive command<br>
//!< 1: Always accept
uint8_t bAcceptFt3MacCmd:1; //!< \brief Treatment of frames with frame type 011 (MAC command):<br>
//!< 0: Reject<br>
//!< 1: Accept
uint8_t bAcceptFt4Reserved:1; //!< \brief Treatment of frames with frame type 100 (reserved):<br>
//!< 0: Reject<br>
//!< 1: Accept
uint8_t bAcceptFt5Reserved:1; //!< \brief Treatment of frames with frame type 101 (reserved):<br>
//!< 0: Reject<br>
//!< 1: Accept
uint8_t bAcceptFt6Reserved:1; //!< \brief Treatment of frames with frame type 110 (reserved):<br>
//!< 0: Reject<br>
//!< 1: Accept
uint8_t bAcceptFt7Reserved:1; //!< \brief Treatment of frames with frame type 111 (reserved):<br>
//!< 0: Reject<br>
//!< 1: Accept
} newFrameTypes; //!< New value of <code>frameTypes</code> for the running background level operation
} __RFC_STRUCT_ATTR;
//! @}
//! \addtogroup CMD_IEEE_MOD_SRC_MATCH
//! @{
#define CMD_IEEE_MOD_SRC_MATCH 0x2003
//! IEEE 802.15.4 Enable/Disable Source Matching Entry Command
struct __RFC_STRUCT rfc_CMD_IEEE_MOD_SRC_MATCH_s {
uint16_t commandNo; //!< The command ID number 0x2003
struct {
uint8_t bEnable:1; //!< \brief 0: Disable entry<br>
//!< 1: Enable entry
uint8_t srcPend:1; //!< New value of the pending bit for the entry
uint8_t entryType:1; //!< \brief 0: Short address<br>
//!< 1: Extended address
} options;
uint8_t entryNo; //!< Index of entry to enable or disable
} __RFC_STRUCT_ATTR;
//! @}
//! \addtogroup CMD_IEEE_ABORT_FG
//! @{
#define CMD_IEEE_ABORT_FG 0x2401
//! IEEE 802.15.4 Abort Foreground Level Command
struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_FG_s {
uint16_t commandNo; //!< The command ID number 0x2401
} __RFC_STRUCT_ATTR;
//! @}
//! \addtogroup CMD_IEEE_STOP_FG
//! @{
#define CMD_IEEE_STOP_FG 0x2402
//! IEEE 802.15.4 Gracefully Stop Foreground Level Command
struct __RFC_STRUCT rfc_CMD_IEEE_STOP_FG_s {
uint16_t commandNo; //!< The command ID number 0x2402
} __RFC_STRUCT_ATTR;
//! @}
//! \addtogroup CMD_IEEE_CCA_REQ
//! @{
#define CMD_IEEE_CCA_REQ 0x2403
//! IEEE 802.15.4 CCA and RSSI Information Request Command
struct __RFC_STRUCT rfc_CMD_IEEE_CCA_REQ_s {
uint16_t commandNo; //!< The command ID number 0x2403
int8_t currentRssi; //!< The RSSI currently observed on the channel
int8_t maxRssi; //!< The maximum RSSI observed on the channel since Rx was started
struct {
uint8_t ccaState:2; //!< \brief Value of the current CCA state<br>
//!< 0: Idle<br>
//!< 1: Busy<br>
//!< 2: Invalid
uint8_t ccaEnergy:2; //!< \brief Value of the current energy detect CCA state<br>
//!< 0: Idle<br>
//!< 1: Busy<br>
//!< 2: Invalid
uint8_t ccaCorr:2; //!< \brief Value of the current correlator based carrier sense CCA state<br>
//!< 0: Idle<br>
//!< 1: Busy<br>
//!< 2: Invalid
uint8_t ccaSync:1; //!< \brief Value of the current sync found based carrier sense CCA state<br>
//!< 0: Idle<br>
//!< 1: Busy
} ccaInfo;
} __RFC_STRUCT_ATTR;
//! @}
//! \addtogroup ieeeRxOutput
//! @{
//! Output structure for CMD_IEEE_RX
struct __RFC_STRUCT rfc_ieeeRxOutput_s {
uint8_t nTxAck; //!< Total number of transmitted ACK frames
uint8_t nRxBeacon; //!< Number of received beacon frames
uint8_t nRxData; //!< Number of received data frames
uint8_t nRxAck; //!< Number of received acknowledgement frames
uint8_t nRxMacCmd; //!< Number of received MAC command frames
uint8_t nRxReserved; //!< Number of received frames with reserved frame type
uint8_t nRxNok; //!< Number of received frames with CRC error
uint8_t nRxIgnored; //!< Number of frames received that are to be ignored
uint8_t nRxBufFull; //!< Number of received frames discarded because the Rx buffer was full
int8_t lastRssi; //!< RSSI of last received frame
int8_t maxRssi; //!< Highest RSSI observed in the operation
uint8_t __dummy0;
ratmr_t beaconTimeStamp; //!< Time stamp of last received beacon frame
} __RFC_STRUCT_ATTR;
//! @}
//! \addtogroup shortAddrEntry
//! @{
//! Structure for short address entries
struct __RFC_STRUCT rfc_shortAddrEntry_s {
uint16_t shortAddr; //!< Short address
uint16_t panId; //!< PAN ID
} __RFC_STRUCT_ATTR;
//! @}
//! \addtogroup ieeeRxCorrCrc
//! @{
//! Receive status byte that may be appended to message in receive buffer
struct __RFC_STRUCT rfc_ieeeRxCorrCrc_s {
struct {
uint8_t corr:6; //!< The correlation value
uint8_t bIgnore:1; //!< 1 if the packet should be rejected by frame filtering, 0 otherwise
uint8_t bCrcErr:1; //!< 1 if the packet was received with CRC error, 0 otherwise
} status;
} __RFC_STRUCT_ATTR;
//! @}
//! @}
//! @}
#endif

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