Rename the CAN data phase API functions to timing_data_* for consistency:
- can_get_timing_min_data() -> can_get_timing_data_min()
- can_get_timing_max_data() -> can_get_timing_data_max()
- .timing_min_data -> timing_data_min
- .timing_max_data -> timing_data_max
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Removes label and compatible properties
from the flash section. The properties are
provided by included stm32h723.dtsi.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Removes label and compatible properties
from the flash section. The properties are
provided by included stm32h723.dtsi.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
* Corrects SRAM0 size. The `TCM_AXI_SHARED`
is `000` after reset. That means ITCM
is shared with SRAM0.
* Adds missing SRAM1,2,4, and ITCM
regions.
* Adds label and compatible properties
to the flash section.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Espressif boards cannot have ble and wifi
CI build tests due to binary blobs policies.
This removes refered tests.
west.yml: update hal repository to get updates
that allows building using Zephyr's SDK.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add reentrant _gettimeofday_ call so that build
won't fail. This is only a workaround for now.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This PR adds missing configuration to enable newlibc
and cpp code to run in ESP32S2 SoC. This isn't enough though.
Toolchain changes are also needed and will come up next.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Remove ESP32 and ESP32S2 from not working samples
and tests. Reason for not working is not enough memory
space in RAM to execute it. This can be worked out as next steps.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Make the available heap for the 128k bank smaller
so that it frees up space for some samples
as pktqueue and smp. In the context of toolchain,
this enables having twister test to pass in those tests
that requires more memory.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Current Espressif porting requires standard include as
part of hal implementation. compiler_flags.cmake checks for
variant name to keep those stdinc in build.
Instead of using variant name as check, use this new CONFIG
to make it clear and to allow having toolchain integrated
in zephyr-sdk package.
stdinc dependency in hal_espressif will be worked out and removed
soon.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add reentrant _gettimeofday_ call so that build
won't fail. This is only a workaround for now.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This PR adds missing configuration to enable newlibc
and cpp code to run in ESP32 SoC. This isn't enough though.
Toolchain changes are also needed and will come up next.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
UART0 is routed to onboard debugger on LPC11u68 EVK. Change the default
console from UART4 to UART0 to enable output on the onboard debugger
console.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable pin control for lpc11u6x soc by selecting CONFIG_PINCTRL=y.
At this time no drivers are ported.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable pin control for lpc11u6x i2c driver, and remove pinmux usage from
board level DTS files.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
convert lpc11u6x syscon clock driver to pin control, and remove all
pinmux usage from driver and syscon dts node.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update pin control driver for lpc11u6x. This SOC does not have a HAL,
so fsl_clock is not available. It also lacks a slew-rate field in the
IOCON register, so this property must be optional.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
switch gpio driver to use pio nodes to configure pin control settings,
and stop using pinmux driver within gpio driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Improve the power domain logging by making the log level configurable
and boosting the log level of the messages printed when the domain turns
on and off.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
The following HALs contain code that makes use of Zephyr headers, so
they have been updated with the <zephyr/...> prefix:
- Altera
- NXP
- STM32
- TI
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Adjust get_mem_region to not return region when address == end
as there will be nothing to read there. Also, a subsequent region
may have that address as a start address and would be a more appropriate
selection.
Signed-off-by: Mark Holden <mholden@fb.com>
Now we define PROPERTY_OUTPUT_FORMAT (which is used for
binutils) only for ARCv3 32 bit. Let's define it for all
ARC elf formats instead of relying on default values.
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Provide required compiler/assembler options for building with mwdt
toolchain for ARCv3 64 bit.
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Use correct gfrc version in nsim args for mdb_hs6x_smp board.
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Add nSIM-based (simulator) boards with
* nsim_hs5x - single core ARCv3 HS5x 32 bit CPU
* nsim_hs5x_smp - SMP, two core ARCv3 HS5x 32 bit CPU
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
K_THREAD_STACK_DEFINE is not correct in a header file as it may conflict
with K_THREAD_STACK_DEFINE usage in the source file.
Signed-off-by: Keith Packard <keithp@keithp.com>
Adding support for the GIC_V1 to the dc_dw USB driver
to be used by Cyclone V SoC FPGA Development Kit
Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
Cyclone V SoC FPGA supports 128Byte FIFO for UART communication,
this modification adds a feature to use 128byte FIFO serial UART
Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
LCD display is connected to the I2C bus SoC bus in the development kit,
this sample guides the user on how to use the LCD display with I2C commands
Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
Add a runner to "flash" and "debug" Cyclone V SoC FPGA Development Kit
the runner is based on OpenOCD and GDB
Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
