Change the power_domain_intel_adsp initialization priority so that it
initializes after the DMA driver that it depends on.
Fixes a few:
ERROR: /soc/dma@72c00 POST_KERNEL 40 69 <
/soc/dfpmccu@71b00/hst_domain POST_KERNEL 75 65
ERROR: /soc/dma@72400 POST_KERNEL 40 66 <
/soc/dfpmccu@71b00/hst_domain POST_KERNEL 75 65
...
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
In OpenThread, Settings are initialized after KeyManager by default.
If device uses PSA with emulated TFM, Settings have to be initialized
at the end of otPlatCryptoInit(), to be available before storing
Network Key.
Signed-off-by: Maciej Baczmanski <maciej.baczmanski@nordicsemi.no>
In some shared-memory use cases between Zephyr and other parallel
running OS, for data coherent, the non-cacheable normal memory
mapping is needed.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Add a a new source coverage for native builds
and new kconfig choice of COVERAGE mode to select which:
* COVERAGE_NATIVE_GCOV: what we had until now with native builds
* COVERAGE_NATIVE_SOURCE: a new LLVM source coverage mode
* COVERAGE_GCOV: the old COVERAGE_GCOV (embedded gcov data generation).
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Following PR #61471, ehl_crb board is now intel_ehl_crb.
Update the footprint test plan accordingly.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The original CONFIG_GDT_RESERVED_NUM_ENTRIES resides in the false
branch of ifdef LINKER_ZEPHYR_FINAL and is actually elminated
finally. It should reside in the outer ifdef clause, namely the
under ifdef CONFIG_GDT_DYNAMIC.
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
The max SPI clock frequency supported by the bmi088 according to the
bmi088 data sheet is 10MHz. Correct the vmu_rt1170 to reflect this.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Fix CONTAINER_OF usage in gpio_keys_interrupt, this should go first to
struct gpio_keys_callback and then to struct gpio_keys_pin_data. It
happens to work right now because cb_data is the first field.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix few instances of delayable work handlers using the k_work pointer
directly in a CONTAINER_OF pointing to a k_work_delayable.
This is harmless since the k_work is the first element in
k_work_delayable, but using k_work_delayable_from_work is the right way
of handling it.
Change a couple of explicit CONTAINER_OF doing the same work as the
macro in the process.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
adds sdmmc1 node on stm32f469i_disco board
to use SDIO bus for SD card access
the mandatory clock is 48 Mhz.
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
Adds new ADI Platforms section covering device drivers and bindings for
Analog Devices, Maxim Integrated, and Linear Technology.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
This change allows to register additional handlers for ICMPv6 so the
user can handle some of the messages between they are handled by the
ICMPv6 module in Zephyr by returning NET_CONTINUE.
Signed-off-by: Konrad Derda <konrad.derda@nordicsemi.no>
"callback != NULL" is used to determine if the callback is in use.
The TX complete semaphone should only be given back after setting the
callback to NULL.
This would likely only be a race condition if the ISR is processed on a
different core to the TX call.
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
The MCAN driver operates in TX queue mode (TXBC.TFQM = 1). In this mode
TXFQS.TFQPI returns the first available buffer (usually buffer zero).
Hardware is free to re-use a buffer as soon as TX completes, it does not
have to wait for the matching TX event to be processed.
If a TX completes and that TX buffer is re-used before processing the TX
event, two TX events for the same buffer occur. The first event calls the
second events TX callback, and the second event results in a NULL pointer
exception.
In a "normal" configuration, the TX event ISR will always preempt the
queuing of a TX frame to the same TX buffer.
However, this issue could occur if:
* Sending a message with ISRs temporarily disabled.
* The ISR is processed on a different core to the TX call.
The fix is to manually track which TX buffers are available, only freeing
a buffer after the TX event has been processed.
The MCAN user manual states that this is allowed:
"The application may use register TXBRP instead of the Put Index and may
place messages to any Tx Buffer without pending transmission request"
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
Move workaround methods for npcx series to soc init functions. If
there's no workaround for this series, drop its soc.c file directly.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
There was a corner case which was not handled well in a scenario, when
listening socket was closed during an active handshake with a new
client.
When a listening socket is closed, the accept callback is cleared on the
TCP context. If this happened during a handshake with a new client, i.
e. before final ACK from the client was processed, this lead to a
context leak, as application did not take ownership of the connection
(i. e. had no means to close it).
Fix this, by proactively closing the connection at the TCP level when no
accept_cb is available. Instead of ignoring the fact that no accept_cb
is available, the TCP stack will now enter TCP_FIN_WAIT_1 state and
proceed with a graceful teardown of the connection.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
getsockname() did not work properly on bound sockets, as it verified
whether the socket has an active connection before retuning result. This
is not correct, as socket after bound may not have a connection yet.
Fix this, by verifying that local_addr on an underlying net_context is
set, to determine whether socket has a local address assigned, before
returning result.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Add tests which verify that getsockname() function works as expected.
Additionally, add a teardown delay in tests involving TCP, to make sure
all resources are released before the test ends, not to interfere with
other tests.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
This adds SoC and board configs to support the dc233c core
that is available on QEMU. This core has more features than
sample_controller, such as MMU support.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The Xtensa HAL has been updated with the following changes:
* Removed intel_s1000 overlay files as it is no longer needed.
* Fix uninitialized variable warning in xthal_v2p()
* Add config and overlay files for dc233c core so we can use
QEMU with this core to test MMU code.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a function arch_xtensa_mmu_post_init() which can
be implemented on the SoC layer to perform additional MMU
initialization steps if necessary.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
...VECBASE during MMU initialization. This is to make sure
that we can use the TLB miss handling in the exception
vector after we have moved back the VECBASE during MMU
initialization. Or else we would be forever stuck in ITLB
miss because the exception vectors are not in TLB and we
cannot populate the TLB because those vectors are not in
TLB.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
...and move it to xtensa_mmu_priv.h.
This would allow the SoC layer to use the RING number if needed.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds arch_reserved_pages_update() which is called in
k_mem_manage_init() to reserve some physical pages so they
are not re-mapped. This is due to Zephyr's linker scripts
for Xtensa which often puts something before z_mapped_start
(aka .text, for example, vecbase). That space needs to be
reserved or else k_mem_map() would be mapping those that
could result in faults.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Instead of only handling data TLB misses for VECBASE, change it
to handle all data TLB misses in the double exception handler.
It is because we may encounter data TLB misses when trying to
preload page table entries inside user exception handler.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
If CONFIG_XTENSA_RPO_CACHE is not enabled, it can be assumed
that memory is not double mapped in hardware for cached and
uncached access. So we can specify those regions to have
cache via TLB.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Simply using __data_start and __data_end is not enough as
it leaves out kobject regions which is supposed to be
near .data section. So use _image_ram_start and
_image_ram_end instead to enclose data, bss and various
kobject regions (among others).
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
During MMU initialization, we clear TLB way 6 to remove all
identity mapping. Depending on CPU configuration, there are
certain number of entries per way. So use the number from
core-isa.h to clear enough entries instead of hard-coded
number 8. Specifying an entry number outside of permitted
range may result in CPU reacting in weird way so better to
avoid that.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This removes the identity map of the first 512MB in TLB way 6.
Or else it would interfere with mapped entries resulting in
double mapped TLB exception.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
MMU needs to be initialized before going in to C, so
z_xtensa_mmu_init() is called in crt1.S before call
to z_cstart(). Note that this is the default case
and crt1.S can be disabled if board and SoC desire
to do so.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Turns out not all MMU enabled Xtensa cores have vaddrstatus,
vaddr0 and vaddr1. And there does not seem to be a way to
determine whether they are available. So remove them from
the exception printout for now.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The full scale prop was incorrectly using the enum idx which was then
to be used with a look up table which used the actual range number.
This changes it to use the int directly from the dts.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Fix an "if" that should have been an "elif". This is currently causing
the script to fallback into the "do all unassigned PRs of the day" path
when a PR is specified.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
