Add support for STM32L0 clocks bindings.
Also, add a small tweak to SYSCLK selection to factorize some lines.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to ensure backward compatibility, use the dts config
only if nodes have prop "clocks".
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
To allow transition to device tree based clock configuration on
stm32 targets, rework clock_control driver to use intermediate
STM32_ macros initially defined as the equivalent Kconfig macros
for now.
Propagate the change in all code using these macros.
The reason to introduce these new macros instead of configuring
Kconfig flags using dt kconfigfunctions is that we'll need
to be able to inform users that Kconfig flags are deprecated
once the whole family conversion is done, to encourage
out of tree users to adopt this new configuration scheme.
Note: For now STM32H7 series and code is excluded.
This is the same for some series specific code such as
PLL mul/div for L0/L1 and XTRE prescaler on F1 series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Convert from device_get_binding to DEVICE_DT_GET. In doing this we
no longer need the label in the devicetree node so we remove that.
Removed all __ASSERT_NO_MSG(clk) since we'll get a build error if
DEVICE_DT_GET cant be satisfied, and the clock control api's will
handle reporting if the device_is_ready.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert clock_control drivers from:
DEVICE_AND_API_INIT -> DEVICE_DT_DEFINE
As part of this we also changed STM32_CLOCK_CONTROL_NAME to be based on
devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
move clock_control.h to drivers/clock_control.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Any word started with underscore followed by and uppercase letter or a
second underscore is a reserved word according with C99.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add "clocks" property on u(s)arts nodes on stm32 socs
Add a dt clocks binding file and rework clock_control
header file include new device tree binding file.
include/dt-bindings folder is introduced as dt-bindings
placeholder
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Following introduction of stm32cube LL based clock control driver,
remove references to former native driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Following activation of stm32 common clock driver for stm32f4 series
remove references to stm32f4 specific driver.
Change-Id: I372a0ea046007bcb34944d6b2b8880077583b1d3
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types. This handles the remaining includes and kernel, plus
touching up various points that we skipped because of include
dependancies. We also convert the PRI printf formatters in the arch
code over to normal formatters.
Jira: ZEP-2051
Change-Id: Iecbb12601a3ee4ea936fd7ddea37788a645b08b0
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
After introduction and activation of STM32Cube LL based driver on
F3 and L4 series, this commit removes the no more needed code for
native driver for these soc.
Change-Id: I266d1a3fc4b464cee34b1cc1a1a333c5bf923e41
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This new clock control driver aims at providing a lightweight
generic driver to the whole stm32 family.
Driver is based on LL Cube API and hence is for now available
only for STM32 supporting this API: stm32f3xx and stm32l4xx.
Other families should be supported soon.
Once globally supported, this unique driver will also help
reducing the impact of stm32 clock control heterogeneity in
other drivers.
Change-Id: Id15a8d0d44f03809b2907ef10d6877700459e674
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add the clock driver for the STM32L4 series.
Change-Id: Icdf79061f163d8d00187b382d1564422fb875c5b
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Based on the STM32F10x driver. Removing old code as we need to use the
bus number when dealing with 4 possible peripherals.
Change-Id: Id0263aa008e9b039ff9a00339e5622e289ffdf99
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Use SOC_SERIES_* for naming SoCs with similar features and architectures
with the goal of code reuse. The Series in the config variable should avoid
name collisions and clearly denote the relationships within an SoC family.
Change-Id: I7a98542f96b5d5dc3acc23782c4d45f98cceb599
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The patch adds a driver for STM32F10x series RCC (Reset and Clock
Control) subsystem.
The module is primarily responsible for setting up of MCU's clock
tree. In particular the driver sets up SYSCLK, PLL (with source
configuration), AHB prescaler, and APB1/APB2 prescalers. As part of this
functionality, the subsystem can enable/disable clock signal for
particular peripherals, thus reducing the power consumption of the MCU.
The driver implements clock control driver API. However, subsystem IDs
being HW specific are exposed in driver public header that must be
included by callers. The driver registers a single device using a common
name STM32_CLOCK_CONTROL_NAME. The device is initialized at
the PRIMARY level with priority 1. This allows the initialization to
take place right after SoC initialization routine.
The driver depends on selection of SOC_STM32F1X config option and is MCU
specific.
Change-Id: I8bea5db20726a24bce7b7ffe0b95de543240429a
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
