Fix definition for ROM status register for ACE1.5. The value should be
same as ACE2.0 and only different for ACE3.0.
Fixes: 6ad9b6ccab ("soc: intel_adsp: tools: add intel_adsp_ace30
support to cavstool.py")
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
SOC_FLASH_MCUX has additional dependencies for LPC55xxx CPUs, due to the
fact that the flash should be disabled when executing in nonsecure mode.
Since the merge of HWMv2, this dependency has been set incorrectly at
the SOC level, resulting in the IAP flash driver being enabled when
targeting CPU1, which is incorrect. Fix the Kconfig dependency to
resolve this issue.
Fixes#79576
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enables the XSPIM2 rail when using GPIO bank N
Enables the XSPIM1 rail when using GPIO bank O or P
Enables the USBvoltage detector when using the GPIO M
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Service for powering peripherals that use GPIO pins
in the global power domains:
- Active Fast
- Active Slow
- Main Slow
Signed-off-by: Rafal Dyla <rafal.dyla@nordicsemi.no>
Commit b73c5578e3 ("soc: ti: move init code from SYS_INIT to hooks")
changed SYS_INIT to init hooks. For AM6x M4 target soc_prep_hook()
was added by mistake instead of soc_early_init_hook(), the platform needs
RAT translation initialized before any other operation and the platform
failed to boot with this change, fix this by replacing with
soc_early_init_hook()
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Some imx8 socs have cpu cluster entries for cores that
are not currently supported. Remove them.
Fixes#79027.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
nRF54H20 EngB is a re-label to the existing hardware revision for the
nRF54H20. nRF54H20 (whithout EngX) is becoming the final revision of the
SoC.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The new GRTC reading manner of the SYSCOUNTER uses hardware mechanism which
allows to keep it alive when any of CPUs is not sleeping. Otherwise
the SYSCOUNTER goes into sleep mode. Thus there is no
longer need to maintain the `CONFIG_NRF_GRTC_SLEEP_ALLOWED` symbol, however
if the user wants to have the SYSCOUNTER enabled all the time the
`CONFIG_NRF_GRTC_ALWAYS_ON` can be used instead.
The nrfx_grtc driver no longer provides the `wakeup-read-sleep` reading
manner.
Also setting the GRTC clock source is performed by the nrfx_grtc driver so
it has been removed from the `sys_clock_driver_init()` function.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Sets CONFIG_HAS_SEGGER_RTT on the max32 soc family to allow using RTT
backends in the logging, shell, and tracing subsystems.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Asserts are by default enabled for tests but flpr and ppr are
small cores (<64k) and many tests does not fit in memory with
asserts enabled.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add debug_slot_offset_by_type() for getting debug window slot offset
by type identifier. How to find the correct slot and what types there
are is documented here:
soc/intel/intel_adsp/common/include/adsp_debug_window.h
In a normal situation a client program would try to find a specific
slot right after DSP boot. Because of that the we can not expect it to
be there immediately. Instead we need to try multiple times and give
firmware some time to update the debug slot descriptor table.
Signed-off-by: Jyri Sarha <jyri.sarha@linux.intel.com>
The fw_is_alive() depends on 'dsp' global variable which is assigned
from map_regs() return value. To make fw_is_alive() and
wait_fw_entered(), that calls fw_is_alive(), callable from another
module, the 'dsp' variable needs to be passed as an argument.
Signed-off-by: Jyri Sarha <jyri.sarha@linux.intel.com>
map_reg() depends on args global variable for knowing it should
load a new firmware or just stand by for logging or Zephyr
shell. The map_regs() code is the very first step to access the
DSP memory, it nees to be shareable if the code is to be accessed
from another python module.
Signed-off-by: Jyri Sarha <jyri.sarha@linux.intel.com>
Do not force argsparse code to all modules importing cavstool.py. The
commit moves argparse code into a separate function, and calls it from
'if __name__ == "__main__":'. Also adds the argsparse call to to
acetool.py that shares cavstool code with the argument parsing.
Signed-off-by: Jyri Sarha <jyri.sarha@linux.intel.com>
Add resource_table section in linker script for i.MX8QXP and
i.MX8QM, for inter-process communication.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Add virtual Cortex R8 SoC. This target does not represent a real SoC,
but can be easily run in Renode.
This will allow to easily test basic architecture support.
Signed-off-by: Krzysztof Sychla <ksychla@antmicro.com>
Signed-off-by: Marek Slowinski <mslowinski@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
Add support for BeaglePlay, a TI AM6254 SoC based development board with a
CC1352P7 wireless microcontroller for supporting software defined 2.4GHz
and SubGHz wireless protocols. Support for running Zephyr on the
quad-A53 SoC or the programmable M4 on the SoC would be provided
separately.
See https://beagleplay.org for details.
Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Add DT node and clocking of TPM peripherals, which are used for PWM.
Also change the soc clock enable code to not use preprocessor
conditionals.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Base enablement of MCXW merged while z_arm_platform_init was being
deprecated, resulting situation is now that no platform init is
happening, fix by converting to use soc_reset_hook.
Also fix a comment that said the core was being set to 40 MHz, when it
is actually being set up to 96 MHz.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
It is a good practice to add a comment after #endif when the condition
is not obvious. However, when the condition is well known, "Don't Repeat
Yourself" rule applies and no comment should be added.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Most of the Kconfig files in soc/silabs start with a comment describing
the chip. This comment is redundant with the help message in associated
to the chip. Let's don't repeat ourselves.
This patch also ensure the Kconfig help message the full name the chip.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Allows selecting the forward GPIO pins to network core Kconfig
option and enables it by default if the node exists in devicetree
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Add a function which can be used to remap embedded device address,
into addresses which can be used in the simulated native boards.
For the nrf_bsim boards we provide an actual implementation.
For other boards, we provide an optional dummy version which does
nothing.
It is up to each board implementation to decide if they want to
provide one or use the dummy.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Update HAL for Series 2 devices to Simplicity SDK 2024.6.
This HAL deprecates sl_device_init_emu(). Equivalent functions
are now performed by sl_power_manager_init().
For now, soc.c remains compatible with both the Gecko SDK based
HAL for Series 0 and 1, and the Simplicity SDK based HAL for
Series 2. In a future commit, soc.c will be split between the
two platforms.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
- Added `cs-supported` property to nrf-radio devicetree
- Added `HAS_HW_NRF_RADIO_CS` Kconfig option which is set if
`cs-supported` property is enabled
- Enabled `cs-supported` property for nrf54-series devices
- Disabled `cs-supported` on nrf54l15bsim because it is not
yet supported
Signed-off-by: Ivan Iushkov <ivan.iushkov@nordicsemi.no>
Add the necessary entries but keep the usbhs disabled by default on
radio core (it is enabled by default on app core).
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
- Add jlink as possible runner for cyw920829m2evk_02 platform in
board.cmake file
Signed-off-by: McAtee Maxwell (CSS ICW SW MTO INT 2) <maxwell.mcatee@infineon.com>
DBGMCU clock handling was not optimal.
If it exists, enable it before dealing with debug configuration in one
block, then deactivate it after in another block.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Similarly to debug in stop mode, enable debug in sleep mode on H7 series,
as initially described by `STM32_ENABLE_DEBUG_SLEEP_STOP` option.
Not extending it further to other series as I won't be able to test.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
# Conflicts:
# soc/st/stm32/common/soc_config.c
