Commit graph

96822 commits

Author SHA1 Message Date
Fin Maaß
1d88d7d139 soc: riscv: litex: add reboot
this makes it possible to reboot a
litex SoC.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-06-06 15:46:40 +01:00
Lorenz Clijnen
d7e5451799 modules: lvgl: input: Fix invalid encoder readout
When the encoder button was pressed, it would send a LV_KEY_LEFT/RIGHT
instead of a LV_KEY_ENTER event.
This clears the enc_diff field, and set the key field to LV_KEY_ENTER
for button events.

Fixes #73529

Signed-off-by: Lorenz Clijnen <lorenz_reclame@outlook.be>
2024-06-06 15:46:20 +01:00
Nelson Ferragut
0d56a3c3f4 doc: unittest: add instructions
Implemented suggestions from Benjamin Cabé.

Signed-off-by: Nelson Ferragut <nelson_ferragut@whirlpool.com>
2024-06-06 07:54:31 -04:00
Nelson Ferragut
7054d01dc8 doc: unittest: add instructions
Add instructions for implementing unit testing.

Signed-off-by: Nelson Ferragut <nelson_ferragut@whirlpool.com>
2024-06-06 07:54:31 -04:00
Fin Maaß
3ba44c9bdd boards: esp32: don't enable spiram for mcuboot
don't enable ESP_SPIRAM for mcuboot.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-06-06 07:53:38 -04:00
Tomasz Moń
e2afcafca5 drivers: udc_dwc2: Abort wait when PHY is not clocked
On nRF54H20DK the USB PHY is powered from VBUS. When the USB cable is
not connected, the PHY is not powered and the PHY clock disappears.

Because the GOUTNAKEFF and INEPNAKEFF can only ever be set when PHY
clock is active, the waits for these bits do timeout if cable is
disconnected. Workaround the issue by aborting the wait if vendor quirk
indicates that PHY clock has abruptly vanished.

Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
2024-06-06 07:53:17 -04:00
Tomáš Juřena
5ac6335505 drivers: pinctrl: esp32: Use BIT macro when writing pin value
GPIO registers w1ts and w1tc expects bitfield of pins to set/clean.

Signed-off-by: Tomáš Juřena <jurenatomas@gmail.com>
2024-06-06 07:52:55 -04:00
Zhengwei Wang
96ff0f1e04 drivers: timer: Optimized the ambiq stimer driver
The original driver has two defects: 1. When setting the next timeout
value the original implementation simply sets a delta value equal to
ticks * CYC_PER_TICK. This operation is reckless and may incorrectly
"reset" the fractional tick, causing clock skew. 2. The original
implementation doesn't handle the counter overflow situation. When the
counter overflows from 0xffffffff to 0x0, the uptimer counter becomes
incorrect. We have fixed above issue by rewriting most of the functions in
this driver and verified it by running all tests under
tests/kernel/timer folder.

Signed-off-by: Zhengwei Wang <zwang@ambiq.com>
2024-06-06 07:52:32 -04:00
Benjamin Cabé
d8b4ff5531 samples: drivers: clock_control_litex: clean up DTS snippet in README
Clean up the DTS snippet in the README file to make it more readable.

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
2024-06-06 07:51:58 -04:00
Andrej Butok
5df6aa8efa boards: nxp: mimxrt11xx: fix non-optimal sector distribution
- Optimize slot sizes for MCUBoot swap move algorithm
  for mimxrt1160/70 boards.
- Use DT_SIZE_K/M macros for slot sizes.
- Limit mcuboot max size to 128KB.

Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
2024-06-06 07:51:38 -04:00
Declan Snyder
a42ada8426 drivers: nxp_enet: Disable hw accel with IPV6
As far as I can tell it appears that the hardware
does not support acceleration of ICMPV6 checksums.
For now, the easiest way to fix the runtime failure of
IPV6 is just to disable the hardware acceleration if
IPV6 is expected to be used.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-06-06 07:51:16 -04:00
Henrik Brix Andersen
331b404185 twister: hardwaremap: avoid exceptions when generating hardware map
Avoid exceptions when generating persistent hardware maps on Linux with no
devices available.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2024-06-06 07:50:51 -04:00
Anas Nashif
94b9790941 ci: test_plan: fix handling of v2 boards
Handling of board changes was broken and did not support v2 boards, fix
this to optimize CI execution on localized changes of board files.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-06-06 07:50:34 -04:00
Fabio Baltieri
19bf8c3631 MAINTAINERS: add the test path to the sensing area
Make sure sensing test changes are assigned.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2024-06-06 04:44:49 -07:00
Fabio Baltieri
92c459a9bc tests: subsys: sensing: set CONFIG_EMUL=y
The test is broken in CI because the emulated spi bus is not built in,
adding an explicit CONFIG_EMUL=y to the test config.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2024-06-06 04:44:49 -07:00
Grzegorz Swiderski
1f05b22acb boards: nordic: nrf54h20dk: Add aliases for RESETINFO
Each local RESETINFO instance can be used in samples.

Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
2024-06-06 10:03:15 +02:00
Grzegorz Swiderski
742c728c7e dts: nordic: Add RESETINFO
Add devicetree nodes for the Reset Information registers on nRF54H20,
along with a new binding.

Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
2024-06-06 10:03:15 +02:00
Sebastian Bøe
e1347ded48 soc: nordic: nrf53: Remove broken PM_S2RAM support
Remove dead code that cannot be enabled.

Kconfig prevents us from enabling PM_S2RAM on 53 because it is not
supported any more.

But we still have some dead code left over in soc.c, so we delete this
code.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2024-06-06 10:02:58 +02:00
Tom Burdick
c5e591bf44 sys: MPSC doc comment cleanup
The doc comment relating to mpsc atomics was worded poorly. Remove
the poorly worded doc comment related to atomics and caches.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2024-06-06 00:42:29 -07:00
Tom Burdick
d95caa51a4 sys: Add a lockfree mpsc and spsc queues
Moves the rtio_ prefixed lockfree queues to sys alongside existing
mpsc/spsc pbuf, ringbuf, and similar queue-like data structures.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2024-06-06 00:42:29 -07:00
Tom Burdick
f32a41d4dd rtio: Exclude platforms from CI testing
Running lock free algorithms on renode seem to cause timeouts so exclude
renode platforms.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2024-06-06 00:42:29 -07:00
Sreeram Tatapudi
69f9d73197 boards: infineon: cyw920829m2evk_02: Fix index.rst
Update index.rst to use the right description for code

Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
2024-06-06 09:42:20 +02:00
Sreeram Tatapudi
0b599c6600 tests: drivers: Enable driver tests for cyw20829
Add overlays to enable GPIO and I2C driver tests

Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
2024-06-06 09:42:20 +02:00
Sreeram Tatapudi
0f2aead57d driver: watchdog: infineon: cyw20829 watchdog
- Enable watchdog for the cyw920829m2evk_02 board

Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
2024-06-06 09:42:20 +02:00
Grzegorz Swiderski
46572f797f dtlib: Allow deleting the root node
Previously, dtlib would fail to parse the following:

   /delete-node/ &{/};

This is accepted by dtc, so dtlib should be aligned.

The expected behavior is that the contents of the "deleted" root node
are emptied, but the node itself remains in the tree. This means that
it's possible to put that statement at the end of a DTS file and still
get a valid output. A small test case for this scenario is included.

Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
2024-06-06 00:42:10 -07:00
Qianru Huang
a736f150f7 tests: subsys: sensing: add sensing test skeleton
Add the test cases for Sensing(Sensing Subsystem) to verify the
functionality of sensing portion of subsystem.
The test cases are based on native_sim platform.

Signed-off-by: Qianru Huang <qianru.huang@intel.com>
2024-06-06 00:42:04 -07:00
Francois Ramu
8cd4d8aa7e boards: arm: stm32h7s78 disco kit
Introduce the stm32h7s78_dk disco kit from STMicroelectronics
Based on the stm32H7S7 mcu
Use STM32CubeProgrammer v2.16.0 as runner.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2024-06-06 00:41:43 -07:00
Francois Ramu
bde663f484 drivers: gpio: stm32 gpio driver supporting the stm32H7RS
Introduce the stm32h7RS serie to the gpio driver,
based on the stm32h7
The SBS controller is used to configure the EXTI line among
the different GPIO port.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2024-06-06 00:41:43 -07:00
Francois Ramu
c0750e9867 drivers: pinctrl: stm32 pinctrl driver supporting the stm32H7RS
Introduce the stm32h7RS serie to the pin control driver,
New GPIO port M, N, O, P
Then add the complete list and from A to P (16 port
coded on 5 bits)

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2024-06-06 00:41:43 -07:00
Francois Ramu
e6ebb044ac drivers: clock: stm32 clock driver supporting the stm32H7RS
Introduce the stm32h7RS serie to the clock_controller,
based on the stm32h7 clock driver
Datasheet DS14359 rev 1 gives CPU max freq of 500MHz

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2024-06-06 00:41:43 -07:00
Francois Ramu
332eb17995 dts: arm: stm32h7 introduce stm32h7R/h7S devices
Add the new stm32h7rs serie with stm32H7R3, stm32H7R7,
stm32H7S3, stm32H7S7 devices from STMicroelectronics

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2024-06-06 00:41:43 -07:00
Francois Ramu
715b246a2a include: reset bindings add the stm32h7rs serie
Add the support of the STM32H7RSX to the
include/zephyr/dt-bindings/reset/stm32h7_reset.h
which differs from the stm32h7 with an APB5 bus

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2024-06-06 00:41:43 -07:00
Francois Ramu
c08f27d84d dts: bindings: stm32 rcc and exti controller for the stm32H7RS
Introduce the stm32h7RS serie to the clock rcc controller,
and the exti interrupt controller based on the stm32h7 rcc bindings.
Three PLL clocks are available.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2024-06-06 00:41:43 -07:00
Francois Ramu
f909c4aee2 soc: st: stm32 common soc config introduce stm32h7R/h7S devices
Add the new STM32HRSX serie from STMicroelectronics

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2024-06-06 00:41:43 -07:00
Francois Ramu
4f995bd0ff soc: arm: stm32h7RS introduce stm32h7R/h7S devices
Add the new STM32HRSX serie with stm32H7R3, stm32H7R7,
stm32H7S3, stm32H7S7 devices from STMicroelectronics
Same MPU regions as stm32h7 device.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2024-06-06 00:41:43 -07:00
Tim Lin
76ced4a82d drivers: pinctrl: ITE: Add a property configure pin current strength
Add the property of drive-strength to drive a high or low current
selection. If this property is not configured, it is the default
setting. According to the SPEC, the default drive current selection
varies from different pins.
Define the high level 0b: 8mA
           low  level 1b: 4mA or 2mA

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2024-06-06 00:41:35 -07:00
Peter van der Perk
388ca7febd vmu_rt1170: update docs
Add QTMR and FlexTimer peripherals, update pinmuxing

Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
2024-06-06 09:41:22 +02:00
Peter van der Perk
0eee622621 boards: nxp: vmu_rt1170: Add Buzzer and QTMR entries
Allows to control buzzer with QTMR PWM

Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
2024-06-06 09:41:22 +02:00
Peter van der Perk
49e7944d59 soc: nxp: rt11xx: Enable NXP QTMR
Adds QTMR dts entries

Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
2024-06-06 09:41:22 +02:00
Peter van der Perk
af52f1b290 clock: mcux_ccm: add qtmr clock
Add defines for QTMR peripheral

Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
2024-06-06 09:41:22 +02:00
Peter van der Perk
9addbe77fc drivers: pwm: pwm_mcux_qtmr: Add QTMR driver.
PWM driver for QTMR peripheral

Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
2024-06-06 09:41:22 +02:00
Daniel DeGrasse
c77b956de5 soc: nxp: imxrt11xx: support configuration of ARM PLL
Add support for configuration of the ARM PLL on the iMXRT1170/1160
series SOCs. This PLL is used to generate the M7 core frequency, and is
an integer pll. Provide default configurations for the RT1160 and RT1170
targeting 600MHz and 1GHz respectively.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2024-06-06 00:41:17 -07:00
Daniel DeGrasse
026d0507ea boards: shields: adafruit_2_8_tft_touch_v2: fix RW612 board overlay
RW612 board overlay should remove the MIPI DBI nodes defined at the
board and at the shield level, because the LCDIC peripheral on this SOC
can support the MIPI DBI protocol directly without the emulated Zephyr
driver.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2024-06-06 00:41:11 -07:00
Pekka Niskanen
6844016d9d doc: update Infocenter links to TechDocs links
As the Infocenter will soon be taken offline, updating
links to point to TechDocs.

Signed-off-by: Pekka Niskanen <pekka.niskanen@nordicsemi.no>
2024-06-06 00:41:04 -07:00
Jeppe Odgaard
1635ad5a4d dts: boards: stm32h562: add timers 15, 16 and 17
Add the remaining timer nodes for stm32h562.

Tested with a Logic Analyzer and `samples/drivers/led_pwm` with added
`nucleo_h563zi.overlay`:

```

&timers15 {
	status = "okay";
	st,prescaler = <1000>;

	pwm15: pwm {
		status = "okay";
		pinctrl-0 = <&tim15_ch2_pa3 /* CN10.34 */>;
		pinctrl-names = "default";
	};
};

&timers16 {
	status = "okay";
	st,prescaler = <1000>;

	pwm16: pwm {
		status = "okay";
		pinctrl-0 = <&tim16_ch1n_pb6 /* CN10.14 */>;
		pinctrl-names = "default";
	};
};

&timers17 {
	st,prescaler = <1000>;
	status = "okay";

	pwm17: pwm {
		status = "okay";
		pinctrl-0 = <&tim17_ch1n_pb7 /* CN10.16 */>;
		pinctrl-names = "default";
	};
};

&pwmleds {
	status = "okay";

	pwm_led_1: green_led_1 {
		pwms = <&pwm15 2 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
		label = "green led";
	};

	pwm_led_2: red_led_1 {
		pwms = <&pwm16 1 PWM_MSEC(20)
		        (PWM_POLARITY_NORMAL | STM32_PWM_COMPLEMENTARY)>;
		label = "red led";
	};

	pwm_led_3: blue_led_1 {
		pwms = <&pwm17 1 PWM_MSEC(20)
		        (PWM_POLARITY_NORMAL | STM32_PWM_COMPLEMENTARY)>;
		label = "blue led";
	};
};
```

Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
2024-06-06 00:40:59 -07:00
Balaji Srinivasan
16fc8f5295 task_wdt: Feed hardware watchdog only when its started
Previously the schedule_next_timeout() function was feeding the hardware
watchdog irrespective of whether or not it was started. This is now
fixed.

Signed-off-by: Balaji Srinivasan <balaji.srinivasan@nordicsemi.no>
2024-06-06 00:40:53 -07:00
Henrik Brix Andersen
633065ec3b drivers: can: mcux: flexcan: calculate and set proper TDCO
Calculate and set a proper Transceiver Delay Compensation Offset (TDCO)
based on FlexCAN FD timing.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2024-06-06 00:40:45 -07:00
Daniel DeGrasse
7b207e309f samples: add testcases for rk043fn02h_ct and rk043fn66hs_ctg shields
Add testcases for rk043fn02h_ct and rk043fn66hs_ctg shields to display
and LVGL samples, so these testcases will be built by CI.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2024-06-06 09:37:16 +02:00
Daniel DeGrasse
6c95c82604 boards: nxp: mimxrt1060_evk: remove display definition
Remove display definition for the RT1060 EVK. This display panel is now
supported as the RK043FN02H-CT shield. Add this information to the
documentation for the board, along with other tested shields.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2024-06-06 09:37:16 +02:00
Daniel DeGrasse
7d441d5c81 boards: shields: rk043fn66hs_ctg: add shield for rk043fn66hs_ctg
Add a shield for the RK043FN66HS-CTG panel, a Rocktech display panel with
an GT911 touch controller. This panel uses a 40+6 FPC interface for
parallel displays, which is supported by many NXP iMX RT EVKs.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2024-06-06 09:37:16 +02:00