In the IT82xx2 chip, the ready bit is automatically cleared by
hardware. When setting other bits, there is a chance that the ready bit
hasn't been cleared yet, leading to unexpected USB transactions. This
change ensures that the ready bit is always set to '0' when setting the
endpoint control value.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
According to the Zephyr documentation, the number of bytes available
for read should be returned if the input data and length parameters are
NULL and zero, respectively. This commit corrects this behavior.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Since the fifo control register and ready bit are checked in ISR
function, this commit locks IRQ when accessing these registers to
prevent racing conditions.
Tested with: Google spikyrock project
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
This commit addresses some issues during the extended endpoint(ep
number is larger than 4) access. There are enable and ready bits for
each endpoint on the IT82xx2 chip. The transaction completion should be
determined by the ready and enable bits of the corresponding endpoint.
Additioinally, for non-control endpoint, the FIFO control register is
selected before writing data and cleared when the IN transaction is
completed. When an IN token interrupts, the FIFO control register
should be checked if it's selected to prevent fake tokens.
Tested with: Google spikyrock project
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
There is default 15K-ohm pull-down for USB controller.
To disable the default pull-down to avoid signal contention in GPIO mode.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
There are some issues with the extended endpoint settings. The incorrect
setting leads to the chip being unable to respond with NAK when the host
polls the extended endpoint for data transfers. Additionally, the controls
for the extended endpoint's ISO and PID data sequence are also incorrect.
This commit addresses these issues to properly support extended endpoint
transactions.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
There are two registers that control the selection of one FIFO as data
buffer for 15 endpoints (ep1-ep15). Both registers should be configured
before sending and receiving data. Additionally, there was an issue with
the corresponding FIFO index setting in the 'usb_dc_ep_read_continue'
function, which has been addressed in this commit.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
ep_ctrl and ep_trans_type is not used inside it82xx2_usb_dc_isr, this
triggers a compile warning. Move these variables to a smaller scope.
Signed-off-by: Ting Shen <phoenixshen@google.com>
Fix few instances of delayable work handlers using the k_work pointer
directly in a CONTAINER_OF pointing to a k_work_delayable.
This is harmless since the k_work is the first element in
k_work_delayable, but using k_work_delayable_from_work is the right way
of handling it.
Change a couple of explicit CONTAINER_OF doing the same work as the
macro in the process.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This change corrects the it82xx2 resumed/suspended mechanism and power
policy flow. The sof package is used to judge if the device can be set as
suspended state. If there is no sof package received(suspended), the chip
power policy is set as standby(deep doze) mode. Meanwhile, the USB D+
interrupt is enabled. The interrupt is triggered at resume signal(from J
to K state). Chip sets its power state as active(doze) mode and disable
the interrupt.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
