Add a support for TI MSPM0 Timer which has sub module for Counter,
Timer Capture and Timer Compare.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
TI MSPM0 SoC series has General Purpose Timer and Advanced control timers
with Counting module, Capture block (measure input signal period/time) and
Compare block (to generate time expiry, output waveform like PWM).
Add a support for counter driver with alarm and counter top functions.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
IDLEOUT presence in PWM means that there are 3 sources from which
PWM pin can be driven:
- GPIO setting when PWM peripheral is disabled.
- IDLEOUT setting when PWM is enabled.
- PWM Sequence when it is in use.
IDLEOUT setting cannot be changed after enabling PWM so it is
configured to the initial state of the pin. It means that if duty
cycle is 100%, GPIO output is set to 1 but initial pin state was 0
(IDLEOUT setting) there will be a glitch between disabling a PWM
sequence and disabling a PWM peripheral.
By default, PWM driver tries to disable PWM peripheral if all channels
are 0% or 100% duty cycle to safe power. When IDLEOUT feature is
present there will be a short glitch on channels with 100% duty cycle.
In order to avoid that CONFIG_PWM_NRFX_NO_GLITCH_DUTY_100 option is
added (enabled by default). When option is enabled 100% duty cycle
is achieved by PWM sequence and not by driving a GPIO pin. It will
consume more power in cases where all channels are 0% or 100% with
at least one channel set to 100% duty cycle.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add property which indicates that PWM instance supports IDLEOUT
feature. Add property to all instances that supports it.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The test which measures and validates transfer times is using the
helper spi_loopback_transceive() to perform the transfer. This
helper internally gets the spi controller, which is useful for
most tests, but for this one, it means the time to get and put
the spi controller is included in the transfer time measurement.
This commit gets the spi controller before calling
spi_loopback_transceive() which results in only the actual
transfer time being measured.
Before this commit, on the nrf54h20:
START - test_spi_complete_multiple_timed
Transfer took 745 us vs theoretical minimum 108 us
Latency measurement: 637 us
PASS - test_spi_complete_multiple_timed in 0.008 seconds
START - test_spi_complete_multiple_timed
Transfer took 700 us vs theoretical minimum 54 us
Latency measurement: 646 us
Assertion failed at ...
Very high latency
FAIL - test_spi_complete_multiple_timed in 0.027 seconds
After this commit:
START - test_spi_complete_multiple_timed
Transfer took 250 us vs theoretical minimum 108 us
Latency measurement: 142 us
PASS - test_spi_complete_multiple_timed in 0.008 seconds
START - test_spi_complete_multiple_timed
Transfer took 204 us vs theoretical minimum 54 us
Latency measurement: 150 us
PASS - test_spi_complete_multiple_timed in 0.008 seconds
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The spi_loopback test suite creates three internal threads. The
stack sizes for these threads is hardcoded to 512, which is to little
for some socs, namely the nrf54h20 cpuapp if pm device runtime is
enabled. Instead, determine the stack sizes the same way ztest
stack sizes are determined.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Statuses of quarantined test cases were not updated properly.
Quarantined tests shouldn't cause errors in integration mode.
Removed obsolate filter type.
Signed-off-by: Maciej Perkowski <maciej.perkowski@nordicsemi.no>
Enable the standby power state by default for the rd_rw612_bga and
frdm_rw612 boards in the peripheral_ht and central_ht Bluetooth samples.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Enable node drbg0 in the google_quincy device tree. This node is
required to enable the entropy upstream test.
Signed-off-by: Firas Sammoura <fsammoura@google.com>
The temperature calibration addresses of ts-cal1-addr and ts-cal2-addr
are not shared between stm32wba5 and stm32wba6 these addresses are now
separated to the dedicated device-tree
Signed-off-by: Romain Jayles <romain.jayles@st.com>
NATIVE_APPLICATION is now deprecated so nobody will set it,
but NATIVE_BUILD should cover the same case this build error
is trying to warn about. Let's use it instead.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
NATIVE_APPLICATION is deprecated, let's not use it, let's use instead
NATIVE_BUILD.
unit_testing is not really meant to be covered by NATIVE_APPLICATION,
or NATIVE_BUILD for that matter, as these options are meant for POSIX
arch based targets.
Still, some kconfig options will default to something which will
also be incompatible with unit_testing (primarily CONFIG_PICOLIBC=y)
if we don't set at least NATIVE_BUILD, which would cause some unit
tests to fail. So let's select NATIVE_BUILD to avoid needing to add
extra dependencies on the libCs options.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
There is a potential issue that the index of ACL may out of the
bounds of the array `bt_hfp_hf_pool` if the array size is not aligned
with the array size of `acl_conns`.
To avoid the potential issue, check if the ACL conn index is less than
the array size of `bt_hfp_hf_pool` before accessing the array
`bt_hfp_hf_pool` with ACL conn index.
Fixes#91172
Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
New versions of the Wiseconnect HAL require a clock manager init
function to be called as part of clock configuration.
Without this, the default reference clock isn't configured correctly
for use with peripherals.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
When there are br connections connected, find_key_in_use call
bt_conn_get_dst to get br connection's dst and bt_conn_get_dst return NULL,
then bt_keys_find_addr aseert because addr is NULL.
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
Currently, every boards that implement a memory controller add an entry
in tests/drivers/memc/ram/testcase.yaml. However, the configuration is
exactly the same for all the boards. So, we can just consider that any
board that declare "memc" capability has to be tested.
For the record here are the boards that has the memc capability:
adi/apard32690/apard32690_max32690_m4.yaml
adi/eval_adin1110ebz/adi_eval_adin1110ebz.yaml
adi/max32690evkit/max32690evkit_max32690_m4.yaml
arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.yaml
arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_1_0_0.yaml
arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_4_10_0.yaml
atmel/sam/sam4s_xplained/sam4s_xplained.yaml
renesas/da1469x_dk_pro/da1469x_dk_pro.yaml
sifive/hifive_unmatched/hifive_unmatched_s7.yaml
sifive/hifive_unmatched/hifive_unmatched_u74.yaml
silabs/radio_boards/siwx917_rb4342a/siwx917_rb4342a.yaml
st/stm32f746g_disco/stm32f746g_disco.yaml
st/stm32f7508_dk/stm32f7508_dk.yaml
st/stm32f769i_disco/stm32f769i_disco.yaml
st/stm32h735g_disco/stm32h735g_disco.yaml
st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.yaml
st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.yaml
st/stm32h750b_dk/stm32h750b_dk.yaml
st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m7.yaml
st/stm32h7b3i_dk/stm32h7b3i_dk.yaml
st/stm32h7s78_dk/stm32h7s78_dk.yaml
st/stm32n6570_dk/twister.yaml
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
When support for SPDX 2.3 was added, it effectively dropped support for
SPDX 2.2, which in retrospect was a bad idea since SPDX 2.2 is the
version that is the current ISO/IEC standard.
This commit adds a `--spdx-version` option to the `west spdx` command
so that users can generate SPDX 2.2 documents if they want.
Default is 2.3 given that's effectively what shipped for a few releases
now, including latest LTS.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
This adds support for BTP commands and events required for running
PAST tests.
struct btp_gap_ev_periodic_transfer_received_ev is also adjusted
to match BTP specification.
Signed-off-by: Szymon Janc <szymon.janc@codecoup.pl>
- Remove memset on bt_l2cap_br_chan during SDP
disconnect to prevent overwriting resources
(e.g., rtx_work) still in use by L2CAP,
which handles channel cleanup itself.
- Delete unused partial_resp_queue to clean up code.
Signed-off-by: ZhongYao Luo <LuoZhongYao@gmail.com>
If the received data length is less than 2 in none basic mode, the
L2CAP channel connection will be dropped.
Only check the received data length if the `SAR` is
`BT_L2CAP_CONTROL_SAR_START`.
Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
Support zero-length SDU sending if the L2CAP channel connection is not
in basic mode.
Flag the zero-length SDU buffer and clear it if it has been processed.
Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
The MIMXRT1170-EVK/EVKB has an Arduino compatible header, add device
tree nodes for the corresponding pins.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Allow to add an image-specific DTS overlay, that is applied based on the
FILE_SUFFIX.
Up to this point, it was possible to specify such Kconfig files
(sysbuild/<image>_<file_suffix>.conf),
but it did not work with dts overlays
(sysbuild/<image>_<file_suffix>.overlay).
This commit aligns the logic of finding configuration files for both
scenarios mentioned above.
Ref: NCSDK-NONE
Signed-off-by: Tomasz Chyrowicz <tomasz.chyrowicz@nordicsemi.no>
Follow-up to PR #88631: fix missing variable declarations introduced in
the STM32 I2C LL driver after adding timeouts to blocking loops.
The missing declarations caused a build failure when interrupts were
disabled (CONFIG_I2C_STM32_INTERRUPT=n).
Fixes a regression introduced in #88631.
Signed-off-by: Jean Nanchen <jean.nanchen@gmail.com>
Add options to area command:
--without-maintainers
--without-collaborators
To show areas without any collaborators or maintainers.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The uart_busy_set and uart_busy_clear are only used when runtime
pm is not enabled. So add #ifndef CONFIG_PM_DEVICE_RUNTIME to
enclose these two functions.
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
AS6212 supports 0.25Hz, 1Hz, 4Hz, and 8Hz sampling frequencies, but the
current driver supports 0.25Hz, 1Hz, 4Hz, and 16Hz sampling frequencies.
Signed-off-by: Clément Laigle <c.laigle@catie.fr>
There was a missing irq-gpios property that cause
building failure on lvgl and display samples.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
On dual-core STM32H7, the Cortex-M4 core is supposed to wait until the
Cortex-M7 initializes the system before starting to execute. CM7 should
signal this by locking a specific HSEM, which CM4 should poll until locked.
However, the logic on the Cortex-M4 side was reading the "RLR" register of
HSEM, which *locks the semaphore on read* - in turn, this makes the CM4
start directly since it sees that the semaphore is locked (by itself).
Use proper LL API to read HSEM status - which will read the "R" register
instead - to make sure CM4 doesn't begin execution earlier than it should.
Suggested-by: hglassdyb
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
The fifth HSEM (#define is equal to 4 due to zero-indexing) is used on
STM32H7 to synchronize the two cores. Update the comment above the SEMID
define to reflect this alternate usage. Also remove the associated define
CFG_HW_ENTRY_STOP_MODE_MASK_SEMID, which is unused.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Reorder the HSEM semaphore ID definitions to be sorted by ascending value.
The dummy defines are also changed to be sorted in the same order. The
definitions for STM32MP1 are already in an order that follows this order
so they don't need to be changed.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Add support to use DMA mode with cc23x0 UART module. This consists in
specifying the DMA channels and peripherals.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Two DMA channels are assigned to TX and RX respectively:
- A TX DMA request is asserted when there is space in the FIFO.
- A RX DMA request is asserted when data is in the FIFO.
When DMA is enabled for a peripheral, the DMA transfer completion is
signaled on the peripheral's interrupt only (here UART's interrupt).
It is not signaled on the DMA dedicated interrupt.
Also, when DMA is enabled for a peripheral, the DMA controller stops
the normal transfer interrupts for this peripheral from reaching the
NVIC (the interrupts are still reported in the interrupt registers of
the peripheral). Thus, when a large amount of data is transferred using
DMA, instead of receiving multiple interrupts from the peripheral as
data flows, the NVIC receives only one interrupt when the transfer
completes (unmasked peripheral error interrupts continue to be sent
to the NVIC).
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Add support to use DMA mode with cc23x0 ADC module. This consists in
specifying the DMA channel and peripheral.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
The ADC has a dedicated interface for communicating with the DMA.
The ADC module provides four interrupt sources (one for each
conversion result storage register) which can be configured to
source the DMA trigger.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
