Commit graph

12 commits

Author SHA1 Message Date
Tomasz Bursztyka
04f5cfb889 wdt: dw: Add support for optional clock gating
Clock gating is platform specific and not mandatory. Thus making it
Kconfig based as well as generic.

Change-Id: I4ea10eadb077ac3d57c9337b43b1a9fb14763302
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:58 -05:00
Tomasz Bursztyka
61c15ba1e1 rtc: dw: Add support for optional clock gating
Clock gating is platform specific and not mandatory. Thus making in
Kconfig based as well as generic.

Change-Id: I01b7831536efd87cc66a95060fcf1faf4a340073
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:58 -05:00
Tomasz Bursztyka
66f05ce4b3 rtc: dw: Make internal primitives Kconfig based
Base address, IRQ, interrupt priority as well as the instance name: all
are now Kconfig based. Thus Applying the change to quark_se and
quark_d2000 platforms. Sample code is updated as well.

Change-Id: I1c225c1b68d94b22ca10423b50a78a0ba09a27a5
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:58 -05:00
Tomasz Bursztyka
85b49efe67 watchdog: dw: Make internal primitives Kconfig based
Base address, IRQ, interrupt priority as well as the instance name: all
are now Kconfig based. Thus Applying the change to quark_se and
quark_d2000 platforms. Sample code is updated as well.

Change-Id: Idcc89e6e9f4acc337fafc7d42f8de3061a5ece04
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:58 -05:00
Anas Nashif
036f793544 quark_se: change interrupt values for UART
The values for this platform were wrong.

Change-Id: Iaa24ae05b29b7af26437f0be8fe88e6eab12469d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:57 -05:00
Daniel Leung
5cdd4584fe uart_pipe: use device name instead of index
Use device name to find the UART device for uart_pipe usage,
instead of relying on an arbitrary index.

Change-Id: I36aaa4ed8f0b4905e4e741ca1464947e59f30869
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:56 -05:00
Daniel Leung
1720991b81 bluetooth/uart: use device name instead of index
Use device name to find the UART device for Bluetooth usage,
instead of relying on an arbitrary index.

The default device names being used are derived from the original
board.h for each platform. Some of them point to the same device
as UART console. Since this is a Kconfig option, the default
can be overridden so this is not a serious issue.

Change-Id: Ibe82f3968e72ba60f9c033aa3dfcb2fb3c41dc75
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:56 -05:00
Daniel Leung
08b4fd431b console/uart: use device name instead of index
Use device name to find the UART device for console usage, instead of
relying on an arbitrary index.

Change-Id: Iebe01c9bf392dfee6d8284367f67647f7d47561a
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:56 -05:00
Daniel Leung
728d91d598 serial/ns16550: refactor (again) to conform to driver model
() Renames ns16550.c to uart_ns16550.c. This is to follow
   the driver naming convention.
() Renames functions ns16550_uart_*() to uart_ns16550_*(),
   following driver naming convention.
() UART ports initialization is moved into the driver itself.
   All the init code in platform config files is removed.
() Adds (many) Kconfig options. These don't have to be defined
   in each platform's board.h anymore.
() Renames CONFIG_NS16550_* to CONFIG_UART_NS16550_*
() Disable NS16550 for ARC as no port is defined anyway.

Change-Id: I76bbe25b9bc75eb62df81e533f84f4f63a5257b7
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:56 -05:00
Tomasz Bursztyka
8e4aff1079 gpio: dw: Support optional clock gating
This is currently valid for quark_se platform. It's used internally to
suspend and/or resume the gpio controller.

Change-Id: I5147568ba6b0450363566b5f9fd2e8aa7e41df49
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:55 -05:00
Tomasz Bursztyka
6351d6671d quark_se: Exposing only one gpio controller and fixing his bits
There is no secondary GPIO controller on such SoC. Plus, the unique
controller controls at least 28 pins (if not 32, so I set 32), as
verified on boards.

Change-Id: I61c563671a908551250faa2a0fb9f9e2e17018d3
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:55 -05:00
Anas Nashif
5115fb57ad quark_se: rename platform and remove x86 suffix
Change-Id: I19ac3a4c6081720736c6fbf16b649ccf6ae60e2f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:54 -05:00
Renamed from arch/x86/platforms/quark_se-x86/Kconfig (Browse further)