* Add support for running interoperability tests with
Qemu X86.
* Remove some debugging messages to allow binary to
fix Qemu Cortex-M3 board.
* Tune buffer and stack sizes to fit all boards.
Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
Some chips, that use Cortex-M SysTick as the system timer, disable a
clock in a low power mode, that is the input for the SysTick e.g.
STM32Fx family.
It blocks enabling power management for these chips. The wake-up
function doesn't work and the time measurement is lost.
Add an additional IDLE timer that handles these functionality when the
system is about to enter IDLE. It has to wake up the chip and update the
cycle counter by time not measured by the SysTick. The IDLE timer has to
support counter API (setting alarm and reading current value).
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
This commit enables clock control instances for apollo4p_blue_kxr_evb.
Also adds pin configuration for each instance.
Signed-off-by: Aaron Ye <aye@ambiq.com>
The picolibc module can be built without thread local storage support if
desired. Allow that by using 'imply' instead of 'select'. However, when
using the toolchain picolibc, we assume that TLS will be enabled wherever
supported, so make sure we match by adding a 'select' for this case.
Signed-off-by: Keith Packard <keithp@keithp.com>
Fix SYS_MEM_BLOCKS_DEFINE_STATIC() description.
Use a "memory blocks allocator" instead of "slab",
which is most probably was copy-pasted from
the previous "slab" chapter by mistake.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics.
Note that for some peripheral instances is needed to define the
HAL macros of the peripheral base address because there are gaps
in the instances or there are SoCs with a single instance.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Add test to verify SDIO subsystem. Note that due to the nature of SDIO
cards, this test only reads from common registers and does not verify
extended reads or writes.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add test for card insertion interrupt to SDHC test.
The test will now wait for the card insertion interrupt whenever it is
run without a card in the slot. By inserting a card, the user can verify
that card insertion interrupts work correctly, as this should notify the
test and allow it to proceed.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
add support for card interrupt sources to SDHC drivers. This can be used
for SDIO card interrupts, or to detect card insertion/removal.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Extends the concept of halting a thread from just aborting a thread
to both aborting and suspending a thread.
Part of this involves updating k_thread_suspend() to operate in a
similar fashion to that of k_thread_abort().
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Extracts the essential thread synchronization logic when aborting
a thread from z_thread_abort() and moves it to its own routine
called z_thread_halt().
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
The routine halt_thread() acts nearly identical to end_thread()
except that instead of only halting the thread if the _THREAD_DEAD
state bit is not set, it will halt it if bit specified by the
parameter new_state is not set (which is always _THREAD_DEAD).
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
The halt queue will be used to identify threads that are waiting
for a thread on another CPU to finish suspending.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Make sure application-kconfig.include is properly highlighted by setting
the :language: attribute.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Several paths are checked for existence before added as global Zephyr
include path.
The existence check was needed because some tooling emit warnings on
non-existing paths.
Only few SoCs are using those pre-defined paths, yet this code runs
for all SoCs. The principle originates back from Kbuild days, and with
CMake it's more common and generally more visible to let the CMake code
defining libraries to specify include paths.
Furthermore it appears that several SoC implementation following the
<soc-path>/include was unaware that the path would be automatically
added as include path, cause they contain lines like:
zephyr_library_include_directories(include)
Remove pre-defineds path except the `<SOC_PATH>` path, which is
guaranteed to exists.
This simplifies the CMake logic in the top-level Zephyr CMakeLists.txt
file.
This cleanup further prepares for future work where SoCs need not to
be organised under architectures which is important for multi-arch SoCs.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Fixes compile warning:
drivers/eeprom/eeprom_emulator.c:645:13:
warning: 'rc' may be used uninitialized [-Wmaybe-uninitialized]
645 | int rc;
Signed-off-by: Nick Ward <nix.ward@gmail.com>
If the interface is WiFi one, then print information about it.
Also the device information is useful to know so print device
name corresponding to the network interface.
Signed-off-by: Jukka Rissanen <jukka.rissanen@nordicsemi.no>
Fix settings for TEAR and DPHYCMD0 to match initialization data
provided by MCUX SDK driver. The following fixes were needed:
- Tear effect signal should only be sent at the VBLANK interval, so TEON
should be set to 0x0
- DPHYCMD0 LP-RX VHYS trimming was incorrectly being set to 37mV, when
it should be set to 66mV (the default value)
These changes resolve some flickering and blooming that occasionally
occurred during initialization
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Fix the following compilation warning:
```
Warning (unit_address_format): /memory@0xb0000000: \
unit name should not have leading "0x"
```
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
This commit names a couple of choices to allow the default
value to be overridden by Kconfig files out of tree
Signed-off-by: Emil Lindqvist <emil@lindq.gr>
This commit introduces SMP support into Cortex-A/R aarch32 architecture.
For now, this only supports multiple core start together and only allow
one CPU initialize system as primary core, others loop at the beginning
as the secondary cores and wait for wake up.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
This commit introduce 'USE_SWITCH' feature into cortex-A/R(aarch32)
architecture
For introducing USE_SWITCH, the exception entry and exit are unified via
`z_arm_cortex_ar_enter_exc` and `z_arm_cortex_ar_exit_exc`. All
exceptions including ISR are using this way to enter and exit exception
handler.
Differentiate exception depth and interrupt depth. Allow doing
context switch when exception depth greater than 1 but not allow doing
this when interrupt depth greater than 1.
Currently, USE_SWITCH doesn't support FPU_SHARING and USERSPACE.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
Store the current CPU's struct _cpu instance into TPIDRURO, so that the
CPU core can get its struct _cpu instance by reading TPIDRURO. This is
useful in the SMP system.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
Replace the TLS base address pointer from TPIDRURO to TPIDRURW.
The difference between them is that TPIDRURO is read-only in user mode
but TPIDRURW isn't. So TPIDRURO is much more suitable for store
the address of _kernel.CPU[n]. For this reason, this commit replaces
the base pointer of the TLS area.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
MMU or MPU unit need to be initialized by its own CPU.
- Primary core initialize MMU or MPU unit in z_arm_prep_c.
- Secondary core initialize MMU or MPU unit in z_arm_secondary_start.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
Since the accelerometer's HM (high-performance mode) bit is forced to 1,
the 1.6Hz frequency is available by setting the ODR to 11.
1.6Hz is a low-power mode that conserves energy and is suitable for
some applications, such as determining the orientation (portrait or
landscape) of a device.
Signed-off-by: Samuel Tardieu <sam@rfc1149.net>
Build errors where introduced by
c76d5b882c and are fixed with this
commit. They are trivial fixes of malformed lines.
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
Add an initial test based on the broadcast audio source/sink samples
which runs them together and after waiting for a predefined
amount of time, checks how many audio packets has the
sink received, and if over a threshold, passes the test.
This test can be expanded after to cover more functionality from
these samples.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
