Internal bootloader will only run application image if valid product
header is present on flash. This means product header is required for
application that are not linked to code partition. Other applications
that are linked to code partition are meant to be run by MCUboot and
should not touch product header, with the exception of MCUboot itself
which is also run by internal bootloader so requires product header.
Default flash load offset for applications not linked to code partition
is set to 0x2400 as this is where internal bootloader looks for an
application image to run based on product header written by flasher.
Flash load offset for MCUboot is set from boot partition.
Valid product header is added by ezFlashCLI when using "flash_image"
command.
Co-authored-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
Applications that are run from MCUboot should reconfigure cache to
ensure they run from cached ared on flash. Initial cache configuration
is done by internal bootloader and is valid for MCUboot only.
Cache is configured once at boot, then new configuration is applied by
triggering SW reset.
Co-authored-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
Flash address is updated to 0x16000000, i.e. actual location instead of
remapped one. FLASH_BASE_ADDRESS is now set via dts.
Co-authored-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
sl_power_manager can only be used if HAL services infrastructure
is enabled, and that is controlled by SOC_GECKO_DEV_INIT kconfig option.
Therefore, SOC_GECKO_PM_BACKEND_PMGR may not be enabled without
SOC_GECKO_DEV_INIT.
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
Using EM2 or deeper sleep states (where HF clocks are off) requires
special care if BLE radio is used, since BLE radio relies on that clock,
and its power/clock requirements need to be taken into account
On SiLabs, radio PM is implemented as part of RAIL blob, which relies
on sl_power_manager HAL service. I've implemented SoC PM
state changes using sl_power_manager instead of emlib, and added
call to RAIL PM initialization in Gecko HCI driver.
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
Driver was based on can_sam. SAMC21 has only 1 interrupt for one
can "output", so can interrupt has to executes two lines of
interrupts.
CAN is configured to use OSC48M clock via GLCK7. GLCK7 is set
by divider configured from dts.
Signed-off-by: Kamil Serwus <kserwus@gmail.com>
This patch enables the PLL clock output and PLL ref clock
for second ethernet module in NXP's i.MxRT106x SoCs
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
To reduce the interrupt latency of MIWU events, the driver prepares a
dedicated callback function item list for each MIWU group in this PR. We
needn't check the MIWU table and group of the event in ISR. And the
maximum item number of each list is also limited to 8. After applying
this PR, the interrupt latency reduces to ~10us consistently.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Glitches were observed if a GPIO pin was configured by
ROM to a non-default state and then Zephyr PINCTRL
reconfigured the pin. The fix involves using the correct
PINCTRL YAML output enable and state flags. Reading the
current spin state and reflecting into new pin configuration
if the pin is output and the drive low/high properties are
not present. We also take advantage of GPIO hardware reflecing
the alternate output value in the parallel output bit before
enabling parallel output mode. Interpret boolean flags with
both enable and disable as do not touch if neither flag is
present. We give precedence to enable over disable if both
flags mistakenly appear. Note, PINCTRL always clears the
GPIO control input pad disable bit.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
1. Enable os_timer as a wakeup-source in the board
dts file.
2. Enable PM_DEVICE when PM is enabled.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Added logging declaration to soc.c of stm32wl, which resolves build
errors when using this SOC with DEBUG logging level
Fixes: #57655
Signed-off-by: Oliver King <oliver.king@steadconnect.com>
board:
- update device tree to use flexcomm devices to the chip design
- enable clocks (soc init file)
- setup connections for loopback test in system controller (board init
file)
tests:
- update board files (overlay, conf)
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Update MCUX ELCDIF driver to use new LCDIF bindings. This
update also adds support for configuring the root clock of
the ELCDIF module based on the pixel-clock property to the
RT11xx SOC clock init, as this SOC series has this IP block
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update DCNANO LCDIF IP to use shared lcd interface binding. This
requires changes to the RT5xx SOC and RT595 EVK, as this SOC
uses the LCDIF IP, and configures the clock for it based off
the new pixel-clock property.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce phy-clock property, which is used by MIPI devices to determine
the target clock frequency for the MIPI PHY. This property can vary
depending on the attached display and target framerate.
Update the MIPI DSI MCUX driver to utilize this property to configure
the MIPI host, and update the RT500 clock initialization to configure
the MIPI root clock based on this property.
Remove dphy-clk-div property from the MIPI DSI 2L binding, as it
is redundant with this change.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Improve the radio off code, mainly:
- Compile the file only if necessary, ie, LORA radio not in use
- Use pin information from DT, so that we do not need to hardcode pins
and can switch to dt-spec APIs.
- Improve error handling, includes, etc.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Although existing nRF SoCs have only one I2S instance, the nrfx_i2s
driver has now multi-instance API and the related nrfx configuration
symbols need to be used appropriately.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Ensure code cache is enabled at boot for RT11xx. CMSIS SystemInit should
enable the code cache, but if CONFIG_INIT_ARCH_HW_AT_BOOT=y and
CONFIG_CACHE_MANAGEMENT=y, then the cache will be disabled after
SystemInit is called. Since calling SCB_EnableICache will not
change hardware settings if the ICACHE is already enabled, just
call it unconditionally during init.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add Silicon Labs xG24-PK6010A (BRD4187C radio plug-in board)
support to the efr32_radio board.
Signed-off-by: Markus Fuchs <markus.fuchs@ch.sauter-bc.com>
For certain combinations of configuration parameters,
z_arm_init_arch_hw_at_boot() disables the instruction cache. Make sure
to re-enable it if required.
Signed-off-by: Jan Peters <peters@kt-elektronik.de>
Clearing of shared memory by one side of the communication
is no longer required after
commit 0620cb1fe1
("ipc: ipc_service: icmsg: Increase reliability of bonding")
was merged.
Signed-off-by: Emil Obalski <Emil.Obalski@nordicsemi.no>
To be consistent with the current NXP clocking scheme,
move the LPADC clocking code to the SOC files where
all of the other peripheral clocking is done.
Also remove any other SOC-specific code to the
respective SOC file and out of this driver.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
It is enabled by default if Device Tree includes a flash controller,
and disabled otherwise. SoC defconfig should not touch it.
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
The mps3 soc is missing PMU defines required for CMSIS. This
adds the defines __PMU_PRESENT and __PMU_NUM_EVENTCNT
enabling the api for the PMU.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Move STM32H7_DUAL_CORE to
soc/arm/st_stm32/stm32h7/Kconfig.soc
add select STM32H7_DUAL_CORE for SOC_STM32H745XX/H747XX
Cleanup old occurences where was set to y
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
This new Kconfig option lets the developer configure if the Cortex M4
core should be force-booted during M7 init independent of the BCM4
option byte.
This allows to disable this default behaviour via Kconfig which was not
possible so far.
Signed-off-by: Jan Krautmacher <jan@krautmacher.org>
Deprecates setting GPREGRET to the reset reason as this has been
replaced with the boot mode retention subsystem for nRF51/nRF52.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit adds the Gecko IADC driver and support for it to the
efr32bg_sltb010a board.
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
Secure Element's mailbox is needed for entropy gathering purposes.
Enable it in the EFR32MG24 SoC series Kconfig.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
- Add Gecko BURTC sys_clock driver to handle wake up from EM2,3 states
- Remove custom PM policy and dependency on HAL sl_power_manager service
- EM1 supported in all configurations
- EM2,3 supported only if SysTick is replaced by BURTC
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
This commit adds the SiLabs Bluetooth HCI driver. It also enables this
BLE HCI driver on the efr32bg_sltb010a board.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
HAL API changes in ethernet and pwm
SoC RT595 power management code change
west.yml update
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
This prevents configuration errors if a board is configured when
the SoC indicates segger RTT support but the segger module is
not available.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This adds the SPI driver for the Renesas SmartBond(tm) DA1469x MCU family.
The driver only supports controller mode. All four SPI modes are supported.
Note that the lowest supported speed is 2285714Hz.
Requesting speeds higher than 16MHz, will result in a 16MHz SCLK.
Co-authored-by: Stan Geitel <stan@geitel.nl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
This commit adds a missing `__weak` symbol to the `pm_policy_next_state`
function.
This is needed for e.g. `tests/kernel/profiling/profiling_api` to build
correctly.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The nRF9161 is technically a SiP (System-in-Package) that consists of
the nRF9120 SoC and additional components like PMIC, FEM, and XTAL,
so for nrfx/MDK the nRF9120 SoC is to be selected as the build target,
but since the nRF9161 is what a user can actually see on a board, using
only nRF9120 in the Zephyr build infrastructure might be confusing.
That's why in the top level of SoC definitions (for user-configurable
options in Kconfig, for example) the nRF9161 term is used and nRF9120
underneath.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
