Currently LLEXT on Xtensa supports relocatable extensions, linked for
a specific address range, while relocation itself takes place in a
temporary buffer. For this section addresses have to be set correctly
by the linker for their target locations.
This commit adds support for relocatable extensions, built without
using specific memory addresses and run at the same addresses, where
they are loaded.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Adds support for all relocation type produced by GCC
on ARM platform using partial linking (-r flag) or
shared link (-fpic and -shared flag).
Signed-off-by: Cedric Lescop <cedric.lescop@se.com>
This adds the necessary bits to enable memory mapping thread
stacks on both x86 and x86_64. Note that currently these do
not support multi level mappings (e.g. demand paging and
running in virtual address space: qemu_x86/atom/virt board)
as the mapped stacks require actual physical addresses.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This introduces support for memory mapped thread stacks,
where each thread stack is mapped into virtual memory
address space with two guard pages to catch
under-/over-flowing the stack. This is just on the kernel
side. Additional architecture code is required to fully
support this feature.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Previous commit changed the privileged stack size to be using
kconfig CONFIG_PRIVILEGED_STACK_SIZE instead of simply
CONFIG_MMU_PAGE_SIZE. However, the stack bound check function
was still using the MMU page size, so fix that.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Most places use CONFIG_X86_STACK_PROTECTION, but there are some
places using CONFIG_HW_STACK_PROTECTION. So synchronize all
to use CONFIG_X86_STACK_PROTECTION instead.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Some toolchains cannot create shared objects for Xtensa, with them we
have to use relocatable objects. Add support for them to llext.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This commit removes the `Kconfig.core` file. It's been largely unused, and
the only symbol it provides (`RISCV_CORE_E31`) overlaps with the SoC-layer
provided `SOC_SERIES_SIFIVE_FREEDOM_FE300`.
As of date, the only SoC that uses the E31 core in Zephyr is the FE310 SoC.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
When thread stack is defined as an array, K_THREAD_STACK_LEN()
is used to calculate the size for each stack in the array.
However, standalone thread stack has its size calculated by
Z_THREAD_STACK_SIZE_ADJUST() instead. Depending on the arch
alignment requirement, they may not be the same... which
could cause some confusions. So align them both to use
K_THREAD_STACK_LEN().
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When kernel stack is defined as an array, K_KERNEL_STACK_LEN()
is used to calculate the size for each stack in the array.
However, standalone kernel stack has its size calculated by
Z_KERNEL_STACK_SIZE_ADJUST() instead. Depending on the arch
alignment requirement, they may not be the same... which
could cause some confusions. So align them both to use
K_KERNEL_STACK_LEN().
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Simple rename to align the kernel naming scheme. This is being
used throughout the tree, especially in the architecture code.
As this is not a private API internal to kernel, prefix it
appropriately with K_.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Simple rename to align the kernel naming scheme. This is being
used throughout the tree, especially in the architecture code.
As this is not a private API internal to kernel, prefix it
appropriately with K_.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This call is used by syscalls machinery, and needs to be available for
extensions that use syscalls on ARM.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
arch_interface.h is for architecture and should not be
under sys/. So move it under include/zephyr/arch/.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There was old code to exit the simulator when there is a fatal
error. This updates the #ifdef and the function name so that
it can be used to exit both QEMU and simulator when a fatal
error occurs. This should help with twister runs as this will
fail immediately instead of having wait for timeout.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The #pragma to ignore array bounds for xtensa_soc_mmu_ranges[]
was a remnant before code refactoring during review. Since
this array is no longer declared __weak and as a zero length
array, the #pragma to ignore array bounds is no longer needed.
So remove them.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
During early boot in assembly, the function parameter to
z_x86_early_tls_update_gdt() should be the pointer to
the interrupt stack. However, what was passed instead
was the pointer to the x86_cpuboot struct. So fix it to
actually pass the stack pointer (which is stashed inside
the x86_cpuboot struct).
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
- spill windows in the current context (before switching task) since
it will be erased.
- Remove unnucessary load/mov
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
According to RISC-V Instruction Set Manual Chapter 3.3.2:
"The operation of WFI must be unaffected by the global interrupt
bits in mstatus
[...]
WFI is also required to resume execution for locally enabled
interrupts pending at any privilege level,
regardless of the global interrupt enable at each privilege level."
Disabling interrupts before executing `wfi` prevents a corner case
where an IRQ is presented just before executing `wfi`,
which would cause it to return directly into `wfi` and potentially
get stuck in sleep, instead of continuing to background processing.
When execution is resumed, interrupts are reenabled
and appropriate IRQ Handlers should be executed.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
Some old references to native_posix are better
refering to the native targets in general,
or being clarified as only applying to the old
native_posix like targets.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This allows the SoC to have total control on what MPU ranges
to be programmed at boot. This overrides the generic ranges
in the architecture core code.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Both CONFIG_XTENSA_SYSCALL_USE_HELPER and
CONFIG_XTENSA_INSECURE_USERSPACE are also applicable to MPU.
So move them out of the CPU_HAS_MMU block.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
For CPU without THREADPTR, we need an alternative way to figure
out if we are in user context. This extends the user context
check to do that via a brief syscall.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Calling z_mrsh_* functions require 7 arguments where the 7th is
the stack frame. Only the first 6 arguments are passed by
registers where the 7th must be done via stack. However, this
is not being done and an incorrect argument was being passed to
the z_mrsh_* functions as stack frame pointer. An obvious issue
would be dumping of stack during kernel oops, as incorrect data
was being printed or crashes due to inaccessible memory. So fix
it by properly populating the stack with correct stack frame
pointer as outgoing argument for the caller of z_mrsh_*
functions.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There is no need to do a call4 and jx. Simply do a callx4
is enough.
Also amended the now incorrect comment about how syscall
trampoline is set up. It is now a straight call4 instead of
the old 2x call4.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
POSIX has a custom implementation for thread abort
(z_impl_k_thread_abort) which lacks the tracing function
calls as in the generic version. So add them.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
ARM/Cortex-M has a custom implementation for thread abort
(z_impl_k_thread_abort) which lacks the tracing function
calls as in the generic version. So add them.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
On Intel ADSP platforms, additional "isync" is needed in interrupt
vector to synchronize icache when core is woken up from deeper
sleep state by an interrupt. This is only needed if DSP clock
gating is enabled.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Let's fix the error messages:
* native_posix is in general replaced with native_sim
* let's use hwmv2 names
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Replace uses of native_[posix,sim]_64 in the documentation
and kconfig help messages with native_[posix,sim]/native/64
to match the hwmv2 naming.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add support for the relocation type R_ARM_ARM_THM_CALL which is
produced for the ARM Thumb BL and BLX (branch immediate)
instructions.
These instructions are used for non-static functions like
void test1(void)
{
}
void main(void)
{
test1();
}
Without support for this relocation, test1() has to be static.
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
The opval argument of arch_elf_relocate() was modified by
adding the value stored at opaddr before passing it to
arch_elf_relocate(). This presumed that the addend would
always be stored as a raw value at opaddr, which is not the
case for all relocation types.
This PR modifies opval to be the absolute address of opval,
and moves the addition of the addend from llext_link_plt()
to the implementation of arch_elf_relocate().
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
RASID must not use 0 for any slot. According with documentation:
"""The operation of the processor is undefined if any two of the
four ASIDs are equal or if it contains an ASID of zero"""
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Configure a new Kconfig (`CONFIG_RISCV_HART_MASK`) so that it
is possible to mask the `mhartid` of a processor. This is
helpful in the cases when the hart id starts from non-zero
value.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
There is a #endif comment which was incorrectly marked with
CONFIG_HW_STACK_PROTECTION instead of
CONFIG_ARM64_STACK_PROTECTION, which is used at #if.
So update it.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Instead of using CONFIG_MMU_PAGE_SIZE for size of the privileged
stack, use the actual kconfig CONFIG_PRIVILEGED_STACK_SIZE.
This allows for changing the size of privileged stack, and
also aligns to the usage of CONFIG_PRIVILEGED_STACK_SIZE.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Instead of using CONFIG_MMU_PAGE_SIZE for size of the privileged
stack, use the actual kconfig CONFIG_PRIVILEGED_STACK_SIZE.
This allows for changing the size of privileged stack, and
also aligns to the usage of CONFIG_PRIVILEGED_STACK_SIZE.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There are two kconfigs that are security related and are x86
specific. Prefix them with X86 to put them under the x86
namespace.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Adds the necessary code required to unconditionally save/restore the
HiFi AE registers. The macros xchal_cp1_load and xchal_cp1_store
are defined in the Xtensa HAL.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Updates the xtensa_irq_base_save_area structure to include space
for saving/restoring the HiFi AudioEngine registers used by CP1.
The starting address of these HiFi AE registers also needs to be
referenced from assembly, so it is added to the set of symbols
symbols for which we need an offset to be auto-generated.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
This was part of the mega hwmv2 commit. Looks like hpet drivers heavily
relies on soc.h. Reverting this for now while we look for a proper fix
and remove reliance on soc.h for drivers.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
