The name read16() collides with other definitions within Zephyr. We
don't actually use this function here, so remove the definition. Fix
various other unnecessary name exports while we are here by adding
'static'.
Change-Id: I7eee8c527a62fea4e6e1bdae8a4874d8ce66596c
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
The read16() name collides with other definitions within zephyr. Make
it static and fix a few other unnecessary name exports while we are
here.
Change-Id: Id72d44a6b84b8d72c7ba2d0f34b29dbc1d02f2b6
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
The build_all tests contain an ever growing list of device drivers to
build. Ideally we minimize the number of images we build, but we
already observe that some of the tests, notably sensors, is too big
for some of our supported boards.
Rather disable an ever growing list of boards as the build_all tests
get bigger it would be better to split the tests into smaller chunks
that can reasonably be expected to run on any supported board.
We split the sensor test set into two, the division is arbitrary,
based on the name of the driver. This allows us to remove the filter
on the quark_d2000.
The current split into two groups is arbirary, in the future it is
inevitable that as the list of supported drivers grows, we will need
to further subdivied the larger tests.
Change-Id: If7ee00b3c8e1749c4c827f83d7cbc2feb70e56ad
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Introduce an architecture sorting of boards. This is to allow for
easier maintenance going forward as the number of boards grows. It
will be easier for any scripts to know the board/arch mapping without
having to maintain an explicit list of what boards are associated with
which arch. We can also do things like have architecture maintainers
cover reviews and branches for arch/${ARCH} and boards/${ARCH} going
forward.
Change-Id: I02e0a30292b31fad58fb5dfab2682ad1c5a7d5a7
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This will signify that we are in the development phase. Having the 1.5.0 on
master between two major releases might be confusing.
Jira: ZEP-1100
Change-Id: Ifbea81fbb8afe544af1fb30c79cb67dadb6d731d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Several platforms utilize a ihex image format. Rather than
duplicating the build bits in everyones makefile, pull it into the
toplevel makefile so we all share it.
Change-Id: I9097b06e7e386a69ce6ab4d4e4d56cc776adfec2
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The exact pin numbers for the nRF5 UART configuration is
board-specific, so the Kconfig default values should be in a
board-specific file.
Change-Id: Ibaacde292db191221e32b3626c68bf972dd26016
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Macros SYS_KERNEL_VER_MAJOR(), SYS_KERNEL_VER_MINOR(),
SYS_KERNEL_VER_PATCHLEVEL() capped their return values to 0-15 range,
even though documentation says "Each of these elements must therefore be
in the range 0 to 255, inclusive". Fix to corresponds to the docs. This
issue especially affected SYS_KERNEL_VER_PATCHLEVEL(), which could be
set to a high value to represent WIP code in-between releases.
Change-Id: I0b72fb68f3f0f8d3d3b321a5ba2c48671879dfbc
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
In order to avoid type conflicts make sure that ISR_HANDLED
is defined. This makes the ISR the correct type.
Make sure that the pointer for the unused argument for ISR
is of the proper type (NULL).
Change-Id: Ia1873f32d2e2174085f929e318a780a1b2574785
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
ARC does not align data structures by 4 bytes by default.
Add necessary linker sections.
Change-Id: I3bf7aa38b9bc8cba56f824469040c027968fa564
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
- the interrupt (both regular and fast) now does not do rescheduling
if the current thread is a coop thread or if the scheduler is not locked
- the _nanokernel.flags cache of _current.flags is not used anymore
(could be a source of bugs) and is not needed in the scheduling algo
- there is no 'task' field in the _nanokernel anymore: scheduling routines
call _get_next_ready_thread instead
- the _nanokernel.fiber field is replaced by a more sophisticated
ready_q, based on the microkernel's priority-bitmap-based one
- thread initialization initializes new fields in the tcs, and does not
initialize obsolete ones
- nano_private includes nano_internal.h from the unified directory
- The FIBER, TASK and PREEMPTIBLE flags do not exist anymore: the thread
priority drives the behaviour
- the tcs uses a dlist for queuing in both ready and wait queues instead
of a custom singly-linked list
- other new fields in the tcs include a schedule-lock count, a
back-pointer to init data (when the task is static) and a pointer to
swap data, needed when a thread pending on _Swap() must be passed more
then just one value (e.g. k_stack_pop() needs an error code and data)
- the 'fiber' and 'task' fields of _nanokernel are replaced with an O(1)
ready queue (taken from the microkernel)
- fiberRtnValueSet() is aliased to _set_thread_return_value since it
also operates on preempt threads now
- _set_thread_return_value_with_data() sets the swap_data field in
addition to a return value from _Swap()
- convenience aliases are created for shorter names:
- _current is defined as _nanokernel.current
- _ready_q is defined as _nanokernel.ready_q
- _Swap() sets the threads's return code to -EAGAIN before swapping out
to prevent timeouts to have to set it (solves hard issues in some
kernel objects).
Change-Id: Ib9690173cbc36c36a9ec67e65590b40d758673de
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Add board support for the Nordic Semiconductor's nRF51822 (nRF51 series)
Development Kit.
Change-Id: Idc082c6930bdebf3726fd453fb1309df7fab3f46
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Still missing a working timer driver, as SysTick is not really available
in this SoC series (enabled to avoid build issues, but not used).
Jira: ZEP-784
Change-Id: Ie1c8e6c5e8955ee7f260ce013f4451f9215f3457
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Make default value compatible with both nRF51 and nRF52.
Change-Id: I65dafbdf8518103becdd7388e9c0195ef1c4460d
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Default IRQ priority changed to 1 to so it can also be compatible with
nRF51 (Cortex-M0 allows up to 4 priority levels but Zephyr needs the
first two for the OS).
Change-Id: Ie57a729f5d932f020a7d1d7e55cf3741f1ecfbab
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Integrating the IRQ definitions for both nRF51 and nRF52, and defining
the set of IRQ values that are common to both.
Also switch the controller, uart and clock drivers to use the common
header definitions.
Change-Id: Id6816d7a97720896cfe4df83656fb8b1f8fb01fa
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Not disabling SysTick as it is optional by the spec.
SVC not used as there is no priority-based interrupt masking (only
PendSV is used).
Largely based on a previous work done by Euan Mutch <euan@abelon.com>.
Jira: ZEP-783
Change-Id: I38e29bfcf0624c1aea5f9fd7a74230faa1b59e8b
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
PM control function is used only by the PM subsystem. Update
documentations to make it clear and name the relevant structures and
functions with _pm_ in the name.
Jira: ZEP-1044
Change-Id: I29e5b7690db34a228ed30a24a2e912e1360a0090
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
This is used by a test case, and it's better to just put this
here instead of forking the linker scripts.
Change-Id: Ifbb90b73bb26118ae2422cc6feccb3db58a26f2c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This mechanism was intended to reserve space during the first pass for
certain data structures created by gen_idt, but this is unnecessary.
The only memory addresses that must be fixed between the two passes are the
locations of the interrupt stubs, which are in the .text section much
earlier than the generated data structures; they do not shift.
Change-Id: I3aab00e171e6a9ff439a7af8d69769e4c29337a7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This sample justs outputs the SPI FLASH IDs.
I think we should improve this to also output done, otherwise
it looks like its stuck or something.
Change-Id: I18d5919c1e25bb5aaa9ceba53793cc14b15f3c77
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
EM7D was recently merged, and one change suggested there was
to remove conditional checks for NSIM. It is OK to have the simulator
use the exact same memory addresses and sizes as would be found on the
board. This submission fixes EM9D and EM11D to be the same -- i.e.
to not have NSIM conditionals.
See ZEP-966.
Change-Id: Ia990ff7bb4b7ff5071af83723ed3d1420fdff012
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
The EM7D SOC is similar to EM11D, except it has different sized
iccm and dccm memories, and also has FIRQ with RGF_NUM_BANK==1.
To select this SOC on the board, all dip switches are in the up position.
See ZEP-966.
Change-Id: I864ffe0efdf367de0a8cd58e9c46efd7e401c671
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
It's not FMSTAT<0/1> but FSMSTAT<0/1>
Change-Id: I836cf001b7baefe86df67f13a8759ea4e697a28e
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Put the clk_perih_enable() call outside of the switch statement so it
actually runs.
Jira: ZEP-1048
Change-Id: Iee8efb4430d37dc74ce48f249bbf58d53125b520
Signed-off-by: Iván Briano <ivan.briano@intel.com>
Needed to resolve various undeclared symbols when SYS_POWER_MANAGEMENT
is enabled.
Jira: ZEP-1073
Change-Id: I21db2580efb15c80d84d9163fe9e8245d6dc0391
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Ring buffer section now resides under "other" topic, since the
ring buffer type is a general purpose type (like the singly and
doubly linked list types), rather than a kernel-specific type.
Enhances ring buffer section to improve content and improve
consistency with the form used elsewhere in the Kernel Primer.
Also corrects a minor error in the ring buffer API documentation.
Change-Id: Icaa8661524f80e31f173adee859844cadb38967f
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
