* Rename DT_SRAM_SIZE to DT_DRAM_SIZE since that is more correct
* Remove mmio-sram compatible since that is not correct for DRAM.
* Rename node label from sram0 to dram0
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Previously, DTS specification of physical RAM bounds did not
correspond to the actual bounds of system RAM as the first
megabyte was being skipped.
There were reasons for this - the first 1MB on PC-like systems
is a no-man's-land of reserved memory regions, but we need DTS
to accurately capture physical memory bounds.
Instead, we introduce a config option which can apply an offset
to the beginning of physical memory, and apply this to the "RAM"
region defined in the linker scripts.
This also fixes a problem where an extra megabyte was being
added to the size of system RAM.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
For HPET devices, configure it with fixed delivery mode because HPET
timer interrupt is needed to fuel the scheduler for all CPUS.
For all other type of devices, like UART, I2C, GPIO, Ethernet, etc.
configure them as lowest priority delivery mode, in which IO APIC
delivers the interrupt to the processor core that is executing at the
lowest priority among all the processors listed in the specified
destination. In this case, the device drivers can avoid the trouble of
handling repeated interrupts delivered to all CPUS.
Signed-off-by: Zide Chen <zide.chen@intel.com>
This driver was still using CONFIG_* values to determine its address,
IRQ, etc. Add a binding for an "intel,hpet" device and migrate this
driver to devicetree.
Fixes: #18657
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
XIP support in x86 was something of a mess. This
patch does the following:
- Generic ia32 SOC no longer defines a "flash" region
as generic X86 devices don't have a microcontroller-
like concept of flash. The same has been done for apollo_lake.
- Generic ia32 and apollo_lake SOCs starts memory at 1MB.
- Generic ia32 SOC may optionally have CONFIG_XIP enabled.
The board definition must provide a flash region definition
that gets exposed as DT_PHYS_LOAD_ADDR.
- Fixed definitions for RAM/ROM source addresses in ia32's
linker.ld when XIP is turned off.
- Support for enabling XIP on apollo_lake SOC removed, there's
no use-case.
- acrn and gpmrb boards have flash and XIP related definitions
removed.
- qemu_x86 has a fake flash region added, immediately after system
RAM, for use when XIP is enabled. This used to be in the ia32 SOC.
However, the default for qemu_x86 is to now have XIP disabled.
- Fixed tests/kernel/xip to run by default on boards that enable
XIP by default, plus an additional test to exercise XIP on
qemu_x86 (which supports it but has XIP switched off by default)
The overall effect of this patch is to:
- Remove XIP configuration for SOC/boards where it does not make
any sense to have it
- Support testing XIP on qemu_x86 via tests/kernel/xip, but leave
it off by default for other tests, to ensure it doesn't bit-rot
and that the system works in both scenarios.
- XIP remains an available feature for boards that need it.
Fixes: #18956
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
After witnessing some strange errors with memory not being
what it should be, lifiting everything above 1MB has solved
it. The Zephyr binary was being loaded into memory containing
reserved regions, resulting in data corruption.
We still simulate XIP for testing purposes by setting up the
memory map as follows:
0x000000 - 0x0FFFFF : Non-present
0x100000 - 0x4FFFFF : "Flash" ROM region
0x500000 - 0x8FFFFF : "SRAM" RAM region
For a total of 9 megabytes of physical RAM used.
Fixes problems observed in some large tests when code coverage
is enabled (which increases the amount of RAM used even more).
Fixes: #17782
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Previous the register size was 1M, technically the there are only a
small handful of registers defined in the IOAPIC, so shrinking the size
to 4k, so its as most one page large.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
We get several warnings of the form:
Warning (unit_address_format): /soc/uart@000003f8:
unit name should not have leading 0s
Fix these by remove the leading 0s.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that we have a common DT_SIZE_K macro use it instead of defining
__SIZE_K eveywhere. We also have DT_SIZE_M, so use that in a few
places as well.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Fix the ns16550 uart driver and relevant SoCs accordingly.
All generic settings are now DTS based.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
patch removes the mem.h and marcos used in that file are
moved appropriate board files. As there are boards with
different flash configuration but of same soc, flash and
ram size are moved to dts file instead of dtsi
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
1. Use compatible "ns16550" to match upstream binding
2. Add reg-shift as optional property to binding yaml
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
