Add RTC timer driver for CC13X2/CC26X2, and use it instead of systick
as system clock. It is necessary to use this timer for power
management support, so that the system can exit from deep sleep upon
expiry of timeouts.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
This driver was still using CONFIG_* values to determine its address,
IRQ, etc. Add a binding for an "intel,hpet" device and migrate this
driver to devicetree.
Fixes: #18657
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
We re-wrote the xtensa arch code, but never got around
to purging the old implementation.
Removed those boards which hadn't been moved to the new
arch code. These were all xt-sim simulator targets and not
real hardware.
Fixes: #18138
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
MEC1501 RTOS timer internal counter is on the 32KHz clock domain.
The register interface is on the AHB clock. When the timer is started
hardware synchronizes to the next 32KHz clock edge resulting is a
variable delay moving the value in the preload register into the
count register. The maximum delay is one 32KHz clock period (30.5 us).
We work-around this delay by checking if the timer has been started
and not using the count value which is still 0. Instead we state zero
counts have elapsed.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
The variable enabling entry to the zero latency interrupt compensation
loop was named generically, and its logic inverted, making the code
difficult to understand. Change the name and initial value to more
clearly indicate its role.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
* it's based on ARC SecureShield
* add basic secure service in arch/arc/core/secureshield
* necesssary changes in arch level
* thread switch
* irq/exception handling
* initialization
* add secure time support
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
* use global free running counter as global wall clock (clock source)
* use arc internal timer 0 as local time event (clock event)
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Update the logic in a corner case, when the target comparator value is
one cycle ahead of the counter value.
Experiments have shown, that `set_comparator(cyc + 1);` might be not
enough in that case, and we still may (rarely) miss the interrupt.
This could happen when the counter incremented its value after the `dt`
variable was set. As we should set the comparator value two cycles
ahead to be on the safe side, increment the target comparator value
by 2 instead of 1.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Add a kernel timer driver for the MEC1501 32KHz RTOS timer.
This timer is a count down 32-bit counter clocked at a fixed
32768 Hz. It features one-shot, auto-reload, and halt count down
while the Cortex-M is halted by JTAG/SWD. This driver is based
on the new Intel local APIC driver. The driver was tuned for
accuracy at small sleep values. Added a work-around for RTOS
timer restart issue. RTOS timer driver requires board ticks per
second to be 32768 if tickless operation is configured.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
On some SoCs the frequency of the system clock is obtained at run time
as the exact configuration of the hardware is not known at compile time.
On such platforms using CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC define
directly introduces timing errors.
This commit replaces CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC by the call
to inline function sys_clock_hw_cycles_per_sec() which always returns
correct frequency of the system clock.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The native_posix timer driver was still using the
legacy timer API.
Replace it with a new version, which is aligned with
the new kernel<->system timer driver API,
and which has TICKLESS_CAPABLE support
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
When the tick rate was less than MIN_DELAY, bumping a "too soon"
expiration by just one tick may not be enough and we could
theoretically miss the counter.
Instead, eliminate the MIN_DELAY computation and write to the spec:
NRF guarantees that the RTC will generate an interrupt for a
comparator value two cycles in the future. And further, we can test
at the set point to see if we "just missed" the interrupt (i.e. zero
cycles delay) and flag a synchronous interrupt. So we only need to
miss a requested interrupt now for the special case of exactly one
cycle in the future, and then we're only late by one cycle. That's
optimal.
Also fixes an off-by-one in the next cycle computation. By API
convention, an ticks argument of one or less means "at the next tick"
and not "right now". So we need to add one to the target cycle to
avoid incorrectly triggering a synchronous interrupt. This was a
non-issue when a tick is longer than a hardware cycle but is needed
now.
Also handles the edge case with zero latency interrupts (which are
unmaskable) which might mess up timing. This was always a problem,
but we're more sensitive now and it's comparatively more likely to
occur.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The MVIC is no longer supported, and only the APIC-based interrupt
subsystem remains. Thus this layer of indirection is unnecessary.
This also corrects an oversight left over from the Jailhouse x2APIC
implementation affecting EOI delivery for direct ISRs only.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This is an oddball API. It's untested. In fact testing its proper
behavior requires very elaborate automation (you need a device outside
the Zephyr hardware to measure real world time, and a mechanism for
getting the device into and out of idle without using the timer
driver). And this makes for needless difficulty managing code
coverage metrics.
It was always just a hint anyway. Mark the old API deprecated and
replace it with a kconfig tunable. The effect of that is just to
change the timeout value passed to the timer driver, where we can
manage code coverage metrics more easily (only one driver cares to
actually support this feature anyway).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
move misc/util.h to sys/util.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
move clock_control.h to drivers/clock_control.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
move power.h to power/power.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Fix path for system_timer.h and loapic.h, we moved it to
include/drivers/timer/ and include/drivers/interrupt_controller/
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The existing local APIC timer driver (loapic_timer.c) has bitrotted
and doesn't support TICKLESS_KERNEL, which is the preferred mode of
operation. This patch introduces a completely new driver, called
the APIC timer driver - the name is changed to allow the drivers to
continue to coexist in the short term, and also because "APIC timer"
isn't ambiguous (the I/O APICs do not have timers).
This driver makes no attempt to work with the MVIC timer as the
previous version did, because MVIC support is deprecated.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Move internal and architecture specific headers from include/drivers to
subfolder for timer:
include/drivers/timer
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The Quark D2000 is the only x86 with an MVIC, and since support for
it has been dropped, the interrupt controller is orphaned. Removed.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
The defines related to IRQ priority don't exist and aren't used. So
just pass 0 to IRQ_CONNECT for the priority field.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The defines should have had a _0 on them, now that we generate the
proper defines, fixup the cases that used that old scheme.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Found a few annoying typos and figured I better run script and
fix anything it can find, here are the results...
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Change code from using now deprecated DT_<COMPAT>_<INSTANCE>_<PROP>
defines to using DT_INST_<INSTANCE>_<COMPAT>_<PROP>.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
More clearly differentiate MVIC vs. APIC timer code, and use new APIC
accessors in include/drivers/loapic.h. Remove extraneous comments, and
other light cleanup work.
This driver is in need of a serious overhaul -- despite appearing to
have support for TICKLESS_KERNEL and DEVICE_POWER_MANAGEMENT, bitrot
has taken its toll and the driver will not build with these enabled.
These should be removed or made to work... but not in this patch.
Old x2APIC-related accessors in kernel_arch_func.h are eliminated.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Simple renaming and Kconfig reorganization. Choice of local APIC
access method isn't specific to the Jailhouse hypervisor.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
The litex_timer driver used hard coded tick rate (set to 100 ticks
per second). This commit replaces the fixed value with a call to
system function which takes under account system configuration.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
Add LiteX timer driver with bindings for this device.
Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
We shall not enable by default a system timer in ARM
platforms, namely the SysTick, the Nordic, or the SAM0
RTC timer, simply by assessing the hardware capabilities
(e.g. by conditioning on CPU_CORTEX_M_HAS_SYSTICK).
Instead, now, all ARM platforms needs to explicitly set
their system timer module. Note that this has already
been the case for ca 80% of the ARM platforms.
This clean-up allows us to decouple HW capabilities from
system configuration (for example, Nordic platforms may
enable option CPU_CORTEX_M_HAS_SYSTICK, and still use
the platform-specific RTC timer for system timing).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit renames the symbol CPU_HAS_SYSTICK to
CPU_CORTEX_M_HAS_SYSTICK, to look similar to all
other CPU_CORTEX_M_HAS_ options, and moves the
K-config symbol definition from arm/core/Kconfig to
arm/core/cortex_m/Kconfig.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Enabling the RTC event is intended to support peripheral-to-peripheral
interconnects, so introduces a request for HFCLK and PCLK16M when the
event is triggered. This specific event is never used with PPI so
enabling events apparently does nothing but increase power consumption.
Closes#15513
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Clearing the pending IRQs when resetting the timeout fixes the
forward time drifting, but the change needs more investigation
until we are sure this won't break kernel time management.
Reverting the change to get 1.14 release out.
This reverts commit 2895da02a4.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
In the unlucky scenario of a SysTick event (wrap) occurring
while we re-program the last_load value, the SysTick ISR
will run immediately after we unlock interrupts. In that
case the timeout we have just configured will expire
instantaneously, leading to operations being executed
much earlier than expected. Avoid this by clearing possibly
pending SysTick exceptions (writing 1 to ICSR.PENDSTCLR).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
When the counter reaches zero, it reloads the value in
SYST_RVR on the next clock edge. This means that if the
LOAD value is N, the interrupt ("tick") is triggered
every N+1 cycles. Therefore, when we operate in tickless
mode, and we want to schedule the next timeout, we need
to configure the LOAD value with last_load - 1, in order
to get an event in last_load cycles.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
When the counter reaches zero, it reloads the value in
SYST_RVR on the next clock edge. This means that if the
LOAD value is N, the interrupt ("tick") is triggered
every N+1 cycles. Therefore, when we operate in non-
tickless mode, we need to configure the LOAD value
with CYC_PER_TICK - 1, in order to get an event
every CYC_PER_TICK cycles.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The SysTick logic looked logically sound, but it was allowing us to
set a LOAD value as low as 512 cycles. On other platforms, that
minimum future interrupt delay is there to protect the "read, compute,
write, unmask" cycle that sets the new interrupt from trying to set
one sooner than it can handle.
But with SysTick, that value then becomes the value of the LOAD
register, which is effectively the frequency with which timer
interrupts arrive. This has two side effects:
1. It opens up the possibility that future code that masks interrupts
longer than 512 cycles will miss more than one overflow, slipping
the clock backward as viewed by z_clock_announce().
2. The original code only understood one overflow cycle, so in the
event we do set one of these very near timeouts and then mask
interrupts, we'll only add at most one overflow to the "elapsed()"
time, slipping the CURRENT time backward (actually turning it into
a non-monotonic sawtooth which would slip every LOAD cycle) and
thus messing up future scheduled interrupts, slipping those forward
relative to what the ISR was counting.
This patch simplifies the logic for reading SysTick VAL/CTRL (the loop
wasn't needed), handles the case where we see more than one overflow,
and increases the MIN_DELAY cycles from 512 to 1/16th of a tick.
Fixes#15216
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Update the files which contain no license information with the
'Apache-2.0' SPDX license identifier. Many source files in the tree are
missing licensing information, which makes it harder for compliance
tools to determine the correct license.
By default all files without license information are under the default
license of Zephyr, which is Apache version 2.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Rename reserved function names in drivers/ subdirectory. Update
function macros concatenatenating function names with '##'. As
there is a conflict between the existing gpio_sch_manage_callback()
and _gpio_sch_manage_callback() names, leave the latter unmodified.
Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
Per #13610, recent changes to this driver seem to have introduced
unexpected latency regressions. This patch effectively reverts these
patches which changed the meat of the driver:
ac36886e62 drivers: nrf: timer: add inline qualifier where
inlining is intended
084363a0dc drivers: timer: nrf: refactor for speed and correctness
71882ff8c4 drivers: timer: nrf: drop unnecessary counter mask
4b24e88fa4 drivers: timer: nrf: use irq_lock instead of spinlock
While backporting these seemingly unrelated hygiene patches:
7cbdb6c5c0 drivers/timer: Restore non-tickless tick count behavior
d30c9aeafd drivers: nrf_power_clock: Migrate to DTS.
75f77db432 include: misc: util.h: Rename min/max to MIN/MAX
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The existing device_set_power_state() API works only in synchronous
mode and this is not desirable for devices(ex: Gyro) which take
longer time (few 100 mSec) to suspend/resume.
To support async mode, a new callback argument is added to the API.
The device drivers can asynchronously suspend/resume and call the
callback function upon completion of the async request.
This commit adds the missing callback parameter to all the drivers
to make it compliant with the new API.
Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
This is intended to initialize CPU-local timer devices, but HPET is
global so we have nothing to do.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Redefining the config will not let another (out-of-source) driver be
chosen instead of the default. The driver is practically forced by the
soc settings. This commit moves default settings from soc/arm/nordic_nrf
into the drivers themselves.
Signed-off-by: Thomas Stenersen <thomas.stenersen@nordicsemi.no>
Update reserved function names starting with one underscore, replacing
them as follows:
'_k_' with 'z_'
'_K_' with 'Z_'
'_handler_' with 'z_handl_'
'_Cstart' with 'z_cstart'
'_Swap' with 'z_swap'
This renaming is done on both global and those static function names
in kernel/include and include/. Other static function names in kernel/
are renamed by removing the leading underscore. Other function names
not starting with any prefix listed above are renamed starting with
a 'z_' or 'Z_' prefix.
Function names starting with two or three leading underscores are not
automatcally renamed since these names will collide with the variants
with two or three leading underscores.
Various generator scripts have also been updated as well as perf,
linker and usb files. These are
drivers/serial/uart_handlers.c
include/linker/kobject-text.ld
kernel/include/syscall_handler.h
scripts/gen_kobject_list.py
scripts/gen_syscall_header.py
Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
Converts the rv32m1 timer driver to use 'DT_' prefixed defines instead
of deprecated non-prefixed defines.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
