These interrupt settings are SOC specific. So, move them to the
SOC level of Kconfig.
As IRQ priority is fixed in D2000, changed the value to 0 to
make it consistent with what other shim drivers are using.
Change-Id: Id20bed46c478a7555ae976e3a3063ba2cb099788
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
This will improve the speed when flashing an image to the board:
before:
downloaded 4936 bytes in 7.982860s (0.604 KiB/s)
after:
downloaded 4936 bytes in 4.486743s (1.074 KiB/s)
Change-Id: I0209d53ba15dbf8e3f16e2d3675a35b58342776a
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The IRQ triggering condition should be specified by SoC as it is
a decision for hardware design. This should not be configurable
in kconfig.
The default is to be triggered on rising edge, just as the same
old kconfig did.
Change-Id: If59d88a30711eb8e03d9cc4f409055cefe1995c5
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Moves those kconfig options which should be declared in
SoC or board header files instead. These are the one
that are tied to SoC or board and there is no need
for them to be configurable in kconfig.
Change-Id: I243d634f1a4a11dc8dc3530d95f93371015492b7
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This file was misplaced here. Atom board is now available only
for minnowboard.
Change-Id: If5a0d723600f957e2b024848b8cb8aac2e7a7ff9
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Most of the SoC and board Kconfig use the same values for
driver initialization priorities. So refactor them, and
discard duplicate ones.
The shared IRQ init priority was changed so that the kernel
default init and device init priorities can be standardized
across all SoC/boards. Same goes for DesignWare SPI driver.
This also changes the UART_CONSOLE_PRIORITY and
IPM_CONSOLE_PRIORITY to UART_CONSOLE_INIT_PRIORITY and
IPM_CONSOLE_INIT_PRIORITY, to standardize across all drivers.
Note that this does not take away the ability to override
those values. This just provides reasonable defaults such
that there is virtually no need to override.
Change-Id: Ibbd95d802c637df06f9a2fd48763ee1e6f4ff627
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The pinmux base address and number of pins are now defined in SoC or board
header files instead of specifying them in kconfig. This is because
the pinmux ties directly to the SoC (or board expanders) so the base
address and number of pins do not need to be configurable in kconfig.
Change-Id: Ib6090d7d022b491f3fe8f522858281504c6302bb
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds conditions to the default values for device init priorities,
and make them follow the dependencies on the config options. This cleans
up the resulting .config a bit, making it easier to read.
Change-Id: Ib05806ac6108d465ffe245142ecca7a51be6df22
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There are two major issues with the kconfig:
() Some of the config options have incorrect dependencies inside help
under menuconfig. For example, CONFIG_GPIO depends on BOARD_GALILEO.
() Since the SoC and board specific kconfig files are parsed first,
the help screen would say, for example, CONFIG_SPI is defined at
arch/arm/soc/fsl_frdm_k64f/Kconfig. This is incorrect because
the actual config is defined in drivers/spi/Kconfig.
These cause great confusion to users of menuconfig/xconfig.
To fix these, the SoC and board defaults are now to be parsed last.
Note that the position swapping of defaults in this patch is due to
the fact the the default parsed last will be used.
And, spi_test is broken due to the fact that it requires
CONFIG_SPI_INTEL_PORT_1, but never enables it anywhere. This is
bypassed for now.
Origin: refactored and edited from existing files
Change-Id: I2a4b1ae5be4d27e68c960aa47d91ef350f2d500f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This moves the STM32 based boards (Nucleo F103RB and STM32 Mini A15) to
the "new" pinmux model.
Change-Id: I190df271a6b83fafeec0b281cd4ee7cf13d7e7db
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
This driver doesn't provide any API, it only initializes the pinmux
controller to appropriate values depending on the board.
The first board to use this new infrastructure is the Arduino 101 board,
because it is alphabetically the first.
To better organize code for the different SoCs and boards, a "family"
level is created in the 'drivers/pinmux' directory. The Arduino 101
board is part of the Quark MCU "family".
The PINMUX_DEV configuration (and functionality) is removed for now, it
will be added back when the pinmux_dev drivers are (re)introduced, with
clearer semantics.
Change-Id: Idf5cc3caf6be620aa50828ae8fdc535df6caf458
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Enable 72MHz SYSCLK by default. The board does not have an on-board
quartz, however the STLink frontend produces a 8MHz clock signal that we
can use. Since the clock signal is not coming from an oscillator, HSE
bypass must be enabled. Make sure not to exceed 36MHz clock on APB1 bus.
Change-Id: I6b0b499a1cc4b0deccbfa374fc9ca3e3e8cc38c5
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Enable 72MHz SYSCLK by default. We use the fact that there is an
on-board 8MHz quartz oscillator available as HSE clock signal. Make sure
not to exceed 36MHz clock limit on APB1.
Change-Id: I9ebc2144910253e68cd8a9b078884852f01c2cab
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Before moving pinmux related code to 'drivers/pinmux' fix their return
codes to be consistent with the rest of the API.
Change-Id: Ie84f64e93745d44bef8b9d2119f6a05cdc8cb8c4
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Add configuration for Nucleo-64 F103RB board. By default, the UART
console is forwarded to USART2, available on STLink V2-1 USB
connector. All GPIO ports available on the connecot headers are
enabled.
Change-Id: I266170d1288ef27f668410c5737c46cdf716e137
Origin: Original
Signed-off-by: Maciek Borzecki <maciek.borzecki@gmail.com>
Introduce configuration for STM32 MINI A15 embedded development
board. The board has a STM32F103VET6 MCU on board. The MCU has 64KB of
SRAM and 512KB of flash.
The board has the following peripherals:
- RS232 port on DB9 connector, connecting to USART1, pin mapping:
- PA9-US1-TX
- PA10-US1-RX
- a LED diode (U2) connected to pin PB5
- micro SD card connector with pin mapping:
- PC8-SDIO-D0
- PC9-SDIO-D1
- PC10-SDIO-D2
- PC11-SDIO-D3
- PC12-SDIO-CK
- PD2-SDIO-CMD
- on board SPI flash AT45DB161D-SU, pin mapping;
- PA4-SPI1-NSS
- PA5-SPI1-SCK
- PA6-SPI1-MISO
- PA7-SPI1-MOSI
- button (K1), connecting PB15 to GND
- 40-pin header connector XS5
Change-Id: Ia378b105abb25fb589a100185ea96512a5f98cf3
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Quark AON counter and timer sub-drivers. They are based
on the QMSI drivers.
In order to enable this driver, the following options
must be set.
CONFIG_QMSI_DRIVERS
CONFIG_QMSI_INSTALL_PATH
CONFIG_COUNTER
Origin: Original
Change-Id: Idbeabfaef3408f4d645b0e64a337d7f5f0f357c7
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
All driver APIs (i2c, spi, gpio, etc.) return 'int' type, but pinmux
APIs. So this patch changes the returning type from 'uint32_t' to
'int' from include/pinmux.h and fixes all pinmux drivers according.
Besides keeping consistency between all drivers APIs, this patch is
also applicable for the errno.h code transition. Pinmux drivers will
return negative errno.h codes so returning 'int' is more suitable
than 'uint32_t'.
Change-Id: I2a6e92d567a0e21fec363226da6197df94657d4b
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This adds a menu to enclose all board Kconfig. So the board
configs do not appear on the top level out of context in
menuconfig. This also reflects the SoC options where these are
under menus for each architecture.
Change-Id: I76ce2bf1acf7cbd2673ceb2eac71e96cdca2ff35
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This makes the board selection dependent on SoC selection. For example,
select Atmel SAM3 will only allow "Arduino Due" as board selection.
This disallows incompatible SoC/board combination, like K64F with
Arduino Due.
JIRA: ZEP-106
Change-Id: I675961cf33db5a0058fc68f14c8f16978f9c6b95
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This board is now part of qemu_x86 and shares the same file except
the configuration which makes it build with IAMCU.
JIRA: ZEP-103
Change-Id: I9a9911d013b493240c089ce71e9f95687dcc02a3
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Making pinmux depend on GPIO breaks many tests and configurations
when running on real hardware. This should be added as local
configuration in the defconfig instead.
Change-Id: Ibbf1c9a3428ed692937383bf85218b0c120cbe44
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
CONFIG_HPET_TIMER_LEVEL_LOW and CONFIG_HPET_TIMER_RISING_EDGE are
selected from same choice option so cannot be both selected.
Since HPET_TIMER_FALLING_EDGE is the default only options overriding
this were left in defconfig files.
Fix following:
Merging prj_x86.conf
.config:10:warning: override: HPET_TIMER_RISING_EDGE changes choice
state
Change-Id: I5c88d2c0ae309afa11d9fae116235a8a424a2408
Signed-off-by: Szymon Janc <ext.szymon.janc@tieto.com>
Many bugs that have taken months to tease out could have been
instantly exposed had we run all our sanity checks on this
ABI.
Origin: Original code or copied from boards/qemu_x86
Change-Id: I6a5038bf99379470c3f736857d104024d3fc7978
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The pinmux API was modified to expand the meaning of the 'func' argument
to allow it to represent more than a pre-configured function. This was done
to reasonably accommodate a larger range of pin configuration options
offered by other MCUs, such as the Freescale K64 (up to 8 pin functions,
plus interrupt, pullup/down, drive strength, open-drain, slew rate, etc.).
This allows bit fields to be used to define various settings.
Change-Id: I2b216b822c6bae7133eed01c8c3339bb47b6c5db
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
In the pinmux_dev driver for the Quark SE development board in
pinmux_dev_set() the variable 'mode' was used, but it should have been
'func'. This was causing a compilation error:
/home/vinicius/work/zephyr/boards/quark_se_devboard/pinmux.c:
In function 'pinmux_dev_set':
/home/vinicius/work/zephyr/boards/quark_se_devboard/pinmux.c:245:23:
error: 'mode' undeclared (first use in this function)
uint32_t mode_mask = mode << (pin_no << 1);
Change-Id: I5b9df7c6b488dc5b8819fcf59bb3b994d9d4820b
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Enable support for WinBond W25QXXDV SPI flash on
arduino 101 platform.
Change-Id: Ia4dc73f956f79c6a56a31bc3dfca4e5298447742
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
The peripherals utilizing UART were required to register their own
ISR rountines. This means that all those peripherals drivers need
to know which IRQ line is attached to a UART controller, and all
the other config values required to register a ISR. This causes
scalibility issue as every board and peripherals have to define
those values.
Another reason for this patch is to support virtual serial ports.
Virtual serial ports do not have physical interrupt lines to
attach, and thus would not work.
This patch adds a simple callback mechanism, which calls a function
when UART interrupts are triggered. The low level plumbing still needs
to be done by the peripheral drivers, as these drivers may need to
access low level capability of UART to function correctly. This simply
moves the interrupt setup into the UART drivers themselves. By doing
this, the peripheral drivers do not need to know all the config values
to properly setup the interrupts and attaching the ISR. One drawback
is that this adds to the interrupt latency.
Note that this patch breaks backward compatibility in terms of
setting up interrupt for UART controller. How to use UART is still
the same.
This also addresses the following issues:
() UART driver for Atmel SAM3 currently does not support interrupts.
So remove the code from vector table. This will be updated when
there is interrupt support for the driver.
() Corrected some config options for Stellaris UART driver.
This was tested with samples/shell on Arduino 101, and on QEMU
(Cortex-M3 and x86).
Origin: original code
Change-Id: Ib4593d8ccd711f4e97d388c7293205d213be1aec
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
That implementation is not galileo-specific, but rather a generic way of
rebooting an x86 target. Needs SoC support.
Change-Id: I9c3374a8ab57a624d9d9b7090260c5b11fe4e773
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
CC2520 can handle up to 8Mhz SPI SCLK frequency, thus let's use it. It
will help to avoid timing issuse while transmitting and receiving (i.e.:
getting registers or buffers from CC2520 through SPI will be fast and
won't impede RX/TX events too much).
Change-Id: I3391993e25ffbe166028923b9afb777a8451a35e
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Base address registers and IRQs are set in Kconfig.
Set proper SPI default to various quark_se_ss based boards.
Change-Id: Iadaae551f441457bef334f94f68cafa7c3e499d0
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Quark SE development board provides an ARC core and thus requires a
board definition so developpers can flash this core as well.
Change-Id: I3612e3b0c4d7085af4fcf3fa1f6233849a05c8b4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This board is not supported and not available for general public.
Use the Quark SE CRB/Devboard instead.
Change-Id: Id0f8c08bbacb812ef00fe9502b4acecf4f31ffd7
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
There can only be one instance of an ADC, but we have code setup for
multiple.
Change-Id: I94eae2450bdc6b138ebad66f80a7c451cefe32a9
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
The radio driver was using DW spi and gpio drivers hardcoded.
Now it will check if SPI_DW or SPI_QMSI is set.
Change-Id: I4e12ef7c071058218c1cc714c62fed90a9f5eb06
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
Using level will just flood the handler, as the concerned gpio pins
stays on level for some time.
Change-Id: I991d818783170b09c326350c04bb588c7324892c
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Fixing the flash script so that we only have one for the process of writing
out the ROM and the OS images.
Change-Id: I6fc8bd8eee553a17c0036da3ce5b89510f3b57d8
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
- Use interface script from openocd distribution
- add debug support
Change-Id: If7e0ab0ad1fc6e67ca648a0a7c32356b3db90cf0
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
