Commit graph

2509 commits

Author SHA1 Message Date
Andrzej Głąbek
cab631e00c boards: arm: nrf5340pdk: Fix i2c1 pin assignments
Pins p0.02/p0.03 that were assigned to the i2c1 node are NFC pins.
Use p1.02/p1.03 instead, which are routed to the standard I2C location
in the Arduino header.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2020-05-22 14:52:40 +02:00
Peter Bigot
b0d509bc0d boards: arm: nrf5340pdk: fix pin assignments
I2C1 used LED pins rather than the ones in the Arduino header
position.  SPI2 used Arduino D0 for both SCK and MOSI; replace all
pins with D11-D13 which are the standard location for SPI on the
Arduino header.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2020-05-21 22:30:25 +02:00
Maureen Helm
7197e7c8fc boards: frdm_k82f: Enable adc instance and pinmux
Enables the adc instance and pinmux associated with arduino header pin
A2 on the frdm_k82 board. Adds adc to the board yaml to ensure we build
adc samples/tests for this board in CI.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-05-21 11:01:18 +02:00
Andrei Gansari
99dcc2a3b9 boards: lpcxpresso55s69 add Arduino mapping
Map Arduino interface to LPCXpresso55S69 pins.
Also tell which SPI interface is used by Arduino.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2020-05-20 19:02:36 +02:00
Andrei Gansari
d9315ba44b boards: lpcxpresso55s69 add mikroBUS mapping
Map mikroBUS interface to LPCXpresso55S69 pins.
Also tell which SPI interface is used by mikroBUS.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2020-05-20 19:02:36 +02:00
Erwan Gouriou
f87586b06c boards: stm32: pinmux: Restore Kconfig control on pinmux(sdmmc)
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_DISK_ACCESS_STM32_SDMMC flag to for each SDMMC pinmux
configuration.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-20 12:09:19 +02:00
Erwan Gouriou
25dfbe3e7e boards: stm32: pinmux: Restore Kconfig control on pinmux (i2s)
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_I2S flag to for each i2s pinmux configuration.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-20 12:09:19 +02:00
Erwan Gouriou
54a85d66e4 boards: stm32: pinmux: Restore Kconfig control on pinmux (can)
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_CAN flag to for each can pinmux configuration.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-20 12:09:19 +02:00
Erwan Gouriou
0990109f45 boards: stm32: pinmux: Restore Kconfig control on pinmux (dac)
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_DAC flag to for each dac pinmux configuration.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-20 12:09:19 +02:00
Erwan Gouriou
0993fa5682 boards: stm32: pinmux: Restore Kconfig control on pinmux (adc)
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_ADC flag to for each adc pinmux configuration.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-20 12:09:19 +02:00
Erwan Gouriou
b3fbc3aa8e boards: stm32: pinmux: Restore Kconfig control on pinmux (pwm)
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_PWM flag to for each pwm pinmux configuration.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-20 12:09:19 +02:00
Erwan Gouriou
572e1c4980 boards: stm32: pinmux: Restore Kconfig control on pinmux (i2c)
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_I2C flag to for each i2c pinmux configuration.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-20 12:09:19 +02:00
Erwan Gouriou
1a7bcccd69 boards: stm32: pinmux: Restore Kconfig control on pinmux (spi)
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_SPI flag to for each spi pinmux configuration.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-20 12:09:19 +02:00
Erwan Gouriou
f9d5df3937 boards: stm32: pinmux: Restore Kconfig control on pinmux (serial)
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_SERIAL flag to for each serial pinmux configuration.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-20 12:09:19 +02:00
Kumar Gala
3393600017 boards: Make GPIO pin config default for LEDs instead of PWM
Add an additional check for CONFIG_PWM to decide if pins associated with
LED are configured for GPIO or PWM.

Fixes #25337

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-20 10:32:11 +02:00
Gerson Fernando Budke
854d3be4b2 boards: sam0: pinmux: Add Kconfig check for GMAC
To avoid pin conflicts add CONFIG_ETH_SAM_GMAC flag for each gmac
pinmux config.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2020-05-19 17:25:59 +02:00
Gerson Fernando Budke
eabae8b0f0 boards: sam0: pinmux: Add Kconfig check for I2C
To avoid pin conflicts add CONFIG_I2C_SAM0 flag for each i2c pinmux
config.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2020-05-19 17:25:59 +02:00
Gerson Fernando Budke
48a4e459e9 boards: sam0: pinmux: Add Kconfig check for SPI
To avoid pin conflicts add CONFIG_SPI_SAM0 flag for each spi pinmux
config.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2020-05-19 17:25:59 +02:00
Gerson Fernando Budke
85ca73ccf8 boards: sam0: pinmux: Add Kconfig check for UART
To avoid pin conflicts add CONFIG_UART_SAM0 flag for each uart pinmux
config.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2020-05-19 17:25:59 +02:00
Andreas Sandberg
81347239cd boards: arm: b_l072z_lrwan1: Fix flashing of big firmware
OpenOCD currently uses a single-bank STM32 configuration for the
B_L072Z_LRWAN1 board. This causes flashing to fail when the firmware
image is larger than the first bank. Switch to the dual bank
configuration to make this work.

Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
2020-05-18 19:14:21 +02:00
Wentong Wu
559238a1f7 boards: qemu_cortex_a53: enable icount mode
Enable icount mode for qemu_cortex_a53 platform, The icount shift
value is selectd based on cpu clock frequency of this platform.
The virtual cpu will execute one instruction every 2^shift ns of
virtual time.

Signed-off-by: Wentong Wu <wentong.wu@intel.com>
2020-05-14 13:52:07 +02:00
Wentong Wu
7bc807e478 boards: qemu_cortex_m3: enable icount mode
Enable icount mode for qemu_cortex_m3 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.

Signed-off-by: Wentong Wu <wentong.wu@intel.com>
2020-05-14 13:52:07 +02:00
Wentong Wu
1080e8d875 boards: qemu_cortex_m0: enable icount mode
Enable icount mode for qemu_cortex_m0 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.

Signed-off-by: Wentong Wu <wentong.wu@intel.com>
2020-05-14 13:52:07 +02:00
Wentong Wu
0b2e633ce3 boards: remove the existing qemu icount configuration
Remove the existing qemu icount configuration because icount mode
will be controlled by Kconfig QEMU_ICOUNT so that none suitable
cases(especially networking cases) can exclude icount configuration

Signed-off-by: Wentong Wu <wentong.wu@intel.com>
2020-05-14 13:52:07 +02:00
Peter Bigot
0a07a29c74 boards: fix misleading size for partition
The length field for the MCUBOOT slot partitions in Nordic platforms
has always had an extra leading zero suggesting it's a 40-bit value,
being stored in a 32-bit field.  Remove the incorrect leading zero to
reduce misunderstanding of the field.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2020-05-13 21:25:29 +02:00
Martí Bolívar
6e8775ff84 devicetree: remove DT_HAS_NODE_STATUS_OKAY
Several reviewers agreed that DT_HAS_NODE_STATUS_OKAY(...) was an
undesirable API for the following reasons:

- it's inconsistent with the rest of the DT_NODE_HAS_FOO names
- DT_NODE_HAS_FOO_BAR_BAZ(node) was agreed upon as a shorthand
  for macros which are equivalent to
  DT_NODE_HAS_FOO(node) && DT_NODE_HAS_BAR(node) &&
- DT_NODE_HAS_BAZ(node), and DT_HAS_NODE_STATUS_OKAY is an odd duck
- DT_NODE_HAS_STATUS(..., okay) was viewed as more readable anyway
- it is seen as a somewhat aesthetically challenged name

Replace all users with DT_NODE_HAS_STATUS(..., okay), which is
semantically equivalent.

This is mostly done with sed, but a few remaining cases were done by
hand, along with whitespace, docs, and comment changes. These special
cases include the Nordic SOC static assert files.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2020-05-13 18:24:42 +02:00
Stephanos Ioannidis
769c2f5181 boards: atsamd21_xpro: Update documentation
This commit updates the board documentation to list all supported
on-chip peripherals.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-05-12 20:17:05 +02:00
Stephanos Ioannidis
7a946bb2e5 boards: atsamd21_xpro: Add supported test dependencies
This commit adds the supported test dependencies that were not listed
in the board yaml file.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-05-12 20:17:05 +02:00
Stephanos Ioannidis
66324ce97b boards: atsamd21_xpro: Fix DT conversion typo
This commit fixes the DT macro conversion typos introduced by the
commit 4d7d3a25c1.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-05-12 20:16:56 +02:00
Ioannis Glaropoulos
effac5b021 boards: arm: nrf: add non-secure SRAM memory information in DTS
When we build Zephyr as Secure image on nRF340 Application
MCU and nRF9160 SoC we would like to pass the information
about the reserved memory area allocated to the Non-Secure
images. The information may be needed to apply proper
security configuration. We add a "chosen" node in board .dts
file for this purpose.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-05-10 17:46:34 +02:00
Ioannis Glaropoulos
d5263f8e6c boards: arm: nrf9160_dk: clean up sram0_ns and sram0_bsd definitions
We do not want sram0_ns and sram0_bsd to represent physical
ram; these are just portions of sram reserved for the non-secure
image and the bsd library, respectively. Thus we can remove the
compatible property from these nodes. We also make use of
'reserved-memory' to represent the different memory partitions
to be used by the nrf9160 builds.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-05-10 17:46:34 +02:00
Håkon Øye Amundsen
562886115a boards: arm: nRF9160: avoid resizing sram0 for nRF9160_dk
sram0 node is needed to hold the size of the
total, physical SRAM available on nRF9160 SoC.
We use sram0_s to represent the Secure image
SRAM for nRF9160_dk builds.

Signed-off-by: Håkon Øye Amundsen <haakon.amundsen@nordicsemi.no>
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-05-10 17:46:34 +02:00
Ioannis Glaropoulos
e03db70906 boards: arm: nrf5340pdk: clean up sram0_shared definition
We do not want sram0_shared to represent physical ram;
this is just a portion of sram reserved for shared memory
between Application and Network MCU. Therfore, we remove
the 'mmio' compatible property and transform this node to
a reserved-memory node definition, inside which we define
the sram0_shared node along with its reg property.

In addition we correct the documentation about the shared
memory, stressing that it is placed after the image RAM of
nrf5340 Application MCU (not after the secure SRAM).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-05-10 17:46:34 +02:00
Ioannis Glaropoulos
28310ea12c boards: arm: nrf5340pdk: define sram0_image for image(s) RAM
We should not be using sram0 for image SRAM in nrf5340pdk.
sram0 represents the physical SRAM and that one includes the
shared memory between the two M33 CPUs on the SoC. We should
not be re-sizing sram0 to account for the shared RAM; instead
we would like to have sram0 representing the whole available
SRAM.

For that, we define a new memory node, sram0_image to
represent the 'image' SRAM that is available for Zephyr
on the board. sram0_image is the chosen image SRAM for
default builds, i.e. when TrustZone is ignored
(TRUSTED_EXECUTION_SECURE is not defined).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-05-10 17:46:34 +02:00
Kumar Gala
b19cf0bed3 drivers: eth: Get Manual MAC address from devicetree
Move from a Kconfig to select/initialize the MAC address to using the
"local-mac-address" property in devicetree.  If the property is set the
drivers will initialize the mac-address from the devicetree (unless the
mac address is all 0's).  The MAC address might get overwritten by
either a driver specific means or by the setting of
"zephyr,random-mac-address" in the devicetree.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-09 16:29:57 +02:00
Kumar Gala
1de61b4c42 drivers: eth: Replace driver specific RANDOM_MAC Kconfig with devicetree
Utilize the devicetree property "zephyr,random-mac-address" to determine
if a driver should use a random mac address and remove the associated
Kconfig options that enabled this feature.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-09 16:29:57 +02:00
Karl Zhang
679b437b75 boards: arm: musca_b1: Add TFM support
This commit adds support for TF-M to the MUSCA B1.

When the CONFIG_BUILD_WITH_TFM flag is set, a secure and
non-secure processing environment image pair will be
generated, with the Zephy application image running on
the non-secure side.

The secure and non-secure binary images will be signed
for use with the BL2 secure bootloader.

Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
2020-05-09 16:21:51 +02:00
Karl Zhang
f2ccd2b00a boards: arm: mps2_an521: Add TFM support
This commit adds support for TF-M to the MPS2 AN521.

When the CONFIG_BUILD_WITH_TFM flag is set, a secure and
non-secure processing environment image pair will be
generated, with the Zephyr application image running on
the non-secure side.

The secure and non-secure binary images will be signed
for use with the BL2 secure bootloader.

An additional .hex file is also generated to enable
running QEMU with the AN521 binaries, `tfm_qemu.hex`,
which can be executed with the `-t run` option with
west,  or `run` with ninja or make.

When configured for use with TF-M, the
`mps2_an521_nonsecure` board definition should be used.

Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
2020-05-09 16:21:51 +02:00
Karl Zhang
68ffc2d7cf arm: musca_b1: Extend memory space in nonsecure
This is for PSA arch test to run on Musca B1. The test cases need more
than 100k RAM.

Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
2020-05-09 16:21:51 +02:00
Karl Zhang
1a001cc94d arm: mps_an521_nonsecure: Add TFM BL2 support
PSA level 1 requires secure boot. TF-M BL2 is the official
secure boot loader. It needs a BL2_HEADER_SIZE offset.

Align nonsecure address with TF-M's NS slot while TF-M BL2 enabled.

Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
2020-05-09 16:21:51 +02:00
Parthiban Nallathambi
246402a2a2 board: arm: add support for infineon relax kit
Add support for relax kit with infineon xmc4500 SoC.

Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
2020-05-09 14:21:44 +02:00
Kumar Gala
c2135f8721 devicetree: DT_NODE_HAS_COMPAT_STATUS_OKAY -> DT_NODE_HAS_COMPAT_STATUS
Swap this out and make the status a parameter.
Leave a couple of cases of DT_NODE_HAS_COMPAT().

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2020-05-08 19:37:18 -05:00
Martí Bolívar
17b8667197 dts: clean up some redundant DT checks
These are redundantly checking a node's status twice.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-08 19:37:18 -05:00
Martí Bolívar
7e0eed9235 devicetree: allow access to all nodes
Usually, we want to operate only on "available" device
nodes ("available" means "status is okay and a matching binding is
found"), but that's not true in all cases.

Sometimes we want to operate on special nodes without matching
bindings, such as those describing memory.

To handle the distinction, change various additional devicetree APIs
making it clear that they operate only on available device nodes,
adjusting gen_defines and devicetree.h implementation details
accordingly:

- emit macros for all existing nodes in gen_defines.py, regardless
  of status or matching binding
- rename DT_NUM_INST to DT_NUM_INST_STATUS_OKAY
- rename DT_NODE_HAS_COMPAT to DT_NODE_HAS_COMPAT_STATUS_OKAY
- rename DT_INST_FOREACH to DT_INST_FOREACH_STATUS_OKAY
- rename DT_ANY_INST_ON_BUS to DT_ANY_INST_ON_BUS_STATUS_OKAY
- rewrite DT_HAS_NODE_STATUS_OKAY in terms of a new DT_NODE_HAS_STATUS
- resurrect DT_HAS_NODE in the form of DT_NODE_EXISTS
- remove DT_COMPAT_ON_BUS as a public API
- use the new default_prop_types edtlib parameter

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2020-05-08 19:37:18 -05:00
Tomasz Bursztyka
97326c0445 device: Fix structure attributes access
Since struct devconfig was merged earlier into struct device, let's fix
accessing config_info, name, ... attributes everywhere via:

grep -rlZ 'dev->config->' | xargs -0 sed -i 's/dev->config->/dev->/g'

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-05-08 23:07:44 +02:00
Ioannis Konstantelias
3f0797488c boards: arm: stm32_min_dev: Add ADC_1
Added ADC_1 support.

Signed-off-by: Ioannis Konstantelias <ikonstadel@gmail.com>
2020-05-08 15:56:33 -05:00
Frank Li
c8a528d322 boards: mm_swiftio: support west command
Modify burner for pyocd to support:
west flash
west debug
west debugserver

Signed-off-by: Frank Li <lgl88911@163.com>
2020-05-08 17:43:18 +02:00
Johann Fischer
14ef0a7ccb boards: reel_board: correct display resolution properties
Correct display resolution properties.

Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2020-05-08 15:11:10 +02:00
Mieszko Mierunski
f4a7255677 boards: nordic: Add support for nRF52833dk_nrf52820 board
This commit adds support for nRF52820 development on nRF52833DK.
Changes afffects:
 - Introduce files related to board description.
 - Add blank documentation file (for future update).
 - configuration files for build process.

Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
2020-05-08 15:00:41 +02:00
Sahaj Sarup
351f39f9cd board: arm: Add Support For 96Boards Aerocore2
Changes:

- Added all required board files in /boards/arm/96b_aerocore2
- Modified pinmux for stm32f4

Most of the changes in this PR is based on reverse-engineering of the
PCB layout and following commits in the PX4 firmware repository for
the same board. The manufacturer does not provide and or generate
schematics and pinout tables for this board.

This PR includes almost all of the interfaces connected to the STM32
MCU, the only thing not included is the J9 and J8 headers that connect
to a 96Boards baseboard.
These headers are not vital to the functionality of the Aerocore2.

Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
2020-05-08 07:33:43 -05:00