This patch moves the CONFIG_STACK_CANARIES check from architecture's
Makefile to the root Makefile since this option is kernel-related,
not architecture-related. This way we avoid replicating the same
CONFIG_STACK_CANARIES check in several Makefiles.
This patch also removes some blank lines from the Makefiles it touches.
Change-Id: I458f92fa6799526c608369d1e56579936bcb196e
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Changes the nanokernel stack API so that the timeout parameter must be
specified when invoking nano_isr_stack_pop(), nano_fiber_stack_pop(),
nano_task_stack_pop() and nano_stack_pop().
This obsoletes the following APIs:
nano_fiber_stack_pop_wait()
nano_task_stack_pop_wait()
nano_stack_pop_wait()
Note that even though the new API requires that the timeout parameter
be specified, there are currently only two acceptable values:
TICKS_NONE and TICKS_UNLIMITED
This nanokernel option does not support CONFIG_NANO_TIMEOUTS.
Change-Id: Ic7f16ee30c3534115ceffa19ef8591ecc5a79080
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Changes the nanokernel LIFO API so that the timeout parameter must be
specified when invoking nano_isr_lifo_get(), nano_fiber_lifo_get(),
nano_task_lifo_get() and nano_lifo_get().
This obsoletes the following APIs:
nano_fiber_lifo_get_wait()
nano_fiber_lifo_get_wait_timeout()
nano_task_lifo_get_wait()
nano_task_lifo_get_wait_timeout()
nano_lifo_get_wait()
nano_lifo_get_wait_timeout()
Change-Id: Ie9f93e46da42ea33c32544c02ab1d70b893cc198
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Changes the nanokernel semaphore API so that the timeout parameter must be
specified when invoking nano_isr_sem_take(), nano_fiber_sem_take(),
nano_task_sem_take() and nano_sem_take().
This obsoletes the following APIs:
nano_fiber_sem_take_wait()
nano_fiber_sem_take_wait_timeout()
nano_task_sem_take_wait()
nano_task_sem_take_wait_timeout()
nano_sem_take_wait()
nano_sem_take_wait_timeout()
Change-Id: If7a4bce1bd8ec8d6410d04f3c16ff1922ff0910e
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Changes the nanokernel FIFO API so that the timeout parameter must be
specified when invoking nano_isr_fifo_get(), nano_fiber_fifo_get(),
nano_task_fifo_get() and nano_fifo_get().
This obsoletes the following APIs:
nano_fiber_fifo_get_wait()
nano_fiber_fifo_get_wait_timeout()
nano_task_fifo_get_wait()
nano_task_fifo_get_wait_timeout()
nano_fifo_get_wait()
nano_fifo_get_wait_timeout()
Change-Id: Icbd2909292f1ced0bad8a70a075478536a141ef2
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
The UART on Quark SE and D2000 supports fractional clock divider.
It is used to limit frequency error for supported baud rates.
Change-Id: I1f39a95db09f4a5a4116edc700a10e4b9ecfa2bd
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The semantics of this value is that it allows for the use of IRQ lines
0 through CONFIG_NUM_IRQS - 1.
Change-Id: I0287da931b06253065f4fba076e9a949dcb3cf53
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Too many entries were being created in this table. It needs to
create indexes starting from 16 to CONFIG_NUM_IRQS - 1, since IRQS 0-15
are reserved for CPU exceptions and are not handled through this
mechanism.
generic_arc was still using the old C-based table which is
incompatible with the static IRQ implementation. An attempt was made
to move the SW IRQ table to arch/arc/core, but linker issues were
encountered and this will be done in another patch.
With CONFIG_NUM_IRQS set to 68 on Quark SE, inspection of binary
with objdump -x reveals that we are generating table entries:
00000000 g O .isr_irq16 00000000 _sw_isr_table
00000000 w O .gnu.linkonce.isr_irq16 00000000 _isr_irq16
00000000 w O .gnu.linkonce.isr_irq17 00000000 _isr_irq17
00000000 w O .gnu.linkonce.isr_irq18 00000000 _isr_irq18
...
00000000 w O .gnu.linkonce.isr_irq67 00000000 _isr_irq67
Which is exactly what we need.
Change-Id: I8ca1682128ae67e2a24642791b7ce31ebca759bf
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The ARC is an architecture that supports tickless idle in
nanokernel-only systems, and it thus must signal this to the build
system.
Change-Id: I96b0a4e8f78b2ea67d2f1b3384e94a32d8eb80e8
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Modified interrupt handling and idle code to enter and exit tickless
idle mode.
Change-Id: I3461ab6dba30003a4317027fc50a3ba07e830015
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
CONFIG_NUM_IRQS expresses the total number of available interrupt
lines in the system, and is used to generate a vector table.
On ARC, the vector table is assembled from two parts, _VectorTable
for the first 16 entries (reserved for CPU exceptions), and
_IrqVectorTable for the remainder. The code that creates _IrqVectorTable
was not taking this into consideration and was 16 entries too big.
Change-Id: I676c8534274de8782178f3773bc53a817b89481f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
On ARC the IRQ and exception vectors are just one big array of
function pointers placed at the very beginning of the binary in ROM.
Vectors 0-15 are for CPU exceptions, 16-255 for interrupts.
In Zephyr these have been logically split into an execption table
followed immediately by the IRQ table, specified in the ARC linker.cmd.
However, the exception vector table defined in Zephyr had only 14
entries so the IRQ table was misaligned by 8 bytes. This went undetected
for some time as in the default configuration every entry in the IRQ
table pointed to the common demux function _isr_enter().
This patch correctly ensures that the IRQ table begins at address
0x40000040 instead of 0x40000038 like it had been.
Change-Id: I3b548df0dcabeb9d986ecd6a41e593bd02e3bd73
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Causes problems for large values of CONFIG_NUM_IRQS.
Some inconsistencies have been noted in how CONFIG_NUM_IRQS is
used on these platforms, with bugs filed. This patch preserves
existing behavior and has been shown to generate the same number
of table entries for both arches using objdump.
Change-Id: I1d3ac5466978acb56e88a6dc3cbe7cc09431e94d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Let the SoC decide the number of the IRQs. Fixes a bug where
Quark SE gets the default instead of the declared value in the SoC
Kconfig.
Change-Id: I978c923fbe2a0737ace27ec951bc3a46e8976584
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
_IrqVectorTable was renamed to _irq_vector_table
Change-Id: I1488bebc7d8174c08f3ce2dc8bcace6ef567aad6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The current gpio_dw_initialize implementation masks the interruptions in the line
dw_write(base_addr, INTMASK, ~(0)) to assign api functions and initialize
interrupt vectors and handlers safely. Immediately after this, the driver expects
that gpio_dw_unmask_int(port) unmasks the interrupts. Without this patch that
implementation is empty for the quark se ss board.
Change-Id: Iac84c8807fcadad8c256c3fcaa4ff624b6337bf3
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Warning comes during compilation about missing prompt, this sets
the prompt for this SoC.
Change-Id: If8b422d6a870eb99c219ab872924875eb04fba0c
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Change terminology and use SoC instead of platform. An SoC provides
features and default configurations available with an SoC. A board
implements the SoC and adds more features and IP block specific to the
board to extend the SoC functionality such as sensors and debugging
features.
Change-Id: I15e8d78a6d4ecd5cfb3bc25ced9ba77e5ea1122f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This is a generic Atom configuration that can be inherited by boards
with Atom SoC like the minnowboard.
Change-Id: I06ab999062be7811d14755fd34440dee8f8b81ed
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
No need for the same SoC configuration with different names. Use IA32
as the "SoC" for qemu_x86 "boards".
Change-Id: Iee00538701c5ece14d0c3df637b0aaa54790f0e2
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Using LOAPIC Timer as default since it is the default for most target
X86 systems.
Change-Id: I71c9b307839ebcf46fb28e1b709089de600af83f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Previous it was renamed in favor of Qemu, now that we have board support
we move this to the original name and derive a qemu board out of the
platform.
Change-Id: Ia8769b27defa0a39503ecf2e6ec7fc6304b6ff49
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
We had one pinmux per platform with support for multiple boards.
This moves pinmuxing to boards as first step. Common functions that
are exposed by the API need to be moved to driver while keeping the
muxing configuration with the boards.
Change-Id: I2b4fabf663db98d644abcb5d51ba83adc6f74541
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The Galileo pinmux configuration and reboot code belong into
the board and not the SoC.
Change-Id: If862178569438a8901902088bd085275416c25ef
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Define boards based on platforms/SoCs and define them under boards/.
Also unify the naming of all platform, SoC and board files and use
platform.h for platforms and board.h for boards.
Change-Id: Icfeb96479ab5800aca98c80a79bdc3cecd645314
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The Galileo board is based on the X1000 SoC, so move galileo to
boards and create this SoC instead, inheriting all SoC related code
and configuration items.
Change-Id: I9b39f1b44644775ee48acae284b82bae7876fffb
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
According to the schematic, SPI1_M_ should be properly mapped out
on the pinmux. This should enable the SPI1_M functionality on the
Arduino / Genuino 101 board now.
Change-Id: Ided0147e7c2d835aa58fdc5860e7ca7f55d9e566
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Updating the pinmux to use a local static table for each pin select
option. Instead moving to a static series of function calls that
move the data from the RAM section to the ROM section.
This impacts only the Quark D2000 and the Quark SE chips. It does
not show any impact to the basic_minuteia tests.
All said we see small changes that amount to some values like:
test platform ram_%_change rom_%_change
======================== ============ ============ ============
microkernel:footprint-max quark_se-x86 -0.01 0.0
microkernel:footprint-reg quark_se-x86 -0.02 -0.01
microkernel:footprint-min quark_se-x86 -0.07 -0.02
nanokernel:footprint-max quark_se-x86 -0.02 -0.01
nanokernel:footprint-max quark_d2000 -0.01 -0.01
nanokernel:footprint-reg quark_se-x86 -0.03 -0.01
nanokernel:footprint-reg quark_d2000 -0.02 -0.02
nanokernel:footprint-min quark_se-x86 0.04 0.01
nanokernel:footprint-min quark_d2000 -0.07 -0.04
Change-Id: Ib69403eced60a8c784887dca9dd1954ce73a3e70
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Currently the Quark SE and Quark D2000 platform are only included
through the use of a compile fence one level higher in the Makefile.
Adding in a secondary compile fence to ensure if that check ever
changes, we won't be in trouble.
Change-Id: I5e39faffb4289f80901c0264a50a3e770db3388a
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Initial import of the pinmux configuration for the Quark_D2000 series
boards. Some minor tweaking of default values may be needed depending
upon expected usage scenarios.
Change-Id: I3b22219546a6534c7c695d0917a35f6f46b03cf1
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Adding support for the pinmux pins to set the pullup and input enable
registers. On the Arduino_101 board some pullup pins specifically can
be used to cause a reset for the Arduino sketch being run. Its use on
other pins is currently being investigated.
Change-Id: Id3293a4da84ea5bf553bf62ccb12782cb88503a5
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Naming convention should follow the IP_noun_verb concept. In this case,
renaming several functions from (for example) pinmux_set_pin to
pinmux_pin_set, while also correctly naming the function to their
specific tasks.
This is being done to make way for the ability to change the input
value, pullup value, and the slew as well.
Change-Id: Iec6f1723a48f80b66f3cea44df9bb6925972f6af
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Extending the public interface of the pinmux to allow the end user
to set a pin as an input/output and to pull up the value on
a specified pin.
Change-Id: Ie0a3b6432dd8c7d7a02f32e3d22049bdd99f1410
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
First step for adding the new board layer. Create configurations for the
various boards we support on x86 under boards with the new Kconfig variables
defining them.
The board selection is optional, that means you will be able to run
make menuconfig
and create your own .config and select any SoC.
Change-Id: If08e88e9675d13f0f0501ef6750b9424b15f5dc8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This variable (CONFIG_BOARD) will store the textual form of the
platform name and will be used for locating files related to the
board in the source tree.
Change-Id: I3c8a05ed428451a6785799a5492f0dd14682f208
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Allow usage of alternative drivers and do not hardcode drivers
to zephyr own implementation.
Change-Id: Ieb55b5dc88b3643f276b7c48facef7f1c1c42fa7
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The LCD display is an add-on, not a feature of the platform or the
board.
Set the defaults and remove the definition from Galileo Kconfig.
Change-Id: Ic319cd765d2dc1fe08cc65615680821fe9bc6a83
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
On Arduino 101, the sensor subsystem also has access to the two UARTs
on board. So this adds the necessary code to enable them to be used.
However, one needs to make sure only one core has access to one UART
at the same time.
Change-Id: I9f6c203916164d1b48559a9752fb1e4d879d7fa4
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
1. Need to unmask interrupts for the sensor subsystem.
2. The GPIO controllers need their clock enabled before they can
start sending out interrupts.
3. Setting up ISR on ARC requires usage of irq_connect().
Change-Id: I633b07292f11e5c5e768fc51fabb70769d407609
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The interrupt number for GPIO0/GPIO1 are 20 and 21 respectively.
The old value of 8 refers to the interrupts line on the x86 side
of GPIO controller.
Change-Id: I2e9e061d3506e27cb7b14e0431c3b6201a50aad4
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The pin mux for Galileo Gen2 isn't set properly to enable UART0_RXD input from
the Arduino headers. EXP1's pin0 OE_N needs to be set HIGH to make the IO0
buffer an Input.
Change-Id: I0167f11ff5ee87bd5afe17300807b1aa4ed17abf
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: David Antler <david.a.antler@intel.com>
The argument to 'lidt' is a chunk of memory with the base address
and limit of the IDT, and not the IDT itself. Horrible things
were happening when the IDT itself was being passed to this
instruction.
To be extra safe, disable interrupts while we modify the table
and subsequently reload it.
Change-Id: I9bf96f13a5f6e1be80d11bbfb9db3df1f2ed613a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The code to poke the system integration module to disable clock gating
for UARTs only works for UART0-3 since all the bits are in the same
register. However, clocks for UART4 and UART5 are controlled by
another register. This means that we have been writing to the wrong
bit for enabling UART4.
This patch fixes this issue, and moves the clock gating clock into
board initialization. The incorrect code has also been removed to
prevent accidental mis-use. The dev_data struct is no longer needed
for uart_k20, so that is removed as well.
Change-Id: I67845a417e43647bf0ffcbdbda34ce68fa887713
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
