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quark_se_ss: enable UART

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On Arduino 101, the sensor subsystem also has access to the two UARTs
on board. So this adds the necessary code to enable them to be used.
However, one needs to make sure only one core has access to one UART
at the same time.

Change-Id: I9f6c203916164d1b48559a9752fb1e4d879d7fa4
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung 2015-12-18 11:04:54 -08:00 • committed by Anas Nashif
commit cbd7dc65c4
3 changed files with 89 additions and 13 deletions
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59
arch/arc/platforms/quark_se_ss/Kconfig
View file

@ -89,6 +89,65 @@ config I2C_QUARK_SE_SS_1_DEFAULT_CFG
endif
if UART_NS16550
config UART_NS16550_PORT_0
def_bool y
if UART_NS16550_PORT_0
config UART_NS16550_PORT_0_NAME
default "UART_0"
config UART_NS16550_PORT_0_BASE_ADDR
default 0xB0002000
config UART_NS16550_PORT_0_IRQ
default 41
config UART_NS16550_PORT_0_IRQ_PRI
default 1
config UART_NS16550_PORT_0_BAUD_RATE
default 115200
config UART_NS16550_PORT_0_CLK_FREQ
default 32000000
config UART_NS16550_PORT_0_OPTIONS
default 0
endif # UART_NS16550_PORT_0
config UART_NS16550_PORT_1
def_bool y
if UART_NS16550_PORT_1
config UART_NS16550_PORT_1_NAME
default "UART_1"
config UART_NS16550_PORT_1_BASE_ADDR
default 0xB0002400
config UART_NS16550_PORT_1_IRQ
default 42
config UART_NS16550_PORT_1_IRQ_PRI
default 1
config UART_NS16550_PORT_1_BAUD_RATE
default 115200
config UART_NS16550_PORT_1_CLK_FREQ
default 32000000
config UART_NS16550_PORT_1_OPTIONS
default 0
endif # UART_NS16550_PORT_1
endif # UART_NS16550
if UART_CONSOLE
config UART_CONSOLE_ON_DEV_NAME
default "UART_1"
config UART_CONSOLE_IRQ
default 42
config UART_CONSOLE_IRQ_PRI
default 1
endif
config KERNEL_INIT_PRIORITY_DEFAULT
default 40

18
arch/arc/platforms/quark_se_ss/board.h
View file

@ -119,19 +119,6 @@
#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
#define CONFIG_ARCV2_TIMER1_INT_PRI 1
/*
* UART configuration settings
*
* This BSP only supports the nanokernel. Therefore:
* - only polled mode is supported (interrupt-driven mode is NOT supported); and
* - only the target console is supported.
*/
#define CONFIG_UART_CONSOLE_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ
#define CONFIG_UART_CONSOLE_IRQ IRQ_UART0_INTR
#define CONFIG_UART_CONSOLE_INT_PRI 0
#define UART_REG_ADDR_INTERVAL 4 /* for ns16550 driver */
#define INT_ENABLE_ARC ~(0x00000001 << 8)
#define INT_ENABLE_ARC_BIT_POS (8)
@ -166,6 +153,11 @@
#define GPIO_SS_1_INT_MASK 0x40C
#endif /* CONFIG_GPIO_DW */
#if defined(CONFIG_UART_NS16550)
#define UART_NS16550_0_INT_MASK 0x460
#define UART_NS16550_1_INT_MASK 0x464
#endif /* CONFIG_UART_NS16550 */
#endif /* !_ASMLANGUAGE */
#endif /* _BOARD__H_ */

25
arch/arc/platforms/quark_se_ss/platform_config.c
View file

@ -80,3 +80,28 @@ SYS_DEFINE_DEVICE(gpio_dw_ss_init, NULL, PRIMARY,
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
#endif /* CONFIG_GPIO_DW */
#ifdef CONFIG_UART_NS16550
static int uart_ns16550_init(struct device *dev)
{
ARG_UNUSED(dev);
#ifdef CONFIG_UART_NS16550_PORT_0
sys_clear_bit((SCSS_REGISTER_BASE + UART_NS16550_0_INT_MASK),
INT_ENABLE_ARC_BIT_POS);
#endif /* CONFIG_UART_NS16550_PORT_0 */
#ifdef CONFIG_UART_NS16550_PORT_1
sys_clear_bit((SCSS_REGISTER_BASE + UART_NS16550_1_INT_MASK),
INT_ENABLE_ARC_BIT_POS);
#endif /* CONFIG_UART_NS16550_PORT_1 */
return DEV_OK;
}
DECLARE_DEVICE_INIT_CONFIG(uart_ns16550_init, "", uart_ns16550_init, NULL);
SYS_DEFINE_DEVICE(uart_ns16550_init, NULL, PRIMARY,
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
#endif /* CONFIG_UART_NS16550 */