Refactors the i.MX RT600 SoC series to be more consistent with the i.MX
RT10xx SoC series by choosing a child node (external flash device) of
the FlexSPI bus for zephyr,flash.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
With this patch, zephyr can enable SMP directly. Otherwise
zephyr needs TB-R to provide psci function.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
Add strong definition z_arm64_el2_plat_init() and it is controlled
by CONFIG_SOC_FVP_AEMV8R_EL2_INIT.
VMPIDR_EL2 must be set manually on EL2. The purpose of VMPIDR_EL2 is
that holds the value of the Virtualization Multiprocessor ID and This
is the value returned by EL1 reads of MPIDR_EL1
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
This commit adds a new Kconfig option CLOCK_CONTROL_NPCX_EXTERNAL_SRC.
With this option enabled, the internal 32.768 KHz clock (LFCLK) is
generated by the on-chip Crystal Oscillator (XTOSC). Otherwise, the
LFCLK is generated by the Low-Frequency Clock Generator (LFCG).
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
NPCX power.c use LOG_MODULE_DECLARE(soc), but NPCX chip doesn't
register soc log module. This CL register soc log in soc.c to fix NPCX
build error for power management & log system.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Save ra to caller saved register is wrong because it might get
overwritten after another function is called, so we fix this.
Remove clear mip register operation. (it8xxx2 supports machine-mode
only, and MEIP bit of mip is read-only).
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
For esp32c3 related ROM located functions instead
of esp32c3_rom.
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
The _PrepC() function is the standard risc-v way
of zephyr entry point, so let it call the z_cstart instead
of calling this function directly.
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
replaces the plain memcpy to zero the bss with
the standard zephyr function that does this task.
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
Plus added implementation for esp32c3 SoC.
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
by adding the soc specific files such: soc initialization code,
linker scripts and support for esp32c3 devkitm
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
hal_espressif repository was updated from esp-idf v4.2
to esp-idf v4.3 to allow latest Espressif chips integration.
As a consequence, it added a few changes in drivers
and peripherals. To maintain bisectability, changes in this
PR cannot be split. Here are some details:
wifi: update linker script by adding libphy and new attributes.
spi: update some APIs and fixed missing wait_idle check
west.yml: esp32: update hal to new version
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Configures Segger RTT and SystemView data linker sections to DTCM by
default on i.MX RT SoCs if there is a zephyr,dtcm chosen node in
devicetree. This fixes a build warning in
samples/subsys/shell/shell_module for the mimxrt1170_evk_cm7 and
mimxrt1170_evk_cm4 platforms, which don't currently have a zephyr,dtcm
chosen node.
Note that there are runtime issues with Segger RTT and SystemView on
this board that need further debug, but submitting this patch now to
address nightly CI failures.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This fixes missing PPP iterable and adds all
common-rom.ld iterables.
ESP32 and esptool does not support more then 16 segments, which
blocks including common iterables section as is.
This partially reverts commit ad0bf94f77
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This adds power management support for the STM32WL series.
Suspend-to-idle is mapped to the three stop states (wake up from any
EXTI, including LPTIM), and soft-off can trigger either standby or
shutdown (wake up in reset).
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
The PS/2 module in npcx provides a hardware accelerator mechanism
including an 8-bit shift register, a state machine, and control logic
that handle both the incoming and outgoing data. The hardware
accelerator mechanism is shared by 4 PS/2 channels. To support it,
this CL separates the PS/2 driver into channel and controller drivers.
The controller driver is in charge of the PS/2 transaction. The channel
driver is in charge of the connection between the Zehpyr PS/2 API
interface and controller driver.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This commit adds the asserts symbol in Kconfig to enable/disable
asserts functionality for stm32 series. These would be used in
stm32cube hal & ll drivers.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
rv32m1_vega don't boot due to device init ordering and changes with the
device model. The soc code is looking for a device pointer for the
intmux. Change to using DEVICE_DT_GET here as that will ensure we get
a valid pointer and by the time we need to utilize the pointer the
intmux driver will have been initialized and thus the device pointer
will be ready.
Also set BUILD_OUTPUT_HEX since we utilize openocd to flash and west
flash is looking for a hex file for openocd targets.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This is a work in progress initial submission for the
Microchip MEC172x family SoC. This submission does
not contain all header files or power management.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
1. Added RT10xx and RT11xx configs
2. Added a new soc file for rt117x. There are clock differences
between the RT10xx and RT11xx series, hence the soc files
have been separated.
Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
Enable Instruction Cache
Warning: no flash driver yet available for STM32l5
But cache coherency management (cache invalidate)
will be rerquired when implementing flash driver.
ICAHE must be disabled for any flash write opeartion.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Enable Instruction cache accelerator for Cortex M4
first 1MB of Flash.
As per Reference Manual: no need for cache coherency management
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Convert the various device_get_binding() calls used to get the device
clock node to use DEVICE_DT_GET. The latter is processed at link time,
so it should be a bit more efficient.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add power management support to STM32L0 series.
The SoC have a single stop state that can be used with LPTIM as a system
timer, as well as a standby mode where the system resets on exit.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
NPCX WIMU CR_SIN is used to wake up soc from NPCX sleep power state.
The wake-up IRQ enabled when UART init. It causes the wake-up IRQ to
generate many extra interrupt events, which causes the system too busy
to handle other events. This PR moves the UART wake-up IRQ enabling
from UART init to npcx_power_enter_system_sleep() to avoid the
interrupt storm.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Set the defalut value of SYS_CLOCK_HW_CYCLES_PER_SEC Kconfig option
from the Device Tree. The `clock-frequency` property of the DT cpu@0
node is a single source of truth defining the CPU frequency. This is
the value used e.g. by all Atmel drivers.
For Atmel SAM family CPU clock is currently the only supported system
clock source. Ensure that kernel understanding of the hardware clock
frequency is the correct one.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Add flash driver for it8xxx2. The driver can implement
flash read, write and erase that will be mapped to the
ram section for executing.
TEST="flash write 0x80000 0x10 0x20 0x30 0x40 ..."
"flash read 0x80000 0x100"
"flash erase 0x80000 0x1000"
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
MPS2 AN521 is a dual (Cortex-M33) core where the two cores
have different capabilities. E.g CPU0 implements TrustZone-M,
while CPU1 implements the FPU. Therefore we introcude separate
Kconfig symbols for the two SoC variants, and use these to
select the different Cortex-M capabilities. We also update
the definitions of __MPU/FPU/SAU/DSP variant in soc.h to make
them get the value from the Kconfig settings, directly.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Adding support for beagleV Starlight board based on Starfive JH7100
SoC. It's a base support, no drivers other than uart has been tested.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
This CL introduces six properties, clock-frequency, core-prescaler,
apb1/2/3/4-prescaler in pcc (Power and Clock Controller) node to
configure clock settings. It also removed the original Kconfig options
used for the same purpose.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Rename OSC_CLK as OFMCLK to meet npcx datasheet. The Oscillator
Frequency Multiplier Clock (OFMCLK), which is derived from
High-Frequency Clock Generator (HFCG), is the source clock of cortex-m4
core and most of NPCX hardware modules.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
