Clean up unused psl functions in scfg.c, unused DT macros, unused psl DT
nodes and related yaml files. Currently, PSL pad configurations are made
by pinctrl mechanism. Please refer
https://issuetracker.google.com/234861079 for more detail.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Clean up unused pinmux function 'npcx_pinctrl_mux_configure()' and
related 'NPCX_DT_IO_ALT*' macro functions.
Please refer https://issuetracker.google.com/234861079 for more detail.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces how to configure PSL (Power Switch Logic) pads
properties such as input detection mode/polarity, pin-muxing and so
on via pinctrl mechanism. It includes:
1. Add two pinctrl properties and their enums for PSL input
detection configuration.
psl-in-mode:
- "level"
- "mode"
psl-in-pole:
- "low-falling"
- "high-rising"
2. Add macro functions to get PSL input detection and pin-muxing
configurations from 'pinmux', 'psl-offset' abd 'psl-polarity'
properties.
Here is an example to configure PSL_IN2 as the PSL detection input and
its mode and polarity.
/* A falling edge detection type for PSL_IN2 */
&psl_in2_gp00 {
psl-in-mode = "edge";
psl-in-pol = "low-falling";
};
A device will be introduced later which uses this pinctrl node to
configure PSL input detection settings and how to turn off VCC1 power
rail by PSL_OUT.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Following zephyr's style guideline, all if statements, including single
line statements shall have braces.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
When using CONFIG_NPCX_IMAGE_OUTPUT_HEX, set the hex_file
runners_yaml_props_target property, so that west flash will flash the
correct file.
Change the cmake flash rules to populate the hex_file value in the
runners.yaml file if either CONFIG_BUILD_OUTPUT_HEX is enabled or some
cmake file set the runners_yaml_props_target hex_file property.
Update the npcx9m6f_evb instructions now that the filename is implicit.
Signed-off-by: Jeremy Bettis <jbettis@google.com>
This commit adds a call to the Colorama initialisation function during
the module execution so that ANSI color sequences are properly
converted to the relevant Win32 API calls on the Windows.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Config pwm open-drain mode without enabling STORE_REG. This CL
collects all active PWM's base address and related index in an
array. Then, pinctrl driver configs its open-drain mode by
finding the corresponding 'channel' index.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL is the initial version for npcx pinctrl driver and introduces
pinctrl nodes for both IO-pads and peripheral devices for each npcx
series. Users can set pin configuration via these nodes in the board
layout DT file. It also wraps all configurations related to pin-muxing
in pinctrl_soc.h. Regarding the other pin properties, we will implement
them later.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Enabling an eSPI channel (r.g. Peripheral Channel, Virtual Wire Channel,
etc.) during an eSPI transaction might (with low probability) cause the
eSPI_SIF module to transition to a wrong state and therefore response
with FATAL_ERROR on an incoming transaction.
This CL workarounds this issue by clearing the bit 4 of NPCX eSPI
specific register#2.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
ADC threshold control register offset is provided by devicetree, this
change will add this property into `adc_npcx_config` structure and
update macro to access register accordingly. Driver behavior is not
meant to be impacted.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Linker files were not migrated with the new <zephyr/...> prefix. Note
that the conversion has been scripted, refer to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In order to bring consistency in-tree, migrate all soc code to the
new prefix <zephyr/...>. Note that the conversion has been scripted,
refer to zephyrproject-rtos#45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In npcx adc driver, we select 'Scan' (Multiple Channels Operation Mode)
mode by default. It means that selected channels in ADCCS will be
converted automatically. Then, read the measured data from CHNDAT
registers if EOCCEV (Event is set after all selected channels are
converted.) flag in ADCSTS is set.
But we enable the wrong interrupt type, INTECEN, during adc
initialization. Ec will send the interrupt after each channel in ADCCS
is converted. It has no harm to the current driver since the driver
reads all selected channels and turns off ADC converter only after
EOCCEV is set in ISR. But it does generate spurious interrupts.
This CL enables the correct interrupt type, INTECCEN, during adc
initialization. Ec only sends the interrupt after all of channels in
ADCCS are converted.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
According to Kconfig guidelines, boolean prompts must not start with
"Enable...". The following command has been used to automate the changes
in this patch:
sed -i "s/bool \"[Ee]nables\? \(\w\)/bool \"\U\1/g" **/Kconfig*
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Rename CONFIG_SOC_POWER_MANAGEMENT_TRACE to CONFIG_NPCX_PM_TRACE so that
it is clear that it's a NPCX specific option.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Remove a redundant symbol that was used as a proxy to enable CONFIG_PM
and CONFIG_PM_DEVICE. If an application needs to enable PM, it should
just enable PM subsystem Kconfig options. Furthermore, there's no clue
"SOC_POWER_MANAGEMENT" is a NPCX specific option.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Aligning with the rest of PM API, replace pm_power_state_exit_post_ops
with pm_state_exit_post_ops.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Do not include psl-in related code is the status of vsby-psl-in-list is
disabled, which can help reduce a little RAM/flash size.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
The SoC Kconfig.defconfig.series files re-defined multiple Kconfig help
entries. The help for such symbols should only be present in places
where symbol is actually defined, not where the defaults are changed.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The reg_def.h was not self-contained: it uses DT API but doesn't
include <devicetree.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Many ARM SoCs included <devicetree.h> likely due to:
1. nvic.h not being self-contained
2. As a result of copy-paste
Some RISC-V SoCs had the same problem, in this case likely due to
copy-paste from ARM. The <devicetree.h> header has been removed using
the following command:
sed -i ':a;N;$!ba;s/#include <devicetree\.h>\n//g' soc/**/soc.h
soc.h files that make a legitimate usage of the API have not been
changed.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Almost none of the soc_*.h headers were self-contained. This patch adds
all necessary includes to improve the situation.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
NPCX7/9 has a different ADC register structure. NPCX7 has 3 threshold
detectors from offset 0x14 & has 10 input channels. NPCX9 has 6
threshold detectors from offset 0x60 & has 12 input channels.
This commit fixes the NPCX ADC register structure.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
In this commit, the driver sets the PM constraint to prevent the system
from entering the suspend state for a CONFIG_UART_CONSOLE_INPUT_EXPIRED
period when data come in. The constraint releases after the
CONFIG_UART_CONSOLE_INPUT_EXPIRED time expires, .
With this change, the PM policy doesn't have to check the timestamp
by calling npcx_power_console_is_in_use() explictly. So the related
npcx_power_console_is_in_use*() functions can be removed.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
The device PM callback needs to be used only to suspend/resume devices.
If the system cannot be suspended because UART is in a particular
state, the pm_constraint_set/release API should be used. For NPCX UART,
the chip can't enter low power idle state until UART completes the data
transmission.
This commit changes NPCX UART to use pm_constraint_set/release & fixes
UART lost data from low power idle.
Fix#40621
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
The FIU/UMA module in the NPCX chip provides an dedicated SPI interface
to access the SPI flash. This commit adds the driver support for it.
With this commit, the application can call the flash APIs
(via spi_nor.c) to access the internal flash of NPCX EC chips.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I32bbf09f6e014b728ff8e4692e48151ae759e188
The parameters to FIELD() should be the position and size of each bit
field. Correct the size of IOMODE and MAXFREQ. Otherwise, the MAXFREQ
field is overwritten by the IOMODE update during espi_npcx_configure().
Signed-off-by: Diana Zigterman <dzigterman@google.com>
The host interface type (eSPI/SHI) is selected via HIF_TYP_SEL field in
DEVCNT register. This commit adds a function to set it.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
The booter (bootloader) behavior may be different in different NPCX
chip series. One example is that the booter sets host interface type in
NPCX7 series but leave the firmware to set it in NPCX9 series.
This commit adds a new DT node to record variants in its properties.
NPCX drivers can understand if they need to configure the related
setting by checking the node's properties.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
The KBC/ACPI event data is 4-byte in width and composed of
event/data/type fields. However, the field position is defined by each
chip vendor via macro and not unified in the current implementation.
The commit uses the structure bit field to define and unify the field
position. It helps the application access it with a common approach.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This CL replaces offset macros of pmc 'multi-registers' such as
PWDWN_CTLn with internal inline functions for better readability.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL replaces offset macros of scfg 'multi-registers' such as DEVALTn
and LV_GPIO_CTLn with internal inline functions for better readability.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Define SoC hooks as weak symbols so this way applications can
overwritten them defining strong symbols.
The problem is that currently SoCs are defining these interfaces as
strong symbol inhibiting the possibility of applications bring their
own implementation.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add the missing includes to make the header more portable. It currently
requires other headers to be included before it.
Signed-off-by: Yuval Peress <peress@chromium.org>
This commit includes the following:
1. Add symbol for choice option. So we can override the default value
by an earlier definition.
2. NPCX9 doesn't support 33MHz SPI clock in the header. So disable the
option for NPCX9.
3. NPCX9 support 512K flash. Change default to 512k for NPCX9.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
To be able to get a tokenize DT string without the quotes. Deprecate
also DT_ENUM_TOKEN and DT_ENUM_UPPER_TOKEN.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit adds a new Kconfig option CLOCK_CONTROL_NPCX_EXTERNAL_SRC.
With this option enabled, the internal 32.768 KHz clock (LFCLK) is
generated by the on-chip Crystal Oscillator (XTOSC). Otherwise, the
LFCLK is generated by the Low-Frequency Clock Generator (LFCG).
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
NPCX power.c use LOG_MODULE_DECLARE(soc), but NPCX chip doesn't
register soc log module. This CL register soc log in soc.c to fix NPCX
build error for power management & log system.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
The PS/2 module in npcx provides a hardware accelerator mechanism
including an 8-bit shift register, a state machine, and control logic
that handle both the incoming and outgoing data. The hardware
accelerator mechanism is shared by 4 PS/2 channels. To support it,
this CL separates the PS/2 driver into channel and controller drivers.
The controller driver is in charge of the PS/2 transaction. The channel
driver is in charge of the connection between the Zehpyr PS/2 API
interface and controller driver.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Convert the various device_get_binding() calls used to get the device
clock node to use DEVICE_DT_GET. The latter is processed at link time,
so it should be a bit more efficient.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
NPCX WIMU CR_SIN is used to wake up soc from NPCX sleep power state.
The wake-up IRQ enabled when UART init. It causes the wake-up IRQ to
generate many extra interrupt events, which causes the system too busy
to handle other events. This PR moves the UART wake-up IRQ enabling
from UART init to npcx_power_enter_system_sleep() to avoid the
interrupt storm.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
This CL introduces six properties, clock-frequency, core-prescaler,
apb1/2/3/4-prescaler in pcc (Power and Clock Controller) node to
configure clock settings. It also removed the original Kconfig options
used for the same purpose.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Rename OSC_CLK as OFMCLK to meet npcx datasheet. The Oscillator
Frequency Multiplier Clock (OFMCLK), which is derived from
High-Frequency Clock Generator (HFCG), is the source clock of cortex-m4
core and most of NPCX hardware modules.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
To support west OpenOCD path image flashing, this generates an npcx hex
image from the npcx BIN image. Moreover, this also changes the name of
npcx output image by CONFIG_KERNEL_BIN_NAME.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
NPCX7 variants allocate code RAM either at 0x10070000 or 0x10090000.
The MPU requires addresses and region sizes to be aligned, so the
generic cortex_m/arm_mpu_regions.c results in an ineffective setup with
the addresses above.
This adds a custom mpu_regions setup for the npcx7, which covers both
available sizes, resulting in these two possible setups:
- 192kB devices
Code ram: 0x10090000 to 0x100bffff
MPU region: 0x10080000 to 0x100bffff (256k)
- 320kB devices
Code ram: 0x10070000 to 0x100bffff
MPU region 0: 0x10040000 to 0x1007ffff (256k)
MPU region 1: 0x10080000 to 0x100bffff (256k)
In both cases MPU data RAM setting is from 0x200c0000 to 0x200cffff,
matching the generic Cortex-m setup.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This CL adds the support for npcx9m3f and npcx9m6f chips in ecst.py
script which generates the NPCX firmware header.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL replaces macros for miwu multi-registers' offset with internal
inline functions. This CL also uses soc series definitions to
distinguish the layout of miwu multi-registers between different npcx
series.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL adds the soc drivers for npcx9 series. There are two soc part
numbers, npcx9m3f and npcx9m6f, are introduced. We also move soc family
configurations from /nuvoton_npcx/npcx7/Kconfig.soc to
nuvoton_npcx/Kconfig.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
In npcx9, the number of pinmux registers (DEVALTx) is more than 16. We
need to extend the "group" member in the struct npcx_ALT to configure
the pinmux settings in npcx9.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL moves power policy source file for all npcx series to common
folder. It also abstracts the sources for checking register structures
to common/registers.c to avoid the duplicated sources in the later npcx
series.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL replaces series-prefix "npcx7-" with family-"npcx-" for npcx dts
nodes such as 'espi-vws-map' and 'miwus-int-map'. Since we plan to
introduce the npcx9 and later series, adding a new node such as
npcx9-espi-vws-map for each series is more complicated and not
necessary.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
NPCX series ROM code changes the chip basic setting by firmware binary
header for loading the firmware from flash to RAM. Add the following to
improve the ec firmware header setting:
- Move the ECST which generates the firmware binary header to NPCX
common folder. All the following NPCX series chips can use this.
- Add ecst setting option in Kconfig.
Signed-off-by: Yuval Peress <peress@chromium.org>
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
This CL limits the compiler to consider the eSPI/LPC host wake-up
functions, such as npcx_host_disable_access_interrupt and
npcx_host_disable_access_interrupt, only if eSPI bus module is selected.
Otherwise, we will encounter compiler errors if the communication
between host and ec is via SPI, not eSPI/LPC bus.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
NPCX clock has some limitations about the frequency range &
synchronization between core clock & other clocks. Add build assert to
check whether NPCX clock setting correct. This also fixed soc_clock.h
to consist with datasheet.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
During configuring the low-voltage power supply of IO pads, the npcx
GPIO driver needs to set the related PORTx_OUT_TYPE bit to 1, i.e.
select to 'Open Drain IO type', also. This CL provides a mechanism that
configuring these bits via 'def-lvol-io-list' node automatically in case
the flag of gpios that have been configured to low-voltage power supply
doesn't contain GPIO_OPEN_DRAIN.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The NPCX power management code gets a compile error if CONFIG_PM is
enabled but CONFIG_ARM_MPU is disabled.
Signed-off-by: Keith Short <keithshort@google.com>
It was found that npcx7 series' GPIOs which support low-voltage power
supply, there is an excessive power consumption if they are selected to
low-voltage mode and their input voltage is 1.8V.
To avoid this excessive power consumption, this CL suspends the
connection between IO pads and hardware instances before ec enters deep
sleep mode. Then restore them after waking up.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL adds a override mechanism for pwm module's input clock source
assignment. If the 'clock-bus' property exists, the NPCX_DT_PROP_ENUM_OR
macro function will return an enum upper token value. Otherwise, it
expands to default value in 'clocks' property.
For example, if the users want to select LFCLK as pwm0's input clock,
ths node can be overridden by adding 'clock-bus' property with an enum
string, "NPCX_CLOCK_BUS_LFCLK".
&pwm0 {
status = "okay";
clock-bus = "NPCX_CLOCK_BUS_LFCLK";
};
Signed-off-by: Keith Short <keithshort@google.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
NPCX host access IRQ enables before entering deep sleep. The pending
bit lets chip wake up from sleep immediately. Clear host access IRQ
pending bit before enabling.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Fixed the name of nodes in in espi-vw, miwu-wui, and miwu-int
device-tree node. This CL fixed missing nodes in CL d3a94fa8ab.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL adds support for console expired mechanism. It implements the
notification to power management module that the module for console is
in use. If the interval that module doesn't receive any input message
exceeds CONFIG_SOC_POWER_CONSOLE_EXPIRED_TIMEOUT, the power management
module is allowed to enter deep sleep mode. This mechanism gives a
window in which the users can organize console input.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Fixed the name of nodes in device-tree files by following rules:
If object is 'phandles', use underscores for object name.
If not, such as 'node' or 'property', use hyphens for object name.
This CL also applies normal style for all nodes in npcx device-tree
files.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The Write Protect pin of the internal SPI flash can be controlled by
WP_IF bit in DEV_CTL4 register. Add functions to set/get the status of
WP pin.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I8a0ce131f006f919a3b38a65722d0d312314ff0a
The compiler shows the array bounds warning message for some boards
which don't set the PSL function.
Change npcx_pinctrl_psl_input_asserted() input parameter from int to
uint32_t to fix it.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
This CL introduces the implementation of configurating PSL input pads
and setting PSL_OUT to inactive level for ultra-low power consumption.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces the Power Switch Logic (PSL) pads which detect the
wake-up events and turn on/off core power supply (VCC1) for ultra-low
-power consumption in npcx device-tree file.
By adding PSL input-pad objects, psl_in1, psl_in2, and so on, into
'psl-in-pads' property and configuring their 'flag' properties, the
related driver will configure them via soc specific functions later.
For example, if PSL input 1 pad that is plan to detect a 'falling edge'
event, this property should be:
vsby-psl-in-list {
psl-in-pads = <&psl_in1>;
};
And the flag property in psl_in1 should change to
&psl_in1 {
flag = <NPCX_PSL_FALLING_EDGE>;
};
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
In NPCX chips, System Configuration module can configure not only
pinctrl but also misc. functionality such as glue and flash write
protection. This change moves the scfg driver from the pinctrl folder
to soc/arm/nuvoton_npcx/common and renames it to avoid confusion.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This CL solves an interrupt storm caused by plenty of host access
messages when system is in S0. It only turns on the host access
interrupt before ec enters sleep and turns it off after leaving
sleep.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL prevents changing data content in the write function of host
interface by declaring it as constant pointer.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add the declaration and check of debug interface register.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: Ib8ecd53f1d6139613f39243aee83bdd75a30f5be
In NPCX7 series, it contains two tachometer (TACH) modules that contains
two Independent timers (counter 1 and 2). They are used to capture a
counter value when an event is detected via the external pads (TA or
TB).
The CL also includes:
— Add npcx tachometer device tree declarations.
— Zephyr sensor api implementation for tachometer.
— Enable "tach1" device in npcx7m6fb.dts for testing.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Since the uart device clock will be stopped after ec entered sleep or
deep sleep state and restore its clock automatically, there is no need
to implement code for suspending and resuming devices manually.
The driver still needs to check the current status of uart device when
it wants to change its power state to LOW or SUSPEND power state. It is
crucial to forbid ec enters sleep or deep sleep state when uart device
is busy with transmitting data. Or we will observe broken characters on
the uart console.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces power management driver that improves the efficiency
of ec operation by adjusting the chip’s power consumption to the level
of activity required by the application in npcx series.
The following list summarizes the main properties of the various chip
power states. Please refer the power.c file for more detail.
Main power states in npcx series include:
- Active: Core, RAM and modules operate at the clocks generated by PLL.
- Idle: Enter this state when the Core executes WFI or WFE instruction.
- Sleep: clock is stopped for most of modules but PLL is enabled.
- Deep Sleep: As Sleep mode but PLL is disabled.
- Standby: All power rails are turned off besides standby and battery
power rails.
And this CL implements one power state, PM_STATE_SUSPEND_TO_IDLE, with
two sub-states for Zephyr power management system.
Sub-state 0 - "Deep Sleep" mode with “Instant” wake-up if residency
time is greater or equal to 1 ms
Sub-state 1 - "Deep Sleep" mode with "Standard" wake-up if residency
time is greater or equal to 201 ms
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces a kernel device driver implemented by the internal
64/32-bit timers in Nuvoton NPCX series. Via these two kinds of timer,
the driver provides an standard "system clock driver" interface.
It includes:
- A system timer based on an ITIM64 (Internal 64-bit timer) instance,
clocked by APB2 which freq is CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
- Its prescaler is set to 1 and provide the kernel cycles reading
without handling overflow mechanism.
- A event timer based on an ITIM32 (Internal 32-bit timer) instance,
clocked by LCLK which frequency is 32KHz and still activated when ec
entered "idle/deep idle" power state for better power consumption.
- Its prescaler is set to 1 and provide timeout event mechansim.
- Compensate system timer which clock is gating for better power
consumption after ec left"idle/deep idle" power state.
This CL passed starve, timer_api, and timer_monotonic test suites.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The NPCX clock driver was already using devicetree, just need to make a
small tweak to use DEVICE_DT_INST_DEFINE and update NPCX_CLK_CTRL_NAME
to match the label for the "nuvoton,npcx-pcc" clock controller.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In this CL, npcx_miwu_interrupt_configure is no longer responsible for
turning the interrupt off. Although the default state of WK_EN is
disabled, the users still have the chance to configure them when WK_EN
is enabled via npcx_miwu_irq_enable(). Hence, this CL also ensures that
WK_EN is disabled before configuring them.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL added more additional details for KBC (Keyboard and Mouse
Controller) bus in espi_event structure. It helps the application to
handle different 8042 events in the callback function.
The format of event data for KBC 8042 protocol is:
[23:16] - 8042 event type: 1: Input buf full, 2: Output buf empty.
[15:8] - 8042 data: 8-bit 8042 data.
[0:7] - 8042 protocol type: 0: data type, 1: command type.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Part of GPIO pads in npcx series support low-voltage (1.8V) level
detection. In order to introduce this feature, this CL adds a new
NPCX-specific controller property, lvol_io_pads, in devicetree file.
For example, here is devicetree fragment which turn on low-voltage
support of i2c1_0 port.
/ {
def_lvol_io_list {
compatible = "nuvoton,npcx-lvolctrl-def";
lvol_io_pads = <&lvol_io90 /* I2C1_SCL0 1.8V support */
&lvol_io87>; /* I2C1_SDA0 1,8V support */
};
};
Then these pads will turn on 1.8V level detection during initialization.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
In npcx7 series, the Timer and Watchdog module (TWD) generates the
clocks and interrupts used for timing periodic functions in the system.
It also provides watchdog reset signal generation in response to a
failure detection.
The CL also includes:
— Add npcx watchdog device tree declarations.
— Zephyr watchdog api implementation.
— Add Watchdog definitions for npcx7 series in
tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c for
supporting test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
The NPCX SMB modules provides full support for a two-wire SMBus/I2C
synchronous serial interface. Each SMBus/I2C interface is a two-wire
serial interface that is compatible with both Intel SMBus and Philips
I2C physical layer. There are 8 SMBus modules and 10 buses in NPCX7
series.
In NPCX7 series, the SMB5 and SMB6 modules contain a two-way switch to
support two separate SMBus/I2C buses (ports) with one SMB module
(controller) Please refer Section 4.7.2 in the datasheet. In order to
support it, this CL seperates the i2c driver into port and controller
drivers. The controller driver is in charge of i2c module operations
and internal state machine. The port driver is in charge of pin-mux
and connection between Zehpyr i2c api interface and controller driver.
All of modules have separate 32-byte transmit FIFO and 32-byte receive
FIFO buffers. These FIFO buffers reduce firmware overhead during long
SMBus transactions by allowing the Core to write or read more than one
data byte at a time to/from the SMB module.
The CL also includes:
— Add npcx i2c port/controller device tree declarations.
— Zephyr i2c api implementation.
— Add "i2c-0" aliases in npcx7m6fb.dts for i2c test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
The System Glue module includes the three major functions:
— Power Switch Logic (PSL)
— SMBus multi-bus, wake-up support
— Simple Debug Port (SDP)
In NPCX7 series, the SMB5 and SMB6 modules contain a two-way switch to
support two separate SMBus/I2C buses (ports) with one SMB module
(controller). Since a single SMB module is able to serve only one
SMBus/I2C bus at a time, SMB_SEL registerin Glue module is used to
control theconnection of I2Cn_0 and I2Cn_1 interface pins to the SMBn
module (where n is 5, 6).
This CL provides a soc specific pin-control function called
"soc_pinctrl_i2c_port_sel" to switch buses (port) of the same SMB module
(controller). It will be used in the following i2c driver.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This CL introduces two kinds of op codes for espi_api_lpc_read_request
and espi_api_lpc_write_request Zephyr espi api functions.
One is for supporting ACPI and shared memory region to access ACPI data.
The other is customized for certain platforms such as Chromebook and so
on.
This CL also introduced the following configurations to add the
flexibility of these settings.
1. ESPI_PERIPHERAL_ACPI_SHM_REGION_PORT_NUM:
Host I/O peripheral port number for shared memory region. The default
value is default 0x0900
2. ESPI_NPCX_PERIPHERAL_ACPI_SHD_MEM_SIZE:
Host I/O peripheral port size for shared memory in npcx series.
Please notice the valid value in npcx ec series for this option is
8/16/32/64/128/256/512/1024/2048/4096 bytes. The default value is 256
bytes.
This CL also turn off hardware-wire feature which generates VW events
that connected to hardware signals such as SMI and SCI. We will set
VW output events directly via espi_api_send_vwire() api function.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL replaces all DT_ prefix with NPCX_DT_ for all macros used
for providing npcx device information in soc_dt.h It avoided the
ambiguity with the DT_ prefix for system DT macros/defines.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
As best any of us could figure this was intended to indicate that the
macro is a function to be passed to UTIL_LISTIFY.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
NPCX7 includes a 10-bit resolution Analog-to-Digital Converter (ADC). Up
to 10 voltage inputs can be measured and a internal voltage reference
(VREF), 2.816V (typical) is used for measurement. It can be triggered
automatically in Autoscan mode. Each input channel is assigned a
separate result register, which is updated at the end of the conversion.
The CL also includes:
— Add npcx adc device tree declarations.
— Zephyr adc api implementation.
— Add adc definitions of npcx7 in
tests/drivers/adc/adc_api/src/test_adc.c for supporting test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
In npcx7 series, there're 8 Pulse Width Modulator (PWM) modules and each
one support generating a single 16-bit PWM output. A 16-bit clock
prescaler (PRSCn) and a 16-bit counter (CTRn) determine the cycle time,
the minimal possible pulse width, and the duty-cycle steps.
Beside introducing pwm driver for Nuvoton NPCX series, this CL also
includes:
1. Add PWM device tree declarations.
2. Zephyr PWM api implementation.
3. Add aliases in npcx7m6fb_evb board device tree file for supporting
samples/basic/blinky_pwm application and pwm test suites
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Change default pinmux of functional pads to GPIOs. It includes:
1. PIN96.A0.A2.A4 - If internal flash is supported
2. PIND2.00 - Default PSL inputs
3. PIN31.30.27.26.25.24.23.22 - Keyboard inputs
4. PIN21.20.17.16.15.14.13.12.11.10.07.06.05.04.82.83.03.B1 - Keyboard
outputs
5. Add description for soc_pinctrl_mux_configure() usage.
It also fixed the typo and inverse mistakes in npcx7-alts-map.dtsi.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This CL adds more comments for each macro functions used for device tree
file for better explanations. It also changes all hex values in soc.c to
lower case.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
