Duplicate const specifier, it should be the pointed data that is const.
Jira: ZEP-1723
Change-Id: I194abb0fc9ad564c6d53e4727bd63c8099d4eb2e
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This implementation of _tsc_read returns a 64-bit value that
is derived from the 64-bit tick count multiplied by hwcycles per tick,
and then it adds the current value from the 32-bit timer.
This produces a 64-bit time. There is a bunch of math here, which
could be avoided if the CPU is built with Real-Time-Clock option.
EM Starter Kit SOCs don't have this. I don't think Arduino 101 does
either.
See ZEP-1559
Change-Id: I9f846d170246556ac40fe2f45809e457c6375d8c
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
The interrupts would be placed at incorrect offsets on systems where
some interrupt vectors are reserved for exceptions, such as ARC.
Change-Id: I5b1f00eb9e8aecb84ae66e3d0461a734ffb5fbe6
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Adds crypto API interface for interaction between applications
and crypto drivers. Encryption/Decryption APIs are defined
here.
Jira: ZEP-328
Change-Id: I1a534ae2a69c7e1c416fa78a2822c37040b225f6
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
Makes it cleared that zoap_update_from_block() doesn't modify the
packet.
Change-Id: I35429b153370c50eb5ae9c914b47a3144faf2f04
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Now types and functions have better explanations of their usage and
parameters associated.
Jira: ZEP-1657
Change-Id: I146688324080ac3cf0876f1db3c92c9514e1303d
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Its current placement was splitting the vector table in half.
Move to rodata, a better place for it. There's no requirement for
it to be in the text section.
Change-Id: I67724b2a26a9cb62c2ccd473cb54c53e4f74dc32
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The BSS section needs to use AT> in XIP systems otherwise the LMA
addresses in the ELF binary are wrong, leading to issues if we
try to manipulate the binary with objcopy. The GROUP_DATA_LINK_IN
macro does the right thing here.
This was already done on other arches but ARC was missed.
Change-Id: I93748e919e0b68c1ff2dfb4b85b7064a8d980f3a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
XCC does neither define __BYTE_ORDER__ nor __ORDER_LITTLE/BIG_ENDIAN__ macros.
This resulted in field preempt of thread.base not correctly built from other
union fields prio and sched_locked, which caused wrong scheduling.
Change-Id: I8566ef4a5cf555906c012c4adc488f9afb26c053
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
1) Fatal errors now all go through _SysFatalErrorHandler. When the
simulator is used, only the death of 'essential' threads will result
in the simulator exiting; some test cases that test exceptions may
actually expect a thread to terminate abnormally.
2) The human readability of the exception errors is improved.
Change-Id: I77f57ea0eae15b0c55237681b959cd21e3fe8c1c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The XCC compiler freaks out if a section name passed via
__attribute__((section)) has parenthesis in it. This happens in the
case of _MDEF_THREAD_DEFINE.
It turns out the whole mechanism of placing kernel objects in completely
unique sections is totally unnecessary. This patch is a workaround until
we can clean this up.
Change-Id: I12c88a1b8f5b27bec27d608614356c1b479c0a8c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The old syntax is not accepted by some compilers including XCC.
Change-Id: Id90849a2159652ec225dd2c50d2dc2ddc22a3e08
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
find_msb_set logic was wrong. find_lsb_set() is now an inline function.
Change-Id: I2c19540907723589298b2f6af2ce1d68704bf1d7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Master branch changed requirements for license headers while this
branch has been in development.
Change-Id: I9bce16ff275057a4bb664019628fc9b6de7aef7c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The current I2C API provides inline functions to access 1 byte
register addresses. This commit adds a set of I2C inline functions
as shortcuts to handle:
- 16 bit register addressing. A family of functions that allows to
handle 2 byte register addressing and can receive the address
parameter as a simple variable. This allows a developer to handle
the address as a C constant or macro.
- Multiple byte addressing. A family of functions to access
registers with a configurable register address size. This family
of functions handle register addressing of any size but receives
the address parameter as a byte array.
Change-Id: Id369ab9eaad7eea807554371d3a520f67dc2e0f2
Signed-off-by: Juan Manuel Cruz Alcaraz <juan.m.cruz.alcaraz@intel.com>
In order for OpenOCD to have a high-level view of an RTOS, it uses the
GDB protocol to obtain symbols from the system.
The GDB protocol, however, does not allow obtaining fields from
structures directly, and hardcoding offsets is not only brittle (due to
possibly different architectures or changes in the code), it's also
infeasible considering Zephyr is highly-configurable and parts of key
structs can be compiled in or out.
Export an array with offsets for these key structs. Also add a version
element in that array to allow changes in those structs.
Change-Id: I83bcfa0a7bd57d85582e5ec6efe70e1cceb1fc51
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
This replaces the hard-coded vector table, as well as the
software ISR table created by the linker. Now both are generated
in build via script.
Issue: ZEP-1038, ZEP-1165
Change-Id: Ie6faaf8f7ea3a7a25ecb542f6cf7740836ad7da3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is a new mechanism for generating interrupt tables which will
be useful on many architectures. It replaces the old linker-based
mechanism for creating these tables and has a couple advantages:
1) It is now possible to use enums as the IRQ line argument to
IRQ_CONNECT(), which should ease CMSIS integration.
2) The vector table itself is now generated, which lets us place
interrupts directly into the vector table without having to
hard-code them. This is a feature we have long enjoyed on x86
and will enable 'direct' interrupts.
3) More code is common, requiring less arch-specific code to
support.
This patch introduces the common code for this mechanism. Follow-up
patches will enable it on various arches.
Issue: ZEP-1038, ZEP-1165
Change-Id: I9acd6e0de8b438fa9293f2e00563628f7510168a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These were reported by ISSM compiler.
Jira: ZEP-1179
Change-Id: I10d04c2949ad2a390d4c1159d2342c73108a58b7
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
This patch moves the include for the generated_dts_board.h inside of
the include/arch/arm/arch.h file. This was done to simplify the
includes required for files. Only two files will include the dts
generated include file directly: arch.h and the linker.ld
Change-Id: I2614f4fd4eeed2ab635a3264d7dac8b83f97b760
Signed-off-by: Andy Gross <andy.gross@linaro.org>
We now use CMSIS for ARM Cortex-M SoCs so we can remove the last bits of
scs and scb.
Jira: ZEP-1568
Change-Id: I0c7c45b0321dc402ed594e9faffb5109922edcf0
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
_SCS_CPACR_CP10_Pos and _SCS_CPACR_CP11_Pos come from scs.h, we have
versions defined in cmsis.h we should be using instead.
Change-Id: Icd8db02000bbc9ef8b2cf89d359e008f62a7d5e9
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Coverted:
_ScbMemFaultMmfarReset
_ScbBusFaultBfarReset
_ScbUsageFaultAllFaultsReset
To use direct CMSIS register access.
Also removed scb.h and references as there is no longer any code in it.
Jira: ZEP-1568
Change-Id: I469f6af39d1bd41db712454b0b3e5ab331979033
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The previous code incorrectly used the value 0xfe to clear the mem and
bus faults. It attempted to handle the address register valid bits
separately, but reversed the bit order.
Jira: ZEP-1568
Change-Id: I240d072610af9979ca93c0081ed862df08929372
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Coverted:
_ScbBusFaultAddrGet
_ScbMemFaultAddrGet
To use direct CMSIS register access
Jira: ZEP-1568
Change-Id: Ic49b3ac3fc4fb63d413f273569c77f6539e4e572
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
After introduction and activation of STM32Cube LL based driver on
F3 and L4 series, this commit removes the no more needed code for
native driver for these soc.
Change-Id: I266d1a3fc4b464cee34b1cc1a1a333c5bf923e41
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
