Commit graph

15409 commits

Author SHA1 Message Date
Tomasz Bursztyka
f0f9be881f net: Fix a const specifier issue
Duplicate const specifier, it should be the pointed data that is const.

Jira: ZEP-1723

Change-Id: I194abb0fc9ad564c6d53e4727bd63c8099d4eb2e
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2017-02-15 12:20:08 +02:00
Chuck Jordan
ae15a26751 arc: add _tsc_read for 64-bit timestamp
This implementation of _tsc_read returns a 64-bit value that
is derived from the 64-bit tick count multiplied by hwcycles per tick,
and then it adds the current value from the 32-bit timer.
This produces a 64-bit time. There is a bunch of math here, which
could be avoided if the CPU is built with Real-Time-Clock option.
EM Starter Kit SOCs don't have this. I don't think Arduino 101 does
either.

See ZEP-1559

Change-Id: I9f846d170246556ac40fe2f45809e457c6375d8c
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2017-02-15 05:55:09 +00:00
Andrew Boie
35fcb2736c arc: enable gen_isr_tables mechanism
Change-Id: I5897e110f554377796bfe38dd5c0f8652c29e5be
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-15 04:54:47 +00:00
Andrew Boie
3944d8313e gen_isr_tables: apply offset to irq parameter
The interrupts would be placed at incorrect offsets on systems where
some interrupt vectors are reserved for exceptions, such as ARC.

Change-Id: I5b1f00eb9e8aecb84ae66e3d0461a734ffb5fbe6
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-15 04:49:19 +00:00
Andrew Boie
bd69c3bdf0 riscv32: enable gen_isr_tables mechanism
Change-Id: Ia09d9a4d3412424dcbb25db829059a0714d81214
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-15 04:49:17 +00:00
Anas Nashif
15a6598691 Merge "Merge remote-tracking branch 'origin/core'" 2017-02-15 04:33:25 +00:00
Jithu Joseph
417c341011 include/crypto: Crypto abstraction header
Adds crypto API interface for interaction between applications
and crypto drivers. Encryption/Decryption APIs are defined
here.

Jira: ZEP-328

Change-Id: I1a534ae2a69c7e1c416fa78a2822c37040b225f6
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
2017-02-15 01:08:13 +00:00
Marcus Shawcroft
ccd6d8c79f net/dhcpv4: Remove unused dhcpv4 offer state
The offer state is unused, remove it.

Change-Id: I9d6217dae291bb90c57c77ce439809bf7e9a9177
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2017-02-14 08:30:34 +02:00
Flavio Santes
bed71d0a02 net/mqtt: Fix inline doc for MQTT
Fix inline documentation for the MQTT API.

Jira: ZEP-1669

Change-Id: I90702eae236a9189b58e0f2fb2a6c5a3eeaf959c
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
2017-02-14 08:30:34 +02:00
Vinicius Costa Gomes
d8d16e81f5 iot/zoap: Add missing const modifier to header file
Makes it cleared that zoap_update_from_block() doesn't modify the
packet.

Change-Id: I35429b153370c50eb5ae9c914b47a3144faf2f04
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
2017-02-14 08:30:33 +02:00
Vinicius Costa Gomes
b032f54f60 iot/zoap: Fix header indentation
Change-Id: Iea2dd0f2493e240caa33f81fa68e5be894f0de86
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
2017-02-14 08:30:33 +02:00
Vinicius Costa Gomes
0c94d6a085 iot/zoap: Improve zoap.h documentation
Now types and functions have better explanations of their usage and
parameters associated.

Jira: ZEP-1657

Change-Id: I146688324080ac3cf0876f1db3c92c9514e1303d
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
2017-02-14 08:30:33 +02:00
Andrew Boie
587ba7b8ea arc: move openocd_dbg section
Its current placement was splitting the vector table in half.
Move to rodata, a better place for it. There's no requirement for
it to be in the text section.

Change-Id: I67724b2a26a9cb62c2ccd473cb54c53e4f74dc32
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-14 02:14:51 +00:00
Andrew Boie
f1260fb618 arc: linker.ld: fix BSS section declaration
The BSS section needs to use AT> in XIP systems otherwise the LMA
addresses in the ELF binary are wrong, leading to issues if we
try to manipulate the binary with objcopy. The GROUP_DATA_LINK_IN
macro does the right thing here.

This was already done on other arches but ARC was missed.

Change-Id: I93748e919e0b68c1ff2dfb4b85b7064a8d980f3a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 20:02:40 +00:00
Andrew Boie
42562b9367 xtensa: fix numerous checkpatch issues
Change-Id: I903f5f0692849fb9e7bf5d978b63b12bf1bd6e33
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 11:39:03 -08:00
Mazen NEIFER
0cfeb626c0 Xtensa port: Fixed scheduling bug caused to missing Endianess related macros.
XCC does neither define __BYTE_ORDER__ nor __ORDER_LITTLE/BIG_ENDIAN__ macros.
This resulted in field preempt of thread.base not correctly built from other
union fields prio and sched_locked, which caused wrong scheduling.

Change-Id: I8566ef4a5cf555906c012c4adc488f9afb26c053
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 11:39:02 -08:00
Andrew Boie
9249f876a9 xtensa: cleanup fatal error handling
1) Fatal errors now all go through _SysFatalErrorHandler. When the
simulator is used, only the death of 'essential' threads will result
in the simulator exiting; some test cases that test exceptions may
actually expect a thread to terminate abnormally.

2) The human readability of the exception errors is improved.

Change-Id: I77f57ea0eae15b0c55237681b959cd21e3fe8c1c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 11:39:02 -08:00
Andrew Boie
ceebd823e7 legacy: work around XCC issue in MDEF threads
The XCC compiler freaks out if a section name passed via
__attribute__((section)) has parenthesis in it. This happens in the
case of _MDEF_THREAD_DEFINE.

It turns out the whole mechanism of placing kernel objects in completely
unique sections is totally unnecessary. This patch is a workaround until
we can clean this up.

Change-Id: I12c88a1b8f5b27bec27d608614356c1b479c0a8c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 11:39:02 -08:00
Mazen NEIFER
aacfd63331 Xtensa port: Removed duplicate file and renamed to sys_io.h as other platforms.
Change-Id: I293bfa9ff8c5e641c727612c56968cec901dbfec
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
967cb2ef8a Fixed compilation error caused by bad initialization of unamed union field.
The old syntax is not accepted by some compilers including XCC.

Change-Id: Id90849a2159652ec225dd2c50d2dc2ddc22a3e08
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
af2593ea7e Xtensa port: Added linker script for several Xtensa cores.
Change-Id: I7a40d5f0c3fe8d25623b88f06523cb62e4ba4706
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
969f000a19 Xtensa port: Added support for Xtensa architecture to linker-defs.h.
Change-Id: Ic20d4746267bb9575960576c6b008c774fb6ef6d
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Andrew Boie
73691609b9 xtensa: fix find_msb_set() and find_lsb_set()
find_msb_set logic was wrong. find_lsb_set() is now an inline function.

Change-Id: I2c19540907723589298b2f6af2ce1d68704bf1d7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 08:04:27 -08:00
Andrew Boie
aa3ab35c88 xtensa: fixup license identifiers
Master branch changed requirements for license headers while this
branch has been in development.

Change-Id: I9bce16ff275057a4bb664019628fc9b6de7aef7c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
dc391f566c Xtensa port: Added support for Xtensa architecture in zephyr include files.
Change-Id: I1ac677cd6da5222707fe31ead71dc354f7c94443
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
f7538f0005 Xtensa port: Added support in arch/cpu.h for Xtensa cores.
Change-Id: If4a053f6164fd2fa30f148e6e907f662cda50722
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
c024e429c9 Xtensa port: Added support for Xtensa cores in toolchain/gcc.h.
Change-Id: Ic76934411e79c288e1440e21ee38e9a95a0399b9
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
3eca4f1f57 Xtensa port: Added Xtensa specific include files.
Change-Id: I9316f847934505bc609e271221027221b76050d6
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Anas Nashif
468eaf6c39 mvic: include stdint for uint32_t
Change-Id: I1ce93a20d657044526c96998c4fdf37624a0b30e
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-02-11 07:00:40 +00:00
Juan Manuel Cruz Alcaraz
75be503bbb i2c: Adds a functions set that supports flexible addressing.
The current I2C API provides inline functions to access 1 byte
register addresses. This commit adds a set of I2C inline functions
as shortcuts to handle:

- 16 bit register addressing. A family of functions that allows to
  handle 2 byte register addressing and can receive the address
  parameter as a simple variable. This allows a developer to handle
  the address as a C constant or macro.

- Multiple byte addressing. A family of functions to access
  registers with a configurable register address size. This family
  of functions handle register addressing of any size but receives
  the address parameter as a byte array.

Change-Id: Id369ab9eaad7eea807554371d3a520f67dc2e0f2
Signed-off-by: Juan Manuel Cruz Alcaraz <juan.m.cruz.alcaraz@intel.com>
2017-02-11 05:20:07 +00:00
Anas Nashif
110df98619 Merge "Merge arm branch into master" 2017-02-11 04:00:58 +00:00
Leandro Pereira
570634a259 kernel: Add OpenOCD support
In order for OpenOCD to have a high-level view of an RTOS, it uses the
GDB protocol to obtain symbols from the system.

The GDB protocol, however, does not allow obtaining fields from
structures directly, and hardcoding offsets is not only brittle (due to
possibly different architectures or changes in the code), it's also
infeasible considering Zephyr is highly-configurable and parts of key
structs can be compiled in or out.

Export an array with offsets for these key structs. Also add a version
element in that array to allow changes in those structs.

Change-Id: I83bcfa0a7bd57d85582e5ec6efe70e1cceb1fc51
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-02-11 03:57:19 +00:00
Andrew Boie
c99c686b2c nios2: use gen_isr_tables mechanism
Change-Id: If1ffcedf86a015789b42e7aec45dae3cc58f74fa
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-11 01:28:00 +00:00
Andrew Boie
2752357922 arm: enable direct interrupts feature
Issue: ZEP-1038
Change-Id: I5417e516cc994e2bbe6bb987d9ed95e912941aa0
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-11 01:27:59 +00:00
Andrew Boie
e7acd3224c arm: use gen_isr_tables mechanism for interrupts
This replaces the hard-coded vector table, as well as the
software ISR table created by the linker. Now both are generated
in build via script.

Issue: ZEP-1038, ZEP-1165
Change-Id: Ie6faaf8f7ea3a7a25ecb542f6cf7740836ad7da3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-11 01:27:58 +00:00
Andrew Boie
1927b3d020 gen_isr_tables: New static interrupt build mechanism
This is a new mechanism for generating interrupt tables which will
be useful on many architectures. It replaces the old linker-based
mechanism for creating these tables and has a couple advantages:

 1) It is now possible to use enums as the IRQ line argument to
    IRQ_CONNECT(), which should ease CMSIS integration.
 2) The vector table itself is now generated, which lets us place
    interrupts directly into the vector table without having to
    hard-code them. This is a feature we have long enjoyed on x86
    and will enable 'direct' interrupts.
 3) More code is common, requiring less arch-specific code to
    support.

This patch introduces the common code for this mechanism. Follow-up
patches will enable it on various arches.

Issue: ZEP-1038, ZEP-1165
Change-Id: I9acd6e0de8b438fa9293f2e00563628f7510168a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-11 01:27:58 +00:00
Jithu Joseph
d625c2bb4c grove: fix variable type mismatch
These were reported by ISSM compiler.

Jira: ZEP-1179

Change-Id: I10d04c2949ad2a390d4c1159d2342c73108a58b7
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
2017-02-11 00:14:15 +00:00
Andy Gross
ac37e3e2c7 arm: include: Add DTS generated file to arch.h
This patch moves the include for the generated_dts_board.h inside of
the include/arch/arm/arch.h file.  This was done to simplify the
includes required for files.  Only two files will include the dts
generated include file directly: arch.h and the linker.ld

Change-Id: I2614f4fd4eeed2ab635a3264d7dac8b83f97b760
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-02-10 15:31:26 -06:00
Kumar Gala
6ca87b576e arm: cmsis: Remove last bits of scs/scb as we've converted to CMSIS
We now use CMSIS for ARM Cortex-M SoCs so we can remove the last bits of
scs and scb.

Jira: ZEP-1568

Change-Id: I0c7c45b0321dc402ed594e9faffb5109922edcf0
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-02-10 15:14:23 -06:00
Kumar Gala
3a7cc31e08 arm: cmsis: cleanup use of _SCS_CPACR_CP1{0,1}_Pos define
_SCS_CPACR_CP10_Pos and _SCS_CPACR_CP11_Pos come from scs.h, we have
versions defined in cmsis.h we should be using instead.

Change-Id: Icd8db02000bbc9ef8b2cf89d359e008f62a7d5e9
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-02-10 14:47:41 -06:00
Kumar Gala
52cf45c62a arm: cmsis: Convert _Scb*Fault*Reset to use direct CMSIS register access
Coverted:
	_ScbMemFaultMmfarReset
	_ScbBusFaultBfarReset
	_ScbUsageFaultAllFaultsReset

To use direct CMSIS register access.

Also removed scb.h and references as there is no longer any code in it.

Jira: ZEP-1568

Change-Id: I469f6af39d1bd41db712454b0b3e5ab331979033
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-02-10 14:47:41 -06:00
Kumar Gala
94db819626 arm: cmsis: Convert _ClearFaults to use direct CMSIS register access
The previous code incorrectly used the value 0xfe to clear the mem and
bus faults. It attempted to handle the address register valid bits
separately, but reversed the bit order.

Jira: ZEP-1568

Change-Id: I240d072610af9979ca93c0081ed862df08929372
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-02-10 14:47:41 -06:00
Kumar Gala
737207f052 arm: cmsis: Convert _Scb*FaultAddrGet to use direct CMSIS register access
Coverted:
	_ScbBusFaultAddrGet
	_ScbMemFaultAddrGet

To use direct CMSIS register access

Jira: ZEP-1568

Change-Id: Ic49b3ac3fc4fb63d413f273569c77f6539e4e572
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-02-10 14:47:41 -06:00
Kumar Gala
d2679c7bbb arm: cmsis: Convert _Scb*FaultIs* & _ScbIs*Fault to use CMSIS register access
Converted:
	_ScbHardFaultIsBusErrOnVectorRead
	_ScbIsMemFault
	_ScbMemFaultIsMmfarValid
	_ScbMemFaultIsStacking
	_ScbMemFaultIsUnstacking
	_ScbMemFaultIsDataAccessViolation
	_ScbMemFaultIsInstrAccessViolation
	_ScbIsBusFault
	_ScbBusFaultIsBfarValid
	_ScbBusFaultIsStacking
	_ScbBusFaultIsUnstacking
	_ScbBusFaultIsImprecise
	_ScbBusFaultIsPrecise
	_ScbBusFaultIsInstrBusErr
	_ScbIsUsageFault
	_ScbUsageFaultIsDivByZero
	_ScbUsageFaultIsUnaligned
	_ScbUsageFaultIsNoCp
	_ScbUsageFaultIsInvalidPcLoad
	_ScbUsageFaultIsInvalidState
	_ScbUsageFaultIsUndefinedInstr

To use direct CMSIS register access

Jira: ZEP-1568

Change-Id: I2a99a4101c5960f825a502c225e511e49fe93bba
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-02-10 14:47:41 -06:00
Kumar Gala
1a146174cb arm: cmsis: Convert _ScbDivByZeroFaultEnable to use direct CMSIS register access
Jira: ZEP-1568

Change-Id: I0118f2d44d2b6fb4eac41b0c66b20c5a85e35795
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-02-10 14:47:41 -06:00
Kumar Gala
831764a898 arm: cmsis: Convert _ScbHardFaultIsForced to use direct CMSIS register access
Jira: ZEP-1568

Change-Id: I9bf2ec4c84f87c8e9d72dc41324d7ee627d2dc2e
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-02-10 14:47:41 -06:00
Kumar Gala
a033a89d76 arm: cmsis: Convert _ScbActiveVectorGet to use direct CMSIS register access
Jira: ZEP-1568

Change-Id: Ibbb3f71d7ee42ab62f764d45bd334c7840b3c04d
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-02-10 14:47:41 -06:00
Kumar Gala
388c26574f arm: cmsis: Convert FaultEnable to use direct CMSIS register access
Jira: ZEP-1568

Change-Id: I1274ee206576babb4bc0b9308d1cc24d7092166a
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-02-10 14:47:41 -06:00
Kumar Gala
cecdc99f38 arm: cmsis: Convert _ScbIsNestedExc to use direct CMSIS register access
Jira: ZEP-1568

Change-Id: I3d41fe88293bab2f40d9177cedb56e9265250dff
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-02-10 14:47:41 -06:00
Erwan Gouriou
3c389b54f0 clock control: clean up after stm32cube LL driver
After introduction and activation of STM32Cube LL based driver on
F3 and L4 series, this commit removes the no more needed code for
native driver for these soc.

Change-Id: I266d1a3fc4b464cee34b1cc1a1a333c5bf923e41
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-02-10 14:47:41 -06:00