Commit graph

8801 commits

Author SHA1 Message Date
Martí Bolívar
22e8283992 dts: mec172x: pinctrl fixes
Two issues:

- The nsmi_gpio107 node is being defined twice with the same pinmux
  property value. This is an error when compiling the file with dtc.
  Zephyr's dtlib doesn't currently error out on this, but it will soon.

  Fix this by removing one of the redundant definitions.

- The eeprom_clk_gpio117 node label is referring to a node named
  gpspi_clk_gpio117, which is already defined in the same file, but
  with a different pinmux property value. This looks like a clear
  copy/paste error causing invalid pinmux settings for the
  gpspi_clk_gpio117 node.

  Fix it by aligning the node name with the node label to create
  a separate node with its own pinmux value.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2022-09-21 07:55:40 -07:00
Martí Bolívar
387b16a3a5 dts: nxp: rt11xx: fix lpuart12 base addresses
The correct address is 0x40c28000 on these SoCs.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2022-09-21 07:55:40 -07:00
Francois Ramu
d53d5c1e42 dts: arm: st: L0, L1, L4 Fix internal temperature value incorrect.
Fix the incorrect temperature sensor (Die temp), the default value of
the vref-mv is 3.3V.
Actually, the vref is a board value rather than a soc one

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-09-21 08:57:58 +00:00
Emilio Benavente
e23a9e355a dts: bindings: fixed pinctrl binding description for nxp mcux rt-iocon
The FULLDRIVE description on the rt-iocon yaml file was
describing the slew rate and not the FULLDRIVE property.

Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
2022-09-20 08:17:17 +00:00
Ettore Chimenti
96362d5a12 dts: arm: stm32f303: add uart5 node
Add missing UART5 node to STM32F303 chip family DTSI.

Signed-off-by: Ettore Chimenti <ettore.chimenti@seco.com>
2022-09-20 08:10:30 +00:00
Emilio Benavente
40af5bf133 dts: arm: nxp: lpc: Added PWM to the peripheral node
The LPC55s3x SOC comes with 2 FlexPWM peripherals each with 4 Sub-Modules.
Each Sub-Modules has 2 channels A && B.

Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
2022-09-19 10:10:32 +00:00
Mahesh Mahadevan
5bebbb91b9 dts: rt10xx: Fix SAI dts entries
The clock gate register bits were incorrectly defined

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-09-16 14:50:06 -05:00
Mahesh Mahadevan
46eaa81ac0 dts: rt1010: Fix RT1010 IP base addresses
Fix the Base addresses for the IP blocks that are
located at a different address on RT1010

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-09-16 14:50:06 -05:00
Francois Ramu
cb0daa3d03 dts: bindings: stm32 uart gives the EXTI line nb for PM
When the EXTI Line nb is not set as interrupt by default
(at reset value), the uart instance cannot waekup the
system from its low power stop mode.
The EXTI line must be specified, like with stm32WL55

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-09-15 15:02:47 +00:00
Lauren Murphy
85445474f2 boards, dts: fix filenames and dts refs for adsp clock
Changes filenames and DTS references from CAVS clock to
ADSP clock.

Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
2022-09-14 07:23:08 -04:00
Lauren Murphy
1983a4c50c boards, dts: fix namespace for intel adsp cavs, ace
Fixes namespace for Intel ADSP CAVS and ACE boards.

Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
2022-09-14 07:23:08 -04:00
Daniel Leung
6034714909 dts: lps22hh: extends to support being on I3C bus
This adds a new YAML file to allow LPS22HH to work on I3C bus.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-09-09 17:42:33 -04:00
Daniel Leung
164a1aa95e soc: arm/nxp/imx/rt6xx: add bits to support I3C controller
This adds a few bits to the RT6xx SoC code to support the I3C
bus interface on RT600 series.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-09-09 17:42:33 -04:00
Daniel Leung
3c8dcb568d dts: add a binding for NXP MCUX I3C controller
This adds a binding for NXP MCUX I3C controller, with compatible
string "nxp,mcux-i3c".

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-09-09 17:42:33 -04:00
Daniel Leung
9cdd49c6e6 dts: add base binding for I3C controllers
This adds a base binding for I3C controllers.

Note that this follows the Linux kernel 5.17 bindings under
Documentation/devicetree/bindings/i3c/i3c.yaml.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-09-09 17:42:33 -04:00
Daniel Leung
db9d83fbb8 tests: devicetree: add bits to test multi-bus nodes
This adds a few bits to the devicetree API tests for multi-bus
nodes where a bus can support multiple protocols. This uses
I3C as basis as I3C controller can support both I2C and I3C on
the same bus, while I2C controller cannot support both. So
this needs to make sure the correct bus macros are generated
if appropriate (and not generated if not needed).

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-09-09 17:42:33 -04:00
Andriy Gelman
888a17cfda drivers: serial: uart_xmc4xxx: Use pinctrl driver
Use xmc4xxx pinctrl in uart driver.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2022-09-09 16:28:41 -04:00
Andriy Gelman
5feae0eafc drivers: pinctrl: Add pinctrl driver for xmc4xxx
Add pinctrl driver for infineon xmc4xxx devices.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2022-09-09 16:28:41 -04:00
Andriy Gelman
105cd84eb7 drivers: serial: uart_xmc4xxx: Get input source from dts
Get input source config from devicetree.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2022-09-09 16:28:41 -04:00
Gerson Fernando Budke
6d5cdc17b4 drivers: ieee802154: rf2xx: Add support to Sub-Giga
Add support to at86rf212[b] sub-giga devices. This work enables use of
pages 0, 2 and 5 in accordance with IEEE-802.15.4/2003/2006/2011. The
proprietary speeds can be object of future work.

Note: It is recommended that user define a power table for better
performance, low emissions and to save power. A reference power table
can be found in the datasheet and should be used for tests only and
not on a final product.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2022-09-09 10:31:35 -07:00
Gerson Fernando Budke
65960c4d32 drivers: ieee802154: rf2xx: Move power table to devicetree
The current version of power table is hardcoded in the driver which is a
problem when use devices in production. This change remove all hardcode
from driver and reimplement the feature to allow people create a table
which is defined in devicetree. The big advantage is that each board can
define their own table based on lab tests and allows use of FEM devices
inclusive.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2022-09-09 10:31:35 -07:00
Huifeng Zhang
d161485173 boards: fvp_baser_aemv8r: fix wrong reg size
Some reg size in fvp-aemv8r.dtsi isn't correct. This commit is used to
fix it.

- gic, the correct reg size is 0x10000 and 0x200000.
- uart0-3, the correct reg size is 0x10000.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2022-09-09 16:36:37 +00:00
Mahesh Mahadevan
e98a61e791 dts: MXRT1xxx: Update USB configuration
Increase the USB speed from Full speed to
High speed

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-09-09 09:44:46 -05:00
Mahesh Mahadevan
3a7c719fb4 dts: nxp: Add a property to get USB controller type
The property is similar to the usb_controller_index_t
enum that is available in the NXP SDK.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-09-09 09:44:46 -05:00
Thomas Stranger
81bf4f98f7 drivers/w1: driver for ds2485 1-Wire master
This commit introduces the 1-wire master driver for maxim ds2485.

The ds2485 master has nearly the same (1-wire) feature set and
i2c-interface as the ds2477.
Therefore the common parts are extracted, but to avoid
any nda troubles only the ds2485 specific part is included.

Compared to older 1-wire masters, the ds2485 supports higher level
commands, supporting multi byte operations, search next, automatic crc
calculation.

In this driver only basic read and write operations are supported,
further hardware features are not yet utilized by the driver.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
2022-09-09 14:11:30 +00:00
Thomas Stranger
f8d2226d58 dts/bindings: w1 move active-pullup property to w1-master
This property is supported by most 1-Wire masters,
move it to the w1-master binding.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
2022-09-09 14:11:30 +00:00
Erwan Gouriou
a6a3642510 dts: arm: stm32u5: Fix LSE default driving-capability
According to errata sheet, LSE driving-capability should not be set
to 0 or 1.
Set it to 2 as default value.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-09-09 14:09:22 +00:00
Kumar Gala
d699bdfda0 dts: bindings: add bindings for missing timer
Add dts bindings for various timer nodes that did not have a
binding associated with them.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-09-09 09:58:48 +00:00
Gerson Fernando Budke
3fcf46b2ab dts: arm: stm32l5: Add sdmmc1 node
Add SD/MMC slot devicetree configuration.

Signed-off-by: Gerson Fernando Budke <gerson.budke@ossystems.com.br>
2022-09-09 09:56:51 +00:00
Martin Jäger
77e4c6515a drivers: can: native_posix_linux: initial implementation
This driver provides an interface to SocketCAN interfaces of the Linux
system running a Zephyr application with the native_posix board. These
interfaces may be virtual or actual CAN buses.

Signed-off-by: Martin Jäger <martin@libre.solar>
2022-09-09 10:08:59 +02:00
Ederson de Souza
3f6286040b dts/bindings/mm: Fix ADSP Meteor Lake DTS bindings
New properties were added but not in the bindings. Add them.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-09-08 20:05:15 -04:00
Ederson de Souza
fcdc9c78e2 soc/xtensa/intel_adsp: Get register address from DTS
Instead of hardcoding it where it's used.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-09-08 18:03:33 -04:00
Ederson de Souza
03a947850d drivers/mm: Get some bit configurations from DTS instead of SoC version
Migrate information to DTS and get it from there on the code. Note that
for CAVS 15, the information is not migrated as there's no DTS entry for
it. It can be brought back (in the DTS) if TLB support is enabled for
it.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-09-08 18:03:33 -04:00
Henrik Brix Andersen
420385218f dts: arm: nxp: lpc55sxx: reduce LPC MCAN RAM usage
Reduce the default RAM usage for the NXP LPC MCAN CAN controller driver by
reducing the number of RX buffers, TX buffers, and filter elements.

The LPC MCAN uses regular SRAM as backend and the default configuration
causes SRAM overflows for many CAN tests.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-09-08 19:26:01 +02:00
Jeremy Bettis
da9448396c drivers/serial: Make serial_test a proper emul
Add emulator functionality to the serial_test driver, so that it can be
used to simulate a device on the other end of the uart.

If you don't set the buffer-size property in the dts node, there should
be effectively no change from the previous behavior.

Signed-off-by: Jeremy Bettis <jbettis@google.com>
2022-09-08 15:26:41 +00:00
Francois Ramu
0fe776c5a2 dts/bindings: introduce the DMA for the octospi devicetree
Add the DMA in the DTS binding for OCTOSPI interface
for the stm32 devices from STMicroelectronics.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-09-08 10:07:21 +00:00
HaiLong Yang
cc9a51a39f dts: add gd32 fmc flash memory info
There are three types GD32 FMC.

GD32 FMC v1: its flash memory has 1 bank, page size is equal in the
bank, flash size is smaller than 512KB.

GD32 FMC v2: its flash memory has 2 banks. Page size equal within the
same bank but different between banks. Flash size can be up to 3072KB.
FMC v2 has two registers to control bank0 and bank1 separately.

GD32 FMC v3: its flash memory has 2 banks, use sector size as the
minimum operating unit, the sector size is not equal.

Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
2022-09-08 10:13:05 +02:00
Daniel DeGrasse
03654969aa dts: add binding for LPC SDIF
add binding for LPC SDIF SD host controller

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-09-08 10:06:28 +02:00
Nils Larsen
1d7ff08c82 dts: rt11xx: add enet1g peripheral and set up clock
The enet1g peripheral was missing in device tree for nxp rt11xx.
With this commit, the peripheral can be operated like the enet peripheral
with the eth_mcux (kinetis-ethernet) driver at 10/100 Mbit (no gigabit).

Signed-off-by: Nils Larsen <nils.larsen@posteo.de>
2022-09-07 16:50:08 -05:00
Pieter De Gendt
bcbd8ff7ff drivers: pwm: pwm_mcux: Add WAIT/debug run options to devicetree
Add properties to allow PWM to keep running in WAIT or debug modes.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2022-09-07 16:28:10 -05:00
Pierre Marzin
f8e7961da7 dts: arm: rcar_gen3_cr7: declare pwm0 node
R-Car Gen3 platforms have up to 7 channels. Add the node to
the rcar_gen3_cr7 SoC series. In contrary to Linux, declare
only one PWM controller with 7 channels. So only one node is
written into dtsi file.

Signed-off-by: Pierre Marzin <pierre.marzin@iot.bzh>
2022-09-07 15:50:49 +02:00
Pierre Marzin
1367767624 dts: bindings: pwm: add Renesas R-Car PWM
This add the PWM can bindings for R-Car platforms.
Tested on Renesas Gen3 (h3).

Signed-off-by: Pierre Marzin <pierre.marzin@iot.bzh>
2022-09-07 15:50:49 +02:00
Kevin Wang
93025635b3 dts: bindings: spi: add andes spi driver
Add Andes SPI atcspi200 dts binding.
Remove not necessary property for spi node in soc dtsi.

Signed-off-by: Kevin Wang <yunkai@andestech.com>
2022-09-07 15:34:47 +02:00
Andrey Borisovich
c75e6cfcb9 soc: intel_adsp_ace1x: Added IPC/IDC implementation
Added IPC and IDC implementation for Intel ADSP ACE1X SoCs.

Co-authored-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-09-06 15:33:24 -04:00
Piotr Kmiecik
0acd68247f drivers: ace_v1x wallclock driver
Wallclock driver with functionality required by ACE v1x base firmware.

Signed-off-by: Piotr Kmiecik <piotrx.kmiecik@intel.com>
2022-09-06 17:44:03 +02:00
TOKITA Hiroshi
4f7201463a dts: bindings: adc: Add RaspberryPi Pico ADC
Define RaspberryPi Pico ADC.

The ADC has internally connected temperature sensor,
Add property to enable this.

The ADC has a single VREF. VCC usually connects to it,
but it may not be in a case.
Add property to make configurable it.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
2022-09-06 17:11:19 +02:00
Tatsuroh Hayashi
36f10006c1 dts: arm: st: f1: STM32F1RTC support
Add RTC support of STM32F1 family.

Signed-off-by: Tatsuroh Hayashi <tatzu884@gmail.com>
2022-09-06 09:43:54 -05:00
Gerard Marull-Paretas
64eb350e5e drivers: spi: gd32: use clock control API
Use the clock control API to enable/get rate of SPI clocks.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-09-06 09:57:25 +02:00
Gerard Marull-Paretas
0aadc2dd44 drivers: serial: gd32: use clock control API
Use the clock control API to enable the UART clock.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-09-06 09:57:25 +02:00
Gerard Marull-Paretas
22e64fddfd drivers: pwm: gd32: use clock control API
Use the clock control API to enable/get rate of timer clocks.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-09-06 09:57:25 +02:00