The flash size is the second part (size) of the first reg value, not the
first part (address) of a nonexistent second reg value.
Based-on-patch-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
This adds a v1.0 support dts flag for devices. This also makes it so it
doesn't try to send a GETCAPS (GETHDRCAP) ccc if this flag is set and it
doesn't support any HDR modes.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
The current configuration allocate 476kB (672 − 196) to the NWP. This
configuration is only required with offloaded network stack
(CONFIG_WIFI_SILABS_SIWX91X_NET_STACK_OFFLOAD).
Since this parameter is not set by default, increase memory allocated to
Zephyr.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Chip siwx91x has 672kB of SRAM shared between the Cortex-M4 (Zephyr) and
the NWP (Network Processor). 3 memory configurations are possible for
the Cortex-M4:
- 196kB
- 256kB
- 320kB
Less memory is allocated to Zephyr, more memory is allocated to NWP,
better are the WiFi and BLE performances.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Some instances of DMA (dma0) can use the normal sram to store their
descriptors. In this case, it makes sense to allow the linker to
allocate the memory rather than tweaking the memory layout.
So, if the attribute silabs,sram-region is not defined, use a statically
allocated buffer.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Memory areas for DMA descriptors are shared with the DMA hardware block.
There area should be cached by the CPU.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Silabs siwx91x hardware use specific memory areas to store descriptors
for DMA requests. These areas are tightly coupled between the CPU and
the hardware. This helps in reducing the wait cycles.
Until now these addresses was also hard coded in the DT and in the
linker script. This patch leverage the zephyr,memory-region driver to
centralize the information in the DT.
Then, with this new implementation, the memory mapping is easier to
understand for the reader.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Add support for SPI to cc23x0 SoC. Only controller mode is implemented.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
AXP2101 is MFD device. Zephyr already support the regulator part. This
commit introduces intial support for the charger one.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
For the SAI peripheral, the MCLK signal input/output direction is
independent from the TX or RX bit clocks directions (TCR2[BCD] and
RCR2[BCD]). Introduces mclk-output property.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
This commit adds the Device Tree include files
for the STM32WBA65x device
Adding GPIO D/E/G banks.
Renaming JTAG reset pin.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Make the IOVDD settling delay configurable, instead of hardcoding a
delay that happens to work for the dev kits. For example, the nPM1300
load switches have a soft-start time of 1.8 ms.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Add STM32N6 USB OTG HS compatible 'st,stm32n6-otghs'
that doesn't require pinctrl-0 and pinctrl-names.
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
We fixed some minor bugs and one missing component for
Microchip MEC5 HAL based chips, MEC174x and MEC175x.
These changes are in preparation for board check-in and
hello world sample. Added the clock-frequency property
to the cpu and rtimer nodes. This properity is used
derive the Kconfig's for the kernel tick.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
The tmp116 sensor driver also supports tmp117 and tmp119. Therefore rename
to indicate that is supports a range of tmp devices.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Adds support for the CVA6 CPU on a Genesys 2 FPGA board
(https://github.com/openhwgroup/cva6).
The SoC currently contains the CVA6 CPU with the SV39 MMU, interrupt
controllers (CLINT and PLIC), UART, a SPI for booting from SD, a boot
ROM, and I2C controller for on-board audio, a GPIO and the lowRISC
ethernet subsystem.
Two slightly different versions of the board are added, with a 64-bit
and a 64-bit configuration of CVA6, respectively.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
Adds support for the CVA6 family of RISC-V CPUs.
CVA6 is commonly found as a soft core CPU on FPGA designs.
Different configurations and instruction set extensions can be
configured, and different SoCs targeting various FPGA boards are
available.
This commit adds support for the 32-bit and 64-bit configurations
of CVA6, as well as three slightly different SoCs (a minimal 32-bit
configuration, a 64-bit configuration without FPU, a 64-bit
configuration with FPU).
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
Create a driver implementation for the battery charge controller
TI BQ25713.
It includes the ability to enable / disable the controller and also
to setup max current and voltage charge parameters at initialization
time but also at run time.
On the other hand, it is possible to assign / obtain input voltage
and current regulation.
Signed-off-by: Kiara Navarro <knavarro@paltatech.com>
inherit from base.yaml instead of sd-device since this device is not
meant to be used on an SD bus.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Accidentall chosen wrong interrup level for flash controller
fixed to be inline with other devices flash controller level
Signed-off-by: Petri Pitkanen <petri.pitkanen@silabs.com>
Add support for Nuvoton numaker m55m1x series EMAC controller.
Also include NOCACHE_MEMORY allocation.
Support to generate random mac address and remove emac data flash.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Add a way to assign the dynamic address for a primary controller. This
is the address that is broadcasted out with the ccc DEFTGTS, and is the
address that secondary controllers use to communicate with the primary
controller.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Renamed the drv8424 stepper driver to indicate its support of the drv8424,
drv8425, drv8426, drv8434 and drv8436 stepper controllors. Also made the
microstep pins optional. All test files are renamed as well.
Signed-off-by: Jan Behrens <jan.behrens@navimatix.de>
ADC output values can have noise, even if the input is 0V. Add a noise
threshold so that raw ADC readings below the threshold can be zeroed
out. By default the threshold is disabled.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Update exit-latency-us with newly measured values. Measurement is
taking into account additional timing compared to wakeup from
WFI.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
