Remove the "required: true" attribute from the STM32 DMAMUX binding.
This is required for STM32WB0 series where the DMAMUX has no interrupt line
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
PR #79683 missed a few nodes introduced while it was under review.
Replace the remaining raw values with STM32_CLOCK in WB0 DTSI files.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Only initialize the HFXO Manager HAL driver if the HFXO is enabled in
DeviceTree, the device uses SYSRTC for timekeeping, and Power Manager
is enabled. HFXO Manager integrates with the Sleeptimer HAL driver for
SYSRTC to autonomously wake the HFXO prior to Sleeptimer wakeup from
deep sleep. It is not needed on devices that don't have HFXO-SYSRTC
integration, and it is not needed if the application doesn't use deep
sleep.
Add missing call to init_hardware() prior to init().
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Additional IO ports (6,7 and 8) are availble on the r7fa6m4af3cfb
variant of the RA6M4 Microcontroller.
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
The CSI is an NXP IP and the driver has been very much changed
by NXP, so add NXP copyright to it.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
The peer remote device "source_dev" can be retrieved from the
remote-endpoint-label. Direct reference via phandle is not needed.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
Instead of fixing csi2rx clock frequencies, set them according to the
pixel rate got from the camera sensor.
Signed-off-by: Trung Hieu Le <trunghieu.le@nxp.com>
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
The peer remote device "sensor_dev" can be retrieved from the
remote-endpoint-label. Direct reference via phandle is not needed.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
USB configuration is missing in Devicetree for NXP MCX C series.
Add the configuration to common and SoC specific dtsi file.
Delete usb node for SoCs without USB support.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
Some NXP SoC's do not have USB voltage regulator present.
Add property to indicate it. Negative logic is used, because
the regulator is present in great majority of SoC's, and thus the new
property can be added only for SoC's without the regulator.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
Add stm32h7 ethernet compatible "st,stm32h7-ethernet",
used also for stm32h5.
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
The DT node "stimer0" represented two different hardware timers,
RTCC and SYSRTC. Use the correct peripheral names for the nodes.
Add interrupt names and missing interrupt numbers.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Documents cirrus,hw-i2c-lock property in the devicetree bindings. This
flag indicates that the control port write-lock was enabled in hardware
via the PGPIO2 pin.
Signed-off-by: Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
Add a pinctrl driver for Microchip MEC5 HAL based chips.
The driver removes the YAML enum "no change" property
value from the driver strength and slew rate properties.
Update the shared header file in mec soc common folder to
use a different Z_PINCTRL_STATE_PINCFG_INIT for MEC5.
Modifications to legacy MEC172x XEC PINCTRL will be in
a future PR.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Die temperature measurement is not configured in devicetree
for NXP MCX C series.
Add die temperature measurement configuration.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
The nRF54 and nRF92 chips has data cache, which means
the ICMsg and ICBMsg must be configured to follow required
cache alignment of the shared memory.
The `dcache-alignement` needs to be defined for that.
Signed-off-by: Dominik Kilian <Dominik.Kilian@nordicsemi.no>
Renamed andestech,plic-sw to andestech,mbox-plic-sw because the mbox node
is based on the PLIC interrupt controller node instead using the plic
hardware directly.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
The plic-sw is the same hardware as the plic interrupt contoller and should
be used with intc_plic driver instead of separate mbox driver.
Renamed plic-sw node from "mbox: mbox-controller@e6400000" to
"plic_sw: interrupt-controller@e6400000".
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
The ILPS22QS is an ultra-compact piezoresistive absolute pressure sensor
which functions as a digital output barometer, supporting dual full-scale
up to user- selectable 4060 hPa. The device delivers ultra-low pressure
noise with very low power consumption and operates over an extended
temperature range from -40 °C to +105 °C.
(https://www.st.com/en/mems-and-sensors/ilps22qs.html)
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Rename the Silabs HCI driver to hci_silabs_efr32.c to better indicate what
hardware it supports. Also rename the associated devicetree binding and
Kconfig options to be consistent with the new driver name.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
Add initial SoC support for the TI J721E SoC series Cortex-R5 core.
TRM for J721e https://www.ti.com/lit/zip/spruil1
File: spruil1c.pdf
Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
Signed-off-by: Andrew Davis <afd@ti.com>
Some instances of the FLEXSPI IP permit limiting AHB bus access so that
no memory access requests will straddle a page boundary. Add a property
to manage this setting.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Updated ADXL345 driver with RTIO stream functionality.
Added Trigger intterupt functionality. RTIO stream is using
FIFO threshold.Together with RTIO stream, RTIO async read
is also implemented.
Signed-off-by: Dimitrije Lilic <dimitrije.lilic@orioninc.com>
Timer driver using Microchip 32KHz based RTOS timer as the kernel
timer tick. The driver uses one of the 32-bit basic timers to
support the kernel's k_busy_wait API which is passed a wait
count in 1 us units. The 32-bit basic timer is selected by using
device tree chosen rtimer-busy-wait-timer set to the handle
of the desired 32-bit basic timer. If this driver is disabled,
the build system will select the ARM Cortex-M4 SysTick as the
kernel timer tick driver. The user should specify RTOS timer
as kernel tick by adding the compatible properity and setting
the status property to "okay" at the board or application level
device tree. The driver implements two internal API's for use
by the SoC PM. These two API's allow the SoC PM layer to disable
the timer used for k_busy_wait so the PLL can be disabled in
deep sleep. We used a custom API so we can disable this timer
in the deep sleep path when we know k_busy_wait will not be
called by other drivers or applications.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Introduce bindings for Series 2 oscillators: HFRCODPLL, HFRCOEM23,
LFRCO and LFXO.
Add clock tree representation in devicetree `clocks` node.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Switch EFR32MG21 to use the device init HAL. This makes the init sequence
the same as the rest of Series 2.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
The DC-DC converter was unconditionally initialized with default
settings on Series 2. Add device tree binding and nodes, and guard
call to init function. Map DT options to config header from HAL.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
