This commit removes the deletion of the `sram0` node, which resulted in
the compat string `mmio-sram` missing from the final devicetree when
building stm32l4r5-based platforms in Zephyr.
This bug was introduced in
306dea6ff3.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The zephyr,gpio-keys is now emitting input events, so it makes sense to
require a key code to be set. Change the zephyr,code property to be
required and add an example in the binding description.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Port the gpio_keys_zephyr driver from the gpio subsystem with a
dedicated API to the input subsystem reporting input events.
Move the test as well, simplify the cases a bit since the API is simpler
now.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The 200ns reset time specified in the datasheet are a minimum time; and the
nanoseconds were being rounded to whole microseconds anyway.
Also make it the same type as `config_delay_us` (`uint16_t`).
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
From FPGA-TN-02001-3.3 "iCE40 Programming and Configuration":
> After driving CRESET_B High or allowing it to float High, the AP must
> wait a minimum of 1200 µs, allowing the iCE40 FPGA to clear its internal
> configuration memory.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Change the preprocessor identifier from CONFIG_SOC_ESP32C3 to
SOC_GDMA_SUPPORTED so it can include ESP32S3 in GDMA routines.
Remove hardcoded values from hal calls to use dma_host instead.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
The board embeds an audio codec IC, Cirrus CS42L73. While there is no
in-tree driver for it, we need a binding to describe how it is wired in
the board, e.g. for IRQ/RESET lines.
Following Linux binding for the same IC, create one in
dts/bindings/sound. Note that Linux binding is less complete/outdated.
Ref. https://statics.cirrus.com/pubs/proDatasheet/CS47L63_DS1249F2.pdf
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
There is a spi-flash fl256s on emsdp board, which can be
contolled by DesignWare SPI driver. Now add DW SPI and
SPI-FLASH support for emsdp board.
Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
Remove SPI2 from F070 (not present on F070x6) and add it to F070xB.
Add it to F051 and remove it from F091 (since it is already defined).
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Flash erase-block-size is 2048 for F030xC, F070xB, and F071 and higher.
For all others, it is 1024, default value in base dtsi.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Remove calibrated temperature measure from base dtsi since it does not
exist for STM32F0x0, and add it only for the other STM32F0.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Fix DMA1 interrupt channels. There are 7 for STM32F071 and higher, and 5
for all others, default value for the series.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Remove TIM6, 7 & 15 from base dtsi, and add TIM6 & 15 to F030x8, TIM7 for
F030xC, TIM15 for F070, TIM6 & 7 for F070xC, TIM6 & 15 to F051, and TIM7
for F071.
Remove TIM2 from F072 and F091 dtsi since it is already included in F031.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Modify the successive dtsi include to better reflect the underlying
structure of the F0 family.
There are two main subfamilies: STM32F0x0 on one side, and STM32F0x1, x2
and x8 on the other
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Fixes the warning below. This commit does not change the firmware
binary. Thanks Kumar Gala for the suggestion.
build-mtl/zephyr/zephyr.dts:279.42-285.5: Warning (simple_bus_reg):
/soc/ace_comm_widget@71C00: simple-bus unit address format error,
expected "71c00"
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Add driver for Xptek XPT2046 resistive touch controller on SPI.
Only interrupt driven mode supported, does not do polling.
Signed-off-by: Seppo Takalo <seppo.takalo@iki.fi>
- Add overlay for the esp32c3 board to die_temp_polling sample.
- Add aliases for the die_temp_polling sample to esp32c3 dtsi.
Testing Environment:
esp32c3-devkitC-02
Signed-off-by: Hiroki Tada <tada.hiroki@fujitsu.com>
Introduce driver for NXP DCNANO LCDIF (lcd interface) peripheral,
present on iMX.RT500. Currently this driver only supports updating
the primary framebuffer, and does not implement support for the cursor
buffer present on this IP.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce driver for MCUX MIPI DSI 2L. This IP block differs slightly from
the existing MCUX MIPI peripheral, and uses a different hardware
abstraction layer. For these reasons, a new driver was introduced rather
than extending the existing mcux_dsi implementation.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Allow configuration of AHB RX buffer allocation. This allows sections
of the AHB RX buffer to be reserved for specific masters, which can
enhance performance.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
STM32L432 SDMMC issue
RM0394 :SDMMC
Not available on STM32L42xxx, STM32L432xx and STM32L442xx devices.
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
The driver utilizes ST Microelectronics library (which
exists in modules\hal\st\sensor\vl53l1x. Platform specific
headers and source files used by the library are included
and adapted for Zephyr.
The driver can be configured in proj.conf to use a
interrupt/polling methods and the use of the XSHUT pin on
the VL53L1X. All uses were tested successfully.
Signed-off-by: Mark Watson <mwatson@prosaris.ca>
This patch adds watchdog driver for Renesas Smartbond SOCs.
Co-authored-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
This adds driver for SmartBond TRNG peripheral that with separate
ISR an thread data pools.
Co-authored-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
Add support for configuring power on delay when using SPI SDHC. This
allows cards that reliably initialize with a shorter (1ms) delay to
avoid the long initialize delay otherwise imposed.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add I2C bus recovery support to the STM32 v1 and v2 driver. The STM32 i2c
peripheral does not natively support I2C bus recovery so recovery is
performed using GPIO bitbanging. This mirrors the bus recovery
implementation for NXP MCUX LPI2C driver.
Fixes: zephyrproject-rtos#54917
Signed-off-by: Maxmillion McLaughlin <github@maxmclau.com>
Microchip XEC devices specify GPIO pin using octal numbering and
organize pins in banks of 32. Chip documentation does not use
bank naming rather naming each pin by its octal number. This has
led to the developer having to calculate the bit position of a pin
in its 32-bit bank when a specifying the pin for GPIO usage. We
created a set of defines for all possible GPIO pins that specify
the DT GPIO bank name used in the chip level DTSI files and the
bit position in that bank.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
