Some files were missed during the migration. This patch adds the prefix
where missing.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Introduce a simple binding for atmel,24mac402 EEPROM that the SAM
GMAC ethernet driver can utilize to get MAC address out of. We
introduce a 'mac-eeprom' phandle into GMAC ethernet devicetree
node that will provide a pointer to the MAC eeprom to utilize.
Signed-off-by: Kumar Gala <galak@kernel.org>
Use the sifive,clint0 compatible instead of "riscv,clint0" and remove
interrupt controller fields (clint compatible is used for its timer
registers). Refer to the Linux or previous commits for more context.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use the sifive,clint0 compatible instead of "riscv,clint0" and remove
interrupt controller fields (clint compatible is used for its timer
registers). Refer to the Linux or previous commits for more context.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The CLINT (Core Local Interruptor) description was not aligned with
Linux. For example, there's no "riscv,clint0", but "sifive,clint0". The
peripheral is not described as an interrupt-controller either.
Ref. https://elixir.bootlin.com/linux/v5.18.14/source/arch/riscv/boot/
dts/starfive/jh7100.dtsi#L106
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
After some analysis I found out that there's no machine timer provided
by the "riscv" vendor. There are some specs for the mtime/mtimecmp
registers (this is why we can have a single driver), but the actual
register layout or implementations differ amongst vendors. GD32 uses the
Nuclei implementation, named "system timer" in their documentation. This
patch aligns with vendor specs.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This adds a driver for Maxims DS2484 Single-Channel 1-Wire master
driver. The DS2484 features an extra pin to enable sleep modes which
is available if the pin is configured in the device tree.
Signed-off-by: Caspar Friedrich <c.s.w.friedrich@gmail.com>
Unlike stated in 57df225b396e43358aac4cc998ed2e99fdb57780, RM0456.pdf
reference manual mentions about PLL1R that "Only division by 1 and even
division factors are allowed."
Though, in reference manual, there is one issue on PLL1R values
description, which should actually be:
0000000: pll1_r_ck = vco1_ck
0000001: pll1_r_ck = vco1_ck / 2 (default after reset)
0000010: Not allowed
0000011: pll1_r_ck = vco1_ck / 4
...
This description will be fixed.
Reflect this in binding and driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This configuration does not work on some variants (simulator), reduce
the number to something that work on all variants.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Instead of enabling WOVCRO clock based on the SOC, use a configuration
to indicate support, so that each platform can specify if WOVCRO is
supported or not.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Add system clock control device (sysclk), so that the drivers can turn
on/off its clock through the clock control API.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Add binding for Aspeed AST10x0 clock driver. The clocks can be turned
on or off through the syscon registers.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
The stm32f303x8 SoC is not equipped with spi2 and spi3 peripherals.
Exclude them from the SoC-level devicetree.
Signed-off-by: Jan Kuliga <jtkuliga@gmail.com>
Add the octospi nodes to the stm32h7A3 and
and h7B0/h7B3 devices.
Note that RM0455 gives a size of 1kB.
The definition of the octospi clock source for both intances
is given by the DTS node. The selected value for
the alternate clock control is the PLL1_Q.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the octospi nodes to the stm32h723/h725
and h730/h733/h735 devices.
Note that RM0468 gives a size of 1kB.
The definition of the octospi clock source for both intances
is given by the DTS node. The selected value for
the alternate clock control is the PLL1_Q.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The UC8176 and UC8179 chips that exist in tree have subtly different
register layouts. Use separate compatible strings for these chips and
a quirks structure that describe device-specific behavior.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
The GD7965 driver is really just a vendor name for the UltraChip
UC8179. Rename the driver to UC81xx since there are other chips in the
family (e.g., the UC8176) with an almost identical register interface.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
For the !SOC_I2C_SUPPORT_HW_CLR_BUS in which we implement bus
reset via GPIOs, change the devicetree properties to be actual
gpio properties and update the code to reflect this.
Signed-off-by: Kumar Gala <galak@kernel.org>
This commit adds the pll2 and pll3 clock control nodes
with st,stm32u5-pll-clock compatible.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit changes the range for stm32u5 pll divider values
to allow divider value of 1.
- DIVQ is allowed to beconfigured 1 for all PLL instances
- DIVR can be 1 for PLL2 and PLL3, but is not valid for PLl1.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
