Currently the only way for a BOARD/SOC to configure at compile time the
MPU regions is to add, in a soc-specific file, the 'mpu_config' struct
adding static entries for the new regions with the needed attributes
(cacheable, non-cacheable, etc...). This exported struct is then read by
the MPU driver at boot time and used to properly setup the MPU regions.
At the same time it is now possible to introduce new memory regions in
the DT using the newly introduced 'zephyr,memory-region' attribute.
What is missing is the link between these two solutions: that is how to
declare the memory regions in the DT and automatically configure these
regions in the MPU with the correct attributes.
This patch is trying to address exactly this problem.
It is now possible to declare the memory regions in the DT and define
the MPU attributes for the regions using the 'zephyr,memory-region-mpu'
property. When this new property is present together with the
'zephyr,memory-region' property and a the 'zephyr,memory-region'
compatible, the 'mpu_config' struct is automatically extended at
compile-time to host the DT defined regions with the correct MPU
attributes.
So for example in the DT we can now have:
sram_cache: memory@20200000 {
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x20200000 0x100000>;
zephyr,memory-region = "SRAM_CACHE";
zephyr,memory-region-mpu = "RAM";
};
and a new region will be created called "SRAM_CACHE" and a new MPU
region will be configure at boot time with the attribute
"REGION_RAM_ATTR".
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add a new boolean devicetree property `tx-rx-swap` to the
st,stm32-usart binding, used to control TX/RX swap during
device initialization.
Signed-off-by: Alexander Mihajlovic <a@abxy.se>
Add boolean properties to the binding for the nRF RADIO peripheral
to indicate whether the following features are supported:
- IEEE 802.15.4 mode
- 2 Mbps BLE mode
- coded BLE PHY
- high TX power settings
Set these properties appropriately in devicetree radio nodes for all
nRF SoCs.
Add also such properties and set them in appropriate nodes for nRF
flash controllers to indicate whether they support partial erase.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
For consistency with the scheme used for other nRF peripherals,
use the peripheral name that nRF Product Specifications use.
In this case, it is WDT, not WATCHDOG.
Also remove the requirement for the label property in the binding.
It is no longer needed.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add missing devicetree nodes representing the following peripherals
in nRF SoCs:
- ACL
- BPROT
- CCM
- COMP/LPCOMP
- CTRLAP
- DCNF
- MPU (nRF MPU peripheral in nRF51 Series, not ARM MPU)
- MUTEX
- MWU
- NFCT
- OSCILLATORS
- POWER (in nRF51 and nRF52 Series)
- PPI
- RESET
- SWI
- USBREG
Add also corresponding bindings and validation of base addresses of
these nodes.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This is a follow-up to commit cf6a58d3f6.
Restore the "nordic,nrf-ipc" compatible property in mbox nodes for both
nRF5340 cores and use it together with the new "nordic,mbox-nrf-ipc"
one. This way either the MBOX or the IPM driver can be used for these
nodes without further modifications. This eliminates the need to use
overlays in quite a few cases, so remove all those no longer needed
ones (which are also a bit confusing now as they refer to no longer
existing ipc@2a000 and ipc@41012000 nodes).
Restore also the ipc node label removed in the commit mentioned above,
as the label is used in validation of base addresses of nRF DT nodes.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Adds an initial driver for HDA streams on cAVS. A common code base is
provided for all HDA streams while the drivers are identified
differently as they have small behavior differences.
Uses dma_status to describe the positions for read/write. Uses dma_reload
to inform when to move the read/write positions. This closely follows
how HDA is being used in SoF
Simple test case is provided for both drivers.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Since the HCI entropy device is a software construct that is able to
provide entropy bytes by retrieving them from a Bluetooth Controller,
generalize it by moving it to the Nordic common DTS code. Additionally
move the chosen nodes from the nRF5340 DK board files to the SoC ones.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Add build time optional PINCTRL support to the Microchip XEC TACH
driver shared by MEC15xx and MEC172x families.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Update Microchip XEC TACH driver to support MEC172x.
Standardize device tree properties between chips.
Standardize device structure usage.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Depending on the stm32 mcus and the timer instance, several channels
can enable the complementary output for the PWM signal.
Example of a DTS <&pwm1 2 4 (PWM_POLARITY_NORMAL | PWM_COMPLEMENTARY)>;
Note that the timer channel must support the complementary output
on that channel : usually channels 1-3 + channel 4 on stm32g4x.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Customize busy wait timer for micro-seconds accuracy.
Verified by follow test pattern:
west build -p auto -b it8xxx2_evb tests/kernel/timer/timer_api
west build -p auto -b it8xxx2_evb tests/kernel/timer/timer_error_case
west build -p auto -b it8xxx2_evb tests/kernel/timer/timer_monotonic
west build -p auto -b it8xxx2_evb tests/kernel/timer/starve
west build -p auto -b it8xxx2_evb tests/kernel/context
west build -p auto -b it8xxx2_evb tests/drivers/adc/adc_api
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Add devicetree node for IPC driver so that the IPC interrupt properties
can be accessed with device tree interrupt property macros and
configured using devicetree overlays.
Signed-off-by: Eivind Jølsgard <eivind.jolsgard@nordicsemi.no>
Co-authored-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Follow up on commit 37bf7cb
("dts/bindings: stm32: Set pinctrl-[0/names] properties as required")
Report lack of those fields soon at build to avoid cryptic
DT api build error messages.
Signed-off-by: Maciej Zagrabski <maciej.zagrabski@grinn-global.com>
Instead of having one single WQ per backend, move to one WQ per
instance instead and add a new "zephyr,priority" property in the DT to
set the WQ priority of the instance. Fix the sample as well.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add Nano header connector defined by Arduino. This allows
hardware with compatible headers to define the related GPIOs.
Signed-off-by: Marco Peter <marco.peter@joylab.ch>
Add description for a plain GPIO configuration using
st,stm32-pinctrl and st,stm32f1-pinctrl bindings.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add backlight gpios property to mcux display driver, so that the driver
can correctly initialize the backlight gpio control.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
In order for pinctrl support to be complete, RT series GPIO driver must
support pinmuxing within the driver level. RT series pinmux settings do
not correspond directly to gpio port/pin numbers, so use DTS mappings to
pinctrl nodes to select and apply pinmux settings in the gpio driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable pinctrl driver for usdhc. USDHC driver uses custom pinctrl states
for fast, slow, and medium signal frequencies, as well as pin pull for
SD detection.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable pinctrl for flexspi driver. Note that when flexspi is being using
in XIP mode, pinctrl settings are not required and will not be applied.
Pinctrl settings are only required when the flexspi device being used is
not the one used for XIP.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
RT11xx series has similar pin configuration peripheral to RT10xx, with
some differences in register layout. Create new pinctrl definition
header file, and reuse existing driver code for RT10xx.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
iMX.RT parts use a GPR register for some pinmux settings. Update pinctrl
driver to support this GPR register definition.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
OCRAM can be used for DMA, and in this case it should be marked as
noncacheable. Add KConfig symbol and appropriate linker scripts to
enable OCRAM region to be defined as noncacheable, and initialized with
data from flash at boot.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
