Enable serial interface on i.MX8ULP.
This also includes a SHA update for hal_nxp which
pulls in the following commits relevant to Zephyr:
* 3366f234ed47 build: hal_nxp: add TPM counter support
* 6544455fcf46 Compile in PXP driver if LVGL is set to use
PXP.
* 31463a848bcd devices: MIMX8UD7: add definition for
LPUART_RX_TX_IRQS
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit enables pinctrl on i.MX8ULP. This includes:
1) Adding `pinctrl_soc.h` header file.
2) Adding DTS node for IOMUXC1, which is one of the
IPs responsible for managing the 8ULP pads.
3) Adding .dtsi with pin definitions. For now, only
the LPUART7 pads are added to this file because this
is going to be the only consummer for now.
4) Modifying the `pinctrl_imx.c` driver to work for 8ULP.
5) Enabling the `CONFIG_HAS_MCUX_IOMUXC`, which is a
dependency of `CONFIG_PINCTRL_IMX`.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Enable clock control for i.MX8ULP. This consists of:
1) Adding a PCC node in the DTS
2) Adding a header file containing the definitions
of the clocks used by the peripherals to be enabled.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit enables the IRQSTEER interrupt controller
on NXP's XTENSA-based i.MX8QM and i.MX8QXP.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit introduces a new interrupt controller driver used
for NXP's IRQ_STEER IP.
Apart from introducing the driver itself, this commit contains
the following changes:
1) Switch i.MX8MP to using the XTENSA core interrupt
controller instead of the dummy irqsteer one.
* this is required because the binding for the
irqsteer driver is no longer a dummy one
(since it's being used by the irqsteer driver).
As such, to avoid having problems, switch to
using another dummy binding.
2) Modify the irqsteer dummy binding such that it
serves the IRQ_STEER driver's needs.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add dummy interrupt id until we can support UART interuppt
on i.MX8MP in order to fix compilation warnings.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
This commit introduces all changes necessary for utilizing
the serial interface on i.MX8QM/QXP.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Since the LPUART peripheral DTS binding requires the
"interrupts" property be specified even if it's not going
to be used for now we need to add a dummy interrupt controller
node to make that possible. Logically speaking, this dummy
interrupt controller should be used by peripherals which
can assert interrupts directly routed to the DSP.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit enables clock control on the i.MX8QM and QXP boards.
This is achieved through the following changes:
1) The "reg" property is no longer marked as required
for the "nxp,imx-ccm" binding. This is necessary because
in the case of i.MX8QM and i.MX8QXP the clock management
is done through the SCFW, hence there's no need to access
CCM's MMIO space (not that you could anyways).
2) The DTS now contains a scu_mu node. This node refers
to the MU instance used by the DSP to communicate with
the SCFW.
3) The CCM driver needs to support the LPUART clocks
(which will be the only IP that's supported for now)
and needs to perform an initialization so that the
NXP HAL driver knows which MU to use to communicate
with the SCFW.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Remove nxp,imx-mu-rev2 compatible. This IP block is the same as the
nxp,imx-mu device, and should be handled by the same compatible
Instead, use CONFIG_HAS_MCUX to determine which HAL APIs should be used
to interact with the messaging unit IP.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add mailbox and interrupt-controller nodes used for
inter-process communication.
Add also the dt binding for the interrupt-controller.
For now, this is used just to fix some compile errors,
since the mailbox requires an interrupt-controller.
For DSP, we have a direct interrupt line to the core.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Enable UART on the DSP from the i.MX8MP target:
- add corresponding nodes in dtsi and dts;
- create a dts overlay for uart;
- add a config fragment for uart and console configuration.
So, in order to compile an application and enable UART
a user must run west build using DTC_OVERLAY_FILE and CONF_FILE.
Here's an example for hello_world:
west build -p always -b nxp_adsp_imx8m samples/hello_world/
-DDTC_OVERLAY_FILE="boards/xtensa/nxp_adsp_imx8m/
nxp_adsp_imx8m_uart.overlay" -DCONF_FILE="boards/xtensa/nxp_adsp_imx8m/
nxp_adsp_imx8m_uart.conf"
For other applications, like SOF, where we don't need UART, we simply run:
west build -p always -b nxp_adsp_imx8m ../modules/audio/sof/ --
-DTOOLCHAIN=/opt/zephyr-sdk-0.15.2/xtensa-nxp_imx8m_adsp_zephyr-elf/
bin/xtensa-nxp_imx8m_adsp_zephyr-elf -DINIT_CONFIG=imx8m_defconfig
The nxp_adsp_imx8m is using the nxp_imx_iuart driver.
For now, is used in poll mode.
Next step is to enable the interrupt controller in
DSP and use the interrupt driver UART.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
In order to bring consistency in-tree, migrate all dts code to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to zephyrproject-rtos#45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add dtsi file for i.MX8MP board.
This has one HiFi4 core, from Cadence, lx6 compatible
and 2 System RAM.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Add dtsi file for i.MX8QM and i.MX8QXP boards.
These two have the same board-level definitions,
so we call it, generically, imx8.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
