The new ace30 files structure is organized as follows:
intel_adsp_ace30.dtsi - main file for all variants
intel_adsp_ace30_ptl.dtsi - additional file for PTL variant
intel_adsp_ace30_wcl.dtsi - additional file for WCL variant
The main ace30.dtsi file contains most of the fields,
with only the differences specified in the ace30_ptl.dtsi
and ace30_wcl.dtsi files.
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
This patch modifies the DTS files for Intel ADSP ACE 3.0 platforms,
ensuring the power-states node is a child of the cpus node. This change
aligns with Linux conventions and mirrors the adjustments made in commit
e4c43e4cc9 for other platforms.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch refactors the power management initialization for the SSP
driver across ACE15, ACE20, and ACE30 generations to align with the
recommended practices outlined in the documentation. The changes
include:
1. Replacing the conditional initialization of power management state
with a call to `pm_device_driver_init` in the `ssp_init` function.
2. Adding the `zephyr,pm-device-runtime-auto` property to the SSP nodes
in the device tree files for ACE15, ACE20, and ACE30.
3. Moving the power domain assignment for the SSP device in the device
tree. The previous configuration resulted in the device not being under
any power domain and being initialized as always ON.
These changes ensure that the SSP driver is initialized with the
appropriate power management state and that runtime power management is
automatically enabled based on the device tree configuration. The
functionality of the power management state remains unchanged, ensuring
consistent behavior.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch refactors the power management initialization for the DMIC
driver across ACE15, ACE20, and ACE30 generations to align with the
recommended practices outlined in the documentation. The changes
include:
1. Replacing the conditional initialization of power management state
with a call to `pm_device_driver_init` in the
`dai_dmic_initialize_device` function.
2. Adding the `zephyr,pm-device-runtime-auto` property to the DMIC nodes
in the device tree files for ACE15, ACE20, and ACE30.
These changes ensure that the DMIC driver is initialized with the
appropriate power management state and that runtime power management is
automatically enabled based on the device tree configuration. The
functionality of the power management state remains unchanged, ensuring
consistent behavior.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch addresses several issues with the Intel ADSP HDA DMA driver:
1. Refactors the HDA DMA power management initialization. The previous
use of `pm_device_runtime_enable` was incorrect. The updated approach
relies on enabling runtime power management through the device tree
using the `zephyr,pm-device-runtime-auto` property. Additionally, the
patch removes redundant device initialization steps as these are already
handled by `pm_device_driver_init` when the device is under a power
domain.
2. Corrects the power domain assignment for the HDA link. The HDA link
was previously assigned to the io0 power domain based on a
misinterpretation of the documentation. The correct power domain
assignment is now based on updated documentation for LNL, ensuring that
the HDA link is associated with the appropriate power domain.
These changes ensure that the HDA DMA driver properly manages power
states, reducing power consumption and improving system stability, while
ensuring the correct power domains are used.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch addresses the following issues with the Intel HDA DAI driver:
1. Adds power management support for the HDA DAI driver by implementing
the `hda_pm_action` function and integrating it with the Zephyr power
management framework.
2. Ensures balanced calls to `pm_device_runtime_get` and
`pm_device_runtime_put` by modifying the `probe` and `remove`
functions to use these power management calls.
3. Ensures that the io0 power domain is active when the HD Audio is in
use by assigning the correct power domain to the HDA DAI devices in
the device tree files for various Intel ADSP platforms (ace15_mtpm,
ace20_lnl, ace30, ace30_ptl).
4. Enables runtime power management for the HDA DAI devices by adding
the `zephyr,pm-device-runtime-auto` property in the device tree.
These changes ensure that the HDA DAI driver properly manages power
states, reducing power consumption and improving system stability, while
ensuring the io0 power domain is active when required.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit introduces the L2 Memory Capabilities (hsbcap) register node
to the Devicetree specifications for Intel ADSP ACE platforms. The
hsbcap register provides information on the general capabilities
associated with the L2 memory, which is critical for system
configuration and resource management. The hsbcap node has been added to
the Devicetree source files for ACE 1.5 (MTPM), ACE 2.0 (LNL), and ACE
3.0 (PTL) platforms.
In addition, the DFL2MM_REG macro in adsp_memory.h has been updated to
use the Devicetree node label for hsbcap, ensuring a consistent and
maintainable approach to accessing this register across the codebase.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Some devices may belong to >1 power domain, so with the current design
this is something not possible to describe. It's worth to note that
Linux also uses the `power-domains` naming scheme, not `power-domain`.
This patch also introduces `power-domain-names` so that each entry in
`power-domains` can be given a name if needed. `#power-domain-cells`
is now required as well.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Renamed soc from ace30_ptl to ace30.
We were previously using the wrong soc name.
The correct name is ace30.
There is only one ptl platform, but there can be several ace30 platforms.
Signed-off-by: Grzegorz Bernat <grzegorzx.bernat@intel.com>
The 'soft-off' state must be used when explicitly request by calling
`pm_state_force`. Set this state as disabled in dts ensures that the
pm policy manager will not use this state.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Programming of the MLCS register was performed on the incorrect bits.
Additionally, saving the new version did not erase the previously set
value, which could result in an incorrect register value.
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
This patch removes definitions of power domains from the ACE30 PTL DTS
file that do not exist in the actual hardware.
The following power domain nodes have been removed:
- 'ml1_domain' with a bit-position of <13>
- 'io3_domain' with a bit-position of <11>
- 'io2_domain' with a bit-position of <10>
These nodes were previously included in the DTS file but do not
correspond to any physical power domain in the ACE30 PTL hardware. Their
presence in the DTS could lead to confusion and misconfiguration, as the
software might attempt to interact with non-existent hardware features.
By removing these nodes, the DTS now accurately reflects the hardware
capabilities of the ACE30 PTL platform, ensuring that the power
management infrastructure within the firmware operates based on the
correct hardware configuration.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Remove the Audio Link Hub (ALH) nodes from the ACE 3.0 PTL DTS file.
This patch cleans up the Device Tree Source (DTS) for the ACE 3.0 PTL
platform by removing the definitions of the ALH DAI nodes. The ALH
interface is not utilized in the ACE 3.0 PTL architecture, making these
nodes redundant.
The following changes are made:
- Deleted the 'alh0' and 'alh1' nodes, which were previously defined
with FIXME comments indicating a problematic modeling of individual
ALH channels/instances using node labels.
This cleanup helps to prevent confusion and potential errors in device
configuration by ensuring that the DTS reflects the actual hardware
capabilities of the ACE 3.0 PTL platform.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Rearrange the power domain entries in the ACE30 PTL device tree source
file to be in ascending order according to their bit positions. This
reordering improves the readability of the device tree source by
grouping power domains logically according to their bit position within
the power management registers.
The changes in this patch include:
- Moving 'ml1_domain' and 'ml0_domain' to their correct positions
according to their bit-position values (13 and 12, respectively).
- Adjusting the order of 'io3_domain', 'io2_domain', 'io1_domain', and
'io0_domain' to reflect their bit positions (11, 10, 9, and 8).
- Placing 'hub_hp_domain' and 'hst_domain' at their new positions
according to their bit-position values (6 and 5).
No functional changes are introduced with this patch. It solely aims to
make the device tree source more intuitive and easier to navigate when
mapping power domains to their respective control bits.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit refactors the SSP driver to support the Intel ACE30 PTL
platform. The changes include:
- Adding new structures ssp_rx_dir and ssp_tx_dir to hold the TDM
slot configuration for RX and TX directions
- Adjusting the dai_ssp_set_config_blob functions to work with
the new TDM slot configuration.
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
adsp_memory.h is pretty much the same for all ace platforms.
Generalize it getting register address from devicetree and
and move it to a common place.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This commit refactors the Intel SSP DAI driver to support dynamic
management of SSP IP. This change additionally separates the
management of the DAI part from the management part of the SSP IP.
Key changes:
- Add new static functions to manage SSP IP power.
- Update the DAI SSP configuration functions to use the new management
approach.
- Update device tree bindings and instances to reflect the new SSP IP
management mechanism.
- ace30 (PTL) support.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
This commit adds definition of ACE 3.0 Panther Lake board.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Secondary cores are not allowed to be power gated on
runtime-idle. They have to explicitely set off by host command.
Remove this state from secondary CPUs so power management logic
does not need workarounds to enforce this behavior.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This commit updates the device tree and memory header file
for the Intel MTPM 1.5 platform to define the LSBPM and
HSBPM registers.
Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_ace15_mtpm.dtsi
- Updated adsp_memory.h
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
This commit updates the device tree and memory header file
for the Intel LNL 2.0 platform to define the LSBPM and
HSBPM registers.
Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_ace20_lnl.dtsi
- Updated adsp_memory.h
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
This commit updates the device tree and memory header file
for the Intel cAVS 2.5 platform to define the LSBPM and
HSBPM registers.
Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_cavs25.dtsi and intel_adsp_cavs25_tgph.dtsi
- Updated adsp_memory.h
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
This commit refactors the Intel SSP DAI driver to support dynamic
management of SSP IP. This change additionally separates the management
of the DAI part from the management part of the SSP IP.
Key changes:
- Add new static functions to manage SSP IP power.
- Update the DAI SSP configuration functions to use the new management
approach.
- Update device tree bindings and instances to reflect the new SSP IP
management mechanism.
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
The ace20 description has incorrect number of SSP instances
described. Correct number should be 3.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The ace15 description has incorrect number of SSP instances
described. Correct number should be 3.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The tgph description has incorrect number of SSP instances
described. Correct number should be 3.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Configure the 'soft-off' power state for manual selection only in the
DTS for Intel ADSP ACE 1.5 MTPM and ACE 2.0 LNL platforms.
Changes include:
- Setting 'min-residency-us' to 0 to indicate that the 'soft-off' state
is not intended for automatic selection by the power management
policy.
- Adding a 'status' property set to "disabled" to prevent the power
management policy from using this state during its decision process.
The 'soft-off' state remains available for manual selection by calling
`pm_state_force`. This change ensures that the state can still be used
when explicitly requested by the system or application, providing
flexibility for power management operations.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This will update host dma copy aligmnet as with current
high value in some cases it was not possible to fully
empty the buffer
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Remove the Audio Link Hub (ALH) nodes from the ACE 2.0 LNL DTS file.
This patch cleans up the Device Tree Source by removing the individual
ALH stream/FIFO nodes. The ALH hardware is not present in the ACE 2.0
architecture, and these nodes are therefore not applicable.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch reorders the power domain definitions for the Intel ADSP ACE
2.0 LNL (Lunarlake) platform in the Device Tree Source (DTS).
Changes include:
- Removing the definitions for io2_domain, io3_domain, and ml1_domain,
which are no longer present in the ACE 2.0 LNL configuration.
- Renaming and reassigning bit positions to existing power domains to
reflect the updated power management architecture.
The reordering ensures that the DTS reflects the current power domain
architecture of the ACE 2.0 LNL platform, facilitating accurate power
management within the SoC.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Changing the power domain from 'hst_domain' to 'io0_domain' for the HDA
DMA link in/out nodes. This aligns the power domain assignments with the
actual hardware configuration and ensures that the power management
subsystem can accurately manage the power states of these interfaces.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch reorders the power domain node definitions in the ACE 1.5
Meteorlake DTS file to improve readability and facilitate comparison with
the documentation.
Changes include:
- Reordering power domain nodes by their bit positions.
- No changes to the bit positions themselves; they remain as originally
defined.
This reordering does not affect the functionality but makes the DTS file
more maintainable and easier to cross-reference with the hardware
specification.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
DW watchdog driver is not used on ACE,
Intel ADSP watchdog driver will be used in DTS when ready to use
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Fix the following compilation warning:
```
Warning (unit_address_format): /memory@0xb0000000: \
unit name should not have leading "0x"
```
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
LP/HP RING OSC clocks were replaced by the ACE IPLL clock.
If needed IPLL can be configured to work as low power clock. But right
now ACE uses only WOVCRO and IPLL (configured to work as HP RING OSC
clock).
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
LP/HP RING OSC clocks were replaced by the ACE IPLL clock.
If needed IPLL can be configured to work as low power clock. But right
now ACE uses only WOVCRO and IPLL (configured to work as HP RING OSC
clock).
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The ACE family platforms do not have LP/HP RING OSC clocks. They were
replaced by the ACE IP integrated PLL clock. Selecting LP or HP in
CLKCTL will result in enabling IPLL.
Clock can supply frequencies for both replaced clocks, default frequency
equals to 393.2 MHz.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The ACE family platforms do not have LP/HP RING OSC clocks. They were
replaced by the ACE IP integrated PLL clock. Selecting LP or HP in
CLKCTL will result in enabling IPLL.
Clock can supply frequencies for both replaced clocks, default frequency
equals to 393.2 MHz.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Add missing definitions for ALH DAIs. Keep the same FIXME
reminder in the comments we have for ACE1.5 that explains
the background of these definitions.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reported-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
To properly setup L1 exit timing this patch will use buffer interrupt
for HOST DMA and wait for Host HDA to actually start
First interrupt will clear all others.
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
On ACE a seperate, soc specific, interrupt mask needs to be enabled
to unmask the interrupt. Do so for GPDMA.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
