RV3032 PMU register should be set from DTS info, but is always being
set to 0 which prevents backup power source configuration.
Restore building PMU reg from DTS.
Signed-off-by: Jacob Schloss <jacob.schloss@suburbanmarine.io>
Set the OSPI memory mapped timeout period to avoid keeping the chip
select line asserted indefinitely after memory mapped accesses.
This is needed when OSPI1 and OSPI2 operate simultaneously with shared
IO0-IO3 and CLK lines, and both instances use memory mapped mode.
The timeout period follows the recommendation from the STM32U575xx and
STM32U585xx device errata, ES0499 section 2.6.4.
Allow dqs-port to be set to 0. The STM32 HAL uses value 0 to indicate
that the DQS port is not used.
Update the debug log printed when CONFIG_STM32_MEMMAP is not enabled,
because stm32_ospi_set_memorymap() is not called in that case.
Signed-off-by: Kirill Shypachov <kshypachov@outlook.com>
The EFM32HG (Series 0) WDOG has no IRQ support, no window mode
and no reset-disable bit.
Guard the logic with HAL feature macros and use `IF_ENABLED` with
`DT_INST_IRQ_HAS_IDX` for conditional IRQ setup.
Add the `wdog0` node to the EFM32HG device tree.
Signed-off-by: Patryk Koscik <pkoscik@antmicro.com>
Adds support to the infineon i2s driver for arbitrary memory block
sizes. The driver was previously limited to block sizes that matched the
hardware FIFOs.
Signed-off-by: Brett Peterson <brett.peterson@infineon.com>
Add a generic I2C_TRANSFER_TIMEOUT_MS option, not tied to any specific
driver, as well as a I2C_TRANSFER_TIMEOUT helper to handle conversions
and infinite timeout and a helper for driver that only supports finite
timeouts.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
As mentioned in the i2c_burst_write documentation, this API may not be
supported by all I2C devices. The recommendation from this documentation
is to use i2c_write with a buffer containing the combined address and
data.
The ssd1306 driver was working well when using I2C but not when using
I2C over I3C. In this case, the control command was sent in a separate
transaction, which the SSD1306 does not support. To fix this issue, we
should apply the recommended approach and use i2c_write instead of
i2c_burst_write. The solution implemented uses chunks to avoid stack
overflow when using large buffers (it can be up to 1 kB).
Signed-off-by: Tanguy Raufflet <tanguy.raufflet@savoirfairelinux.com>
the plca related api functions are only needed
for T1S ethernet phys, therefore hide them
behind a Kconfig, that is selected from the phy,
so we don't include these if they are not needed.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
This fix adds a macro for writing register updates in big endian
at compile-time to fix an issue with multi-device configurations.
Previously, the I2C write function would flip the byte order of
arrays unconditionally, which is problematic if arrays are shared
across instances of a driver. Adds a new "raw write" for I2C
transactions where the uint32_t array to write is already in BE32
format.
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
Addresses checkpatch and related warnings, including:
- Update select files within Cirrus haptics subdirectory to not have
execute permissions.
- Fixes identified warnings by adding `const` where appropriate.
- Add `__maybe_unused` qualifiers where appropriate.
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
Because I2C- and SPI-related source files only need to be compiled
if corresponding Kconfig options are enabled, update CMakeLists.txt
accordingly.
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
Add support for software resets in case no reset GPIO can be provided.
Add a mailbox write to prevent hibernation during bringup because
we can no longer rely on a hardware reset to make sure the device is
not hibernating.
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
Rather than return the current logging state on success and an
error code on failure (without real benefit), simplify the
function to return success or failure, which also simplifies
the implementation.
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
This interrupt indicates that the current was limited, not that
an overcurrent condition was detected. Since it is not a fatal
error, remove the addition to error_bitmask and correct the
language.
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
The initial driver implementation used ring buffers, kept a private
variable to count "effects in flight", and register GPIO callbacks
to log playback events, but these ultimately bloat the driver and
introduce new issues where a dropped start or complete playback can
force the driver into a bad state. Additionally, the mailbox events
already provide sufficient log information if needed. As a result,
let's simplify the driver's logging mechanisms.
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
The register and address width macros are used across files, so
remove duplicates and expose in the private header file.
Ensure macros match the datasheets where appropriate, and
organize the macros more clearly. Add unsigned specifiers for
clarity.
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
Split the generic cirrus,cs40l5x compatible into device-specific
variants. Update the driver and Kconfig accordingly. Update the
CRD40L50 demonstration board's compatible to cirrus,cs40l50. Move
the device ID from the data struct to the config struct. Move uses
of DT_ANY_INST_HAS_PROP_STATUS_OKAY() and similar macros from the
device driver to Kconfig to support new DT_DRV_COMPAT usage in the
driver.
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
Many structures and functions in the public CS40L5x do not need to be
exposed to userspace. Split the header accordingly into private
and public headers, and remove comments accordingly.
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
If the channel setup function is called while an ADC conversion is
on-going, it can lead the system to hang indefinitely. Prevent this by
adding a locking mechanism on the setup function, similar to what is
done for the read function.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This macro is now called "SAI_MASTERDIVIDER_DISABLE" (no 'D' at the end);
stop using the old name which only worked thanks to the HAL Legacy
definitions header.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The custom arm_arch_timer arch_busy_wait() computed the wait duration as:
cycles_to_wait = sys_clock_hw_cycles_per_sec() / USEC_PER_SEC *
(uint64_t)usec_to_wait;
Integer division applied first. When the timer frequency is not an
integer multiple of USEC_PER_SEC (e.g. 62.5 MHz on Cortex-A53), the
fractional cycles-per-microsecond are silently dropped, making every
call to k_busy_wait() return short by up to 0.8% of the requested
duration -- breaking the API contract that busy_wait() is guaranteed
to wait at least the requested number of microseconds.
Replace the open-coded conversion with k_us_to_cyc_ceil64(), which
multiplies first and rounds up, so the resulting cycle count always
covers at least the requested microseconds.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Introduce a PECI transport driver that operates over the eSPI bus,
enabling platforms without a native PECI controller to communicate
with the host CPU via an embedded controller.
This driver:
- Implements the PECI transaction layer on top of eSPI OOB channel
- Serializes PECI transactions to ensure protocol correctness
- Integrates with the existing PECI core infrastructure
- Allows PECI consumers (e.g. DTT, thermal, power management) to remain
transport-agnostic
A corresponding devicetree binding enables PECI-over-eSPI by defining
a PECI child node under the eSPI controller node.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
set BUF21 mode after enabling regulator, to ensure the buffered
output is available for the LPADC's VREFI reference.
This fixes an issue where the LPADC would produce inaccurate
conversion results due to BUF21 being left disabled.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add an invert-direction boolean DT property that negates the axis value
reported by the event worker. This handles boards where the physical
encoder orientation produces a direction opposite to what the quadrature
state machine reports without swapping the A/B GPIO wires.
Signed-off-by: Andrew Yong <me@ndoo.sg>
Fix the test on the number of arguments in the erase command
to get the optional size argument that was mistakenly increased by
cb2382d25b ("drivers: flash: flash_shell.c: Requires device on
destructive ops") and made the argument never considered.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
as the ethernet api already includes
struct net_if as a argument for its
functions also add it to struct wifi_mgmt_ops.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Introduce CONFIG_RISCV_S_MODE to select Supervisor-mode execution.
Add depends on !RISCV_S_MODE to RISCV_PMP since PMP CSRs are
inaccessible from S-mode.
Add an M-mode SBI shim (reset.S + sbi.S) that configures exception
delegation, PMP, and counter access before dropping to S-mode via mret.
The shim handles SBI_SET_TIMER ecalls from S-mode and forwards MTIP to
STIP so the supervisor timer driver works without a full SBI firmware.
Introduce privilege-level abstractions in isr.S (RV_CAUSE, RV_EPC,
RV_STATUS, RV_TVAL, etc.) and update all runtime code that previously
accessed M-mode-only CSRs (mcause, mtval, mstatus, mie, mip) to use the
S-mode equivalents when CONFIG_RISCV_S_MODE is set.
ARCH_EXCEPT in kernel context uses ebreak (cause=3, Breakpoint) instead
of a direct z_riscv_fatal_error() call. In S-mode, ecall (cause=9) is
kept in M-mode for SBI and never reaches the S-mode exception handler;
a direct call with NULL esf caused the stack unwinder to crash into an
infinite fault loop. ebreak is delegated to S-mode by our medeleg
configuration; isr.S treats ebreak with t0=RV_ECALL_RUNTIME_EXCEPT the
same way M-mode treats ecall-based ARCH_EXCEPT.
Signed-off-by: Alexios Lyrakis <alexios.lyrakis@gmail.com>
-Add inband independent reset support for IW612, IW416 and IW610
-Add kconfig option to enable/disable IR support
Signed-off-by: Vinit Mehta <vinit.mehta@nxp.com>
Add function to read the state of the monitored external power at startup.
Needed when controller can startup with monitored external power rails
beeing powered or not. The actual read of the state is not done during
init but deferred to a later stage after all child devices of this power
domain are also initialized and are able to receive a PM action callback.
A Kconfig switch CONFIG_POWER_DOMAIN_GPIO_MONITOR_INITIAL_READ is
introduced to optionally turn on this feature.
Signed-off-by: Thomas Decker <decker@jb-lighting.de>
The new hardware supports fifo mode for all i2c channels. This commit
adds support for fifo mode across all i2c channels.
Additionally, the compilation fails when the `I2C_IT51XXX_FIFO_MODE`
option is disabled because the isr function is behind this option.
This change also resolves this issue.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Explicitly casting a `const void *` to an end data type is unnecessary,
introduces the opportunity to mis-cast the `const` qualifier and goes
against the direction decided in:
https://github.com/zephyrproject-rtos/zephyr/issues/37616
Signed-off-by: Jordan Yates <jordan@embeint.com>
Explicitly casting a `const void *` to an end data type is unnecessary,
introduces the opportunity to mis-cast the `const` qualifier and goes
against the direction decided in:
https://github.com/zephyrproject-rtos/zephyr/issues/37616
Signed-off-by: Jordan Yates <jordan@embeint.com>
- Add DMA support for SPI on RZ/N2L, T2M since the previously supported
had not support DMA.
- Add initial support SPI driver for board RZ/T2L.
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
- Introduce support for the DesignWare I2C specific core clock frequency
optimization feature (IC_CLK_FREQ_OPTIMIZATION).
- This feature reduces the internal latency cycles required to generate
the SCL high and low periods, allowing the controller to achieve target
bus speeds with a lower input clock (ic_clk) frequency.
- The driver now supports both standard calculation (optimization=0) and
the new optimized mode, selectable via Kconfig. This ensures
compatibility with existing hardware while enabling the optimization
on platforms that support it.
Signed-off-by: Shreehari HK <shreehari.hk@alifsemi.com>
- Replace hardcoded magic numbers for SCL High and Low Count register
minimum values with descriptive macros.
- The DesignWare I2C controller requires specific minimum values
(Section 2.14.1 of DW Spec) for IC_*_SCL_HCNT and IC_*_SCL_LCNT
registers based on the spike length (SPKLEN) configuration.
Specifically:
- HCNT must be at least IC_*_SPKLEN + 6
- LCNT must be at least IC_*_SPKLEN + 8
- Using macros improves readability and maintainability by documenting
the source of these constraints and ensuring consistency across the
driver.
Signed-off-by: Shreehari HK <shreehari.hk@alifsemi.com>
