On Apollo Lake, each GPIO controller has more than 32 pins.
But Zephyr API can only manipulate 32 pins per controller.
So the workaround is to divide each hardware GPIO controller
into 32-pin blocks so each block has a GPIO driver instance.
Compounding to the issue is that there cannot be two device
tree nodes with same register address. So another workaround
is to increment the register addresses by 1 for each block.
So when mapping the address, the lowest 8-bit needs to be
masked to get the actual hardware address.
Fixes#28551
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
In case of multi-instance the driver tries to discover whether
there are devices attached to SDx/SCx sensorhub bus. If not it
just turns the shub_inited variable (inside data structure) to false
and skips doing any further sensorhub related action for that
particular IIS2ICLX device instance, regardless the fact that the
macro CONFIG_IIS2ICLC_SENSORHUB is enabled.
Moreover, the info found during the enumeration process for a
particular instance (number and types of attached devices) must be
saved inside the per-instance data structure, so that more than one
IIS2ICLX device can be used as a sensorhub without interfering with
the others.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
In case of multi-instance the driver tries to discover whether
there are devices attached to SDx/SCx sensorhub bus. If not it
just turns the shub_inited variable (inside data structure) to false
and skips doing any further sensorhub related action for that
particular LSM6DSO device instance, regardless the fact that the macro
CONFIG_LSM6DSO_SENSORHUB is enabled.
Moreover, the info found during the enumeration process for a
particular instance (number and types of attached devices) must be
saved inside the per-instance data structure, so that more than one
LSM6DSO device can be used as a sensorhub without interfering with
the others.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
This avoid IRQ to be handle before iface init is finished
(especially before iface address is set)
Fixes#32771
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
The logging macros use _Generic() atm and it started to complain
when we are trying to print pointer value of gsm_dlci and gsm_mux
structs. Cast the pointer value to (void *) to overcome this.
Fixes#35329
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
uarte_enable function was not supporting a case when async
api was enabled but instance did not use it. Added runtime
check for async instance presence.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Driver was failing when interrupt mode was enabled for given
instance but interrupt driven TX part was not used. In that
case uart was not disabled after sending a byte which resulted
in continuous interrupt triggering. Added check for
fifo_fill_lock which is set when uart_fifo_fill is used.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
The default behavior of the +KSRAT= command has
changed to not reboot the HL7800.
Adjust the command so the reboot takes place properly.
Signed-off-by: Ryan Erickson <ryan.erickson@lairdconnect.com>
This commit fixes the ADC driver flow. And add internal
reference voltage to ADC driver API. And correct the
data buffer that only need to store raw data.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
After i2c_reset, there is still no external pull-up I2C bus,
and finishing off the rest of loop causes the code to hang
indefinitely.
This patch fixes that if I2C bus is not available(No external
pull-up), dropping the transaction.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
-ENOSYS should be returned if the operation is not implemented. This
issue was causing some PM tests to fail, as -ENOSYS was expected.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use gpio_pin_configure_dt() and gpio_pin_interrupt_configure_dt()
for drdy_gpio: they result in a more readable code.
Moreover, this commit includes also the fix for PR #35156
(i.e. CID 235979, add check for gpio_pin_configure() return val).
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Resetting the dma_tx.buffer_length after the dma_tx.counter
calculation, instead of before.
We need to reset the buffer_length when the transmission is finished,
but in order to give the correct value to the uart_event_tx struct,
we use the dma_tx.buffer_length in the calculation of the
dma_tx.counter, used for the len of the event (number of bytes sent).
I found this problem, when I wanted to use the uart_event_tx.len for
freeing the used space inside a ring buffer (ring_buf_get_finish),
and it didn't work, I logged the values of the uart_event_tx struct,
and found out it always was 0, because the buffer_length was 0,
and the whole buffer was transmitted (stat.pending_length also 0).
Signed-off-by: Prema Jonathan van Win <jonathanvanwin@gmail.com>
This commit loops on rx not empty only if rx_buf is enabled.
And if rx_buf is not enabled, it loops on tx empty status.
Signed-off-by: Affrin Pinhero <affrin.pinhero@hcl.com>
In case of the following sequence of UART events:
- UART_ENDRX
- UART_RXRDY
- TIMER_RXTIMEOUT
The application receives one more byte that was received,
due to RX counter alignment upon ENDRX event.
The proposed fix moves the RX byte counter alignment to the
RX timeout event handler.
Signed-off-by: Tomasz Chyrowicz <tomasz.chyrowicz@nordicsemi.no>
Add check to see that the GPIO devicetree node is actually enabled
before we build the PSoC6 GPIO driver.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
If we try and build the MiV uart driver with interrupt support enabled
we get some errors related to code that hasn't been updated. Fix the
compile errors and add SERIAL_SUPPORT_INTERRUPT to the Kconfig to
hopefully catch these issues in the future
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
STM32 internal temperature sensor driver.
This sensor can be used to measure the temperature of the CPU
and its surroundings.
Signed-off-by: Eug Krashtan <eug.krashtan@gmail.com>
In the power mgmt conversion of void *context to uint32_t *state this
driver got missed and shows build errors with power mgmt is enabled.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The cache API currently shipped in Zephyr is assuming that the cache
controller is always on-core thus managed at the arch level. This is not
always the case because many SoCs rely on external cache controllers as
a peripheral external to the core (for example PL310 cache controller
and the L2Cxxx family). In some cases you also want a single driver to
control a whole set of cache controllers.
Rework the cache code introducing support for external cache
controllers.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
In a multi-instance driver it may happen that on some h/w
one device should use interrupts and a second device should use
polling mode. So, CONFIG_LSM6DSO_TRIGGER is not enough to discriminmate
if interrupt inizialization routine should be called or not; the choice
is now based whether the "irq-gpios" property is present in the DT
for that particular instance or not.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Move ctx structure from struct data to struct config, so that
it can be filled at compile time and we could get rid of the bus
init routines.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
NPCX clock has some limitations about the frequency range &
synchronization between core clock & other clocks. Add build assert to
check whether NPCX clock setting correct. This also fixed soc_clock.h
to consist with datasheet.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
If the modem drivers are built on a 64-bit platform we get errors with
the logging code due to use of size_t. Update to use %zX to handle this
correctly between 32-bit and 64-bit platforms.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The context parameter used across device power management is
actually the power state. Just use it and avoid a lot of
unnecessary casts.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Modern hardware all supports a TSC_DEADLINE mode for the APIC timer,
where the same GHz-scale 64 bit TSC used for performance monitoring
becomes the free-running counter used for cpu-local timer interrupts.
Being a free running counter that does not need to be reset, it will
not lose time in an interrupt. Being 64 bit, it needs no rollover or
clamping logic in the driver when presented with a 32 bit tick count.
Being a proper comparator, it will correctly trigger interrupts for
times set "in the past" and thus needs no minimum/clamping logic. The
counter is synchronized across the system architecturally (modulo one
burp where firmware likes to change the adjustment value) so usage is
SMP-safe by default. Access to the 64 bit counter and comparator
value are single-instruction atomics even on 32 bit systems, so it
beats even the RISC-V machine timer in complexity (which was our
reigning champ for "simplest timer driver").
Really this is just ideal for Zephyr. So rather than try to add
support for it to the existing APIC driver and increase complexity,
make this a new standalone driver instead. All modern hardware has
what it needs. The sole gotcha is that it's not easily emulatable
(qemu supports it only under kvm where they can freeload on the host
TSC) so it can be exercised only on hardware platforms right now.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Move LUT to driver.
Update CMake to include SoC specific driver.
Fix mimxrt685_evk LUT header spacing.
Signed-off-by: Saurabh Jagdhane <saurabh.jagdhane@nxp.com>
Adding Reset and Write-protect pins initialization during AT45 driver
start-up. Usually these pins are driven high when not used.
The AT45 device incorporates an internal power-on reset circuit, so
there is no initial on-off reset sequence.
Signed-off-by: Eug Krashtan <eug.krashtan@gmail.com>
To keep compatibility between the old GPIO API implementation and a new
one introduced in the Zephyr 2.2.0 release the gpio_pin_configure()
function was accepting interrupt flags. In the new API implementation
interrupt flags are only accepted by gpio_pin_interrupt_configure()
function.
This temporary support for INT flags in gpio_pin_configure should have
been removed in the Zephyr 2.4.0 release.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
The shared interrupt controller depended on interrupt-cell sense
to inialize the interrupt using IRQ_CONNECT.
Forward the "sense" property only conditionally to be able to
use the driver all drivers that don't define it.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The size of the array holding the client information is determined
from the number of dt supports dep ordinals.
Finally remove the Kconfig symbol for the number of clients.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The intc_shared driver used kconfig to set the number of clients.
This commit changes the driver to determine the number of clients
per instance using supports ordinals information from device tree.
Leave the kconfig symbol for the number of clients, it now only defines
the array size in driver data and therefore an upper limit of how
many clients can be defined in dts.
It will be removed later with changes of driver data struct.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The intc_shared driver until now had the possibility to enable
up to two instances of the driver using the symbols SHARED_IRQ_0
and SHARED_IRQ_1.
This commit removes those Config options, and instead instantiates the
driver using DT_INST_FOREACH_STATUS_OKAY macro.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Implementation of the Bosch M_CAN IP driver.
This driver is just the base for a specific SoC implementation.
Signed-off-by: Alexander Wachter <alexander@wachter.cloud>
