Introduce a streaming API that uses the same data path as the async API.
This includes features to the decoder:
* Checking if triggers are present
Adding streaming features built ontop of existing triggers:
* Adding 3 operations to be done on a trigger
* include - include the data with the trigger information
* nop - do nothing
* drop - drop the data (flush)
* Add a new sensor_stream() API to mirror sensor_read() but add an
optional handler to be able to cancel the stream.
Signed-off-by: Yuval Peress <peress@google.com>
topic#sensor_stream
Convert the ITE keyboard scanning driver from kscan to input, add the
corresponding kscan compatibility node to the current board, build test
only.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Use GPIO_OUTPUT_INACTIVE to initialize the pin so that the ACTIVE_LOW DT
flag is honored and use the gpio_pin_set_dt functions to set the
(logical) value of the pin instead of gpio_pin_configure_dt, that
tries to reconfigure the pin each time.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Initialize the MDIO peripheral clock (normally done during GMAC
initialization) before trying any MDIO transfers, preventing startup
errors.
Signed-off-by: Nick Kraus <nick@nckraus.com>
We need to do a build assert for the fifo enable status of 'I2C2'.
There is a problem with using instance to obtain property when
any one I2C port is not enabled.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit enables clock control on the i.MX8QM and QXP boards.
This is achieved through the following changes:
1) The "reg" property is no longer marked as required
for the "nxp,imx-ccm" binding. This is necessary because
in the case of i.MX8QM and i.MX8QXP the clock management
is done through the SCFW, hence there's no need to access
CCM's MMIO space (not that you could anyways).
2) The DTS now contains a scu_mu node. This node refers
to the MU instance used by the DSP to communicate with
the SCFW.
3) The CCM driver needs to support the LPUART clocks
(which will be the only IP that's supported for now)
and needs to perform an initialization so that the
NXP HAL driver knows which MU to use to communicate
with the SCFW.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Use arch-specific sys IO APIs to access the memory-mapped
registers to ensure safe memory operations
fixes#62956
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Added some defines and helper functions to help with the
arithmetics so that the bit shifts and stuff do not look like
magic number.
Converted manual bit shift/set/unset to use macros provided by
Zephyr.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Most of the public APIs in `riscv_plic.h`
(except `riscv_plic_get_irq` & `riscv_plic_get_dev`) expect the
`irq` argument to be in Zephyr-encoded format, instead of the
previously `irq_from_level_2`-stripped version. The first level
IRQ is needed by `intc_plic` to differentiate between the
parent interrupt controllers, so that correct ISR offset can be
obtained using the LUT in `sw_isr_common`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Use a config struct to store per-instance device config during
init and connect the IRQ based on the devicetree instead of
hardcoded value and instance number.
The `get_plic_dev_from_irq` is still a placeholder for now and
always return the first instance.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Many (or almost all) drivers contain the specified prefixes
related to the driver subsys so add the missing one for the
BQ24190.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
This patch set provides support for T1S ethernet device - LAN8651.
For SPI communication the implementation of Open Alliance TC6
specification is used.
The driver implementation focuses mostly on reducing memory footprint,
as the used SoC (STM32G491) for development has only 32 KiB RAM in total.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Those files provide generic functions to handle transmission between chip
conforming OA TC6 standard and Zephyr's network stack represented by
struct net_pkt.
The communication is performed via SPI and is focused on reduced memory
footprint (works with SOC equipped with 32 KiB of RAM) and robustness of
operation.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
NXP USB bindings were combined into one binding and using
a property corresponding to HAL enums which is improper use
of devicetree.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
ep_ctrl and ep_trans_type is not used inside it82xx2_usb_dc_isr, this
triggers a compile warning. Move these variables to a smaller scope.
Signed-off-by: Ting Shen <phoenixshen@google.com>
Add drivers for gpio_i2c_switch which is present in beagleconnect freedom
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
Signed-off-by: Ayush Singh <ayushdevel1325@gmail.com>
The load switch / LDO pin configuration function now
correctly configures the associated GPIO pin.
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
When using console debug server hooks, not all characters are
processed if the server hook returns non-zero for one character
while there are other characters in the buffer. This is seen
when using a fast console (like USB) where multiple characters
come in before the ISR is called. Fix it by continuing to
process characters instead of returning from the ISR with
characters still in the buffer.
Fixes: #64661
Signed-off-by: Mariano Goluboff <mariano.goluboff@nordicsemi.no>
Some NXP S32 shim drivers are using macros defined in
soc/arm/nxp_s32/*/soc.h but not including soc.h. Those still
can be built because the header file is included indirectly
by some other header files. This is very fragile, it should
be included directly
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Remove the depenency on TF-M so that this driver can be used when PSA
is provided by something else than TF-M.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
user dma config is not fully saved in dma_sedi_chan_config
function. When dma_sedi_start function it will check local
context, it will cause failure here.
Signed-off-by: Ning Yang <ning.yang@intel.com>
This CL is to minimize `CONFIG_SOC_SERIES_XXXX` definitions when we
introduce a new chip series. Most of them are relevant to register
layouts in different npcx soc series. It moves soc-specific register
definitions from `reg_def.h` to its own soc.h file.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Add basic support for ams TSL2561 light sensor. Triggers, attributes
and manual integration time are currently not supported.
Signed-off-by: Gustavo Silva <gustavograzs@gmail.com>
Both the BQ27421 and BQ27427 have a few preset Chemistry profiles.
For the BQ27421 there exists three variants of the IC, and for the BQ27427,
it can be configured. The chemistry profile among other things includes the
taper voltage, which is used to detect charge termination.
This adds an optional `chemistry-id` config option to the driver. On the
BQ27421, it will confirm that the correct variant of the IC is mounted,
and on the BQ27427, it will configure it with the correct value.
Side note: The reference manual for the BQ27427
(https://www.ti.com/lit/ug/sluucd5/sluucd5.pdf) currently contains some
errors and inconsistencies regarding these registers. The table on page 7
appears to be correct.
Signed-off-by: Tobias Pisani <topisani@hamsterpoison.com>
Implement RTC support in counter driver for STM32WBA devices.
Changes are made according to the following specificities:
- Similarly to STM32U5, it is not connected to EXTI.
- On this series, there is no bit in BCDR register to enable RTC. Enabling
RTC is done directly via the RCC APB register bit
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Enables setting the initialization priority of the nPM1300 independently
from other MFDs.
Signed-off-by: Bernt Johan Damslora <Bernt.Damslora@nordicsemi.no>
Enables setting the initialization priority of the nPM6001 independently
from other MFDs.
Signed-off-by: Bernt Johan Damslora <Bernt.Damslora@nordicsemi.no>
Added initial version of Infineon AIROC WIFI driver
Added initial version of binding file for Infineon AIROC WIFI
driver
Rename CONFIG_ABSTRACTION_RTOS_COMPONENT_ZEPHYR to
CONFIG_USE_INFINEON_ABSTRACTION_RTOS
Exclude cy8cproto_062_4343w platform from
drivers.modem.esp_at.build test
Change revision hal_infineon to
69c883d3bd9fac8a18dd8384624b8c472a68d06f
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Added initial version of Infineon CAT1 SDHC/SDIO driver
Added initial version of binding file for Infineon CAT1 SDHC/SDIO
driver
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
With CSL enabled, when nrf5_stop is called,
nrf_802154_sleep_if_idle() will be called, and if the radio is
busy with another task, another IEEE802154_EVENT_RX_OFF event
will be pended right away, resulting in another call
to nrf5_stop(), effectively busy waiting until the
radio has reached idle.
In simulation, this whole operation (busy wait loop) is
done without letting the CPU sleep, in an infinite loop,
and therefore without letting any time pass
(note that in the POSIX architecture,
no time passes if the CPU does not go to sleep).
And therefore the radio will never be done with whatever
it is doing, resulting in the simulation being stuck
in this loop.
Let's add a very minor delay to this loop, which is
conditionally compiled only for the POSIX architecture.
Which effectively mimics the time it takes for the CPU
to loop thru, let's time pass, and allows the radio
to eventually be done.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
MDIO is currently initialized in the ETH NXP S32 NETC
driver for Physical Station Interface (PSI), so do not
try to build the MDIO driver if the ETH driver is not built
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
There is no require to prevent building nxp s32 netc
shim driver if NET_TEST is set, so just remove this
unnecessary dependency
Fix#64944
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Add a property for I2C channel switch selection. This property will
write to the SMBxxCHS register according to the I2C node you selected,
which can make channel swapping.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
