Nordic's nPM10 Series PMIC watchdog driver implementation and devicetree
bindings.
Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
atcwdt200 already supports the CONFIG_WDT_DISABLE_AT_BOOT feature.
However, HAS_WDT_DISABLE_AT_BOOT was not enabled in the driver config layer
at that time.
This PR fixes that issue.
Signed-off-by: Kevin Wang <kevinwang821020@google.com>
Use the Clock controller to get the frequency of the WDT clock instead
of hand roling with some defines owned/intendet for the clock
controller.
Signed-off-by: Fiona Behrens <me@kloenk.dev>
Add System Clock Controller for the M480 nuvoton MCU.
This only adds the base driver to setup HIRC, HXT, LIRC, LXT and
PLL. Configuring the PLL driver from a target frequency with
calculating values to best match this frequency.
Signed-off-by: Fiona Behrens <me@kloenk.dev>
TI MSPM0 has a WWDT module to initiate a reset when correct operation of
the device has failed due to an unexpected software or system delay.
Signed-off-by: Sanjay Vallimanalan <sanjay@linumiz.com>
Signed-off-by: Jackson Farley <j-farley@ti.com>
The EFM32HG (Series 0) WDOG has no IRQ support, no window mode
and no reset-disable bit.
Guard the logic with HAL feature macros and use `IF_ENABLED` with
`DT_INST_IRQ_HAS_IDX` for conditional IRQ setup.
Add the `wdog0` node to the EFM32HG device tree.
Signed-off-by: Patryk Koscik <pkoscik@antmicro.com>
- Initial implementation for the numaker watchdog timer peripheral.
- Add binding to the m48x series soc.
Signed-off-by: Scott Laboe <scottyl2.718@gmail.com>
If DT has IRQ defined, the board supports NMI mode, if reset-capable
property is set then the board can support reset as well. Based
on these DT properties and the flags passed by the application,
NMI mode or Reset mode can be set.
Signed-off-by: Sunil Hegde <s-hegde3@ti.com>
Allow WWDT callbacks without warning configuration when
WDT_FLAG_RESET_NONE is selected.
This restores callback-at-expiry behavior for reset-none
flows while keeping reset-enabled modes on the guarded
warning-interrupt path.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
STM32WB0 watchdog does not support disable the Debug
module during STANDBY mode once the DBGMCU
clock is enabled.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
`tests/drivers/watchdog/wdt_error_cases` test was failing
on `it51xxx_evb/it51526aw` due to insufficient error
handling. This change fixes those issues, and the following
tests now pass.
- tests/drivers/watchdog/wdt_error_cases
- tests/drivers/watchdog/wdt_basic_api
- tests/drivers/watchdog/wdt_basic_reset_none
- tests/drivers/watchdog/wdt_variables
- samples/drivers/watchdog
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within:
- `drivers/w1`
- `drivers/watchdog`
- `drivers/wifi`
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Update the MCUX WWDT driver to partially use the Zephyr clock control API
instead of direct HAL clock APIs for clock on and get rate.
Keep using HAL clock APIs for set clock divider because the set rate API
accepts clock frequency and it may cause two external calls to get WWDT
frequency.
Support multiple instances.
Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
Update the MCUX i.MX WDOG driver to support multiple device instances
instead of being hardcoded to instance 0.
Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
Update the MCUX WDOG32 driver to support multiple device instances
instead of being hardcoded to instance 0.
Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
Add WWDG support for STM32C5. Replace the IS_WWDG_COUNTER macro (that
doesn't exist in the STM32C5 LL) by the IN_RANGE macro.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add the *_FreezePeriph function for STM32C5. While at it, fix the driver
for C0/F0/G0/L0 by calling the *_FreezePeriph function once the DBGMCU
clock is enabled (a #endif was missing). It is done the same
way for WWDG driver.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Some macros used in the IWDG driver are no longer present in HAL2. Replace
them by doing the same operation directly.
Also make some clean up/cosmetic changes.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Following the convention of other driver libraries, allow the library
to be empty, so there is no build warning if CONFIG_WATCHDOG is
enabled, but no driver is selected.
<!-- ps-id: 2581e043-e366-4115-b6d2-73ca070add8b -->
Signed-off-by: James Walmsley <james@fullfat-fs.co.uk>
Add support for the CONFIG_WDT_DISABLE_AT_BOOT Kconfig option.
If the watchdog timer is enabled by default on the target board,
enabling this option will explicitly disable the watchdog during
the driver initialization phase.
Signed-off-by: Kevin Wang <kevinwang821020@google.com>
Fix broken FS26 watchdog field extraction and refresh checks.
Correct the device status macro, simple watchdog write error
handling, related register field helper macros, and use integer
duty-cycle values when selecting the watchdog window.
Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
Removed the options variable on wdt_cc13xx_cc26xx_init
which was only initialized to zero and not used.
Signed-off-by: Jean-Pierre De Jesus DIAZ <me@jeandudey.tech>
Add software state check (!data->wdt_started) to wdt_feed() validation
to ensure feed operations are only allowed after wdt_setup() has been
called.
Signed-off-by: Harini T <harini.t@amd.com>
On CY_IP_S8SRSSLT devices (PSOC 4), the WDT match register is 16-bit.
When Cy_SysClk_IloCompensate returns a compensated count that exceeds
UINT16_MAX (e.g. for a ~2000ms timeout at ~32768 Hz), passing it to
Cy_WDT_SetMatch triggers a HAL assertion that causes a HardFault on
Cortex-M0+.
Clamp ilo_compensated_counts to UINT16_MAX in the setup path, matching
the existing clamp in the feed path (ifx_wdt_timeout_to_match).
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Add a watchdog timer driver for all Bouffalo Lab SoC families.
Tested on Sipeed M0Sense (BL702) with tests/drivers/watchdog/wdt_basic_api.
Signed-off-by: William Markezana <william.markezana@gmail.com>
The WWDG timeout check used a signed comparison between the requested
and computed timeout, causing valid configurations to be rejected when
the computed timeout was slightly lower than the requested one.
Replace the comparison by an absolute‑difference check so that the
configured timeout is accepted as long as it stays within the allowed
error margin.
This fixes spurious -EINVAL returned by install_timeout() on STM32.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
If the clock device (i.e., RCC) failed to initialize, we have bigger
problems than trying to call clock_control_{off,on,configure} on it.
Don't bother checking to save some footprint.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
There are many drivers which control a disabled-by-default watchdog timer
but take the liberty of selecting HAS_WDT_DISABLE_AT_BOOT and interpreting
WDT_DISABLE_AT_BOOT=n as "enable the timer", which does not correspond to
the semantics of this option.
Update all such drivers to no longer select HAS_WDT_DISABLE_AT_BOOT and
ignore the WDT_DISABLE_AT_BOOT option.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
WDT_DISABLE_AT_BOOT should only be used to forcefully disable watchdog
timers that are enabled by default after system reset. Update the Kconfig
help text of WDT_DISABLE_AT_BOOT and its dependency HAS_WDT_DISABLE_AT_BOOT
to make this clear.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
1. enable watchdog support
2. verified tests/drivers/watchdog/wdt_basic_api
Signed-off-by: Peter Wang <chaoyi.wang@nxp.com>
Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
Add MAX42500 watchdog driver, including ability to configure voltage
monitors that can also generate reset conditions.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Under RTIO SPI behaves differently and thus FS26 didn't work and
would reset the board. This changes to add 8-bit transfer support
and doesn't lock the irq anymore since the SPI driver got changed.
Which would yield an assertion, best it ensure feed callee priority
is high enough.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Add support for the Infineon PSoC4 family to the infineon watchdog driver.
PSoC4 specific ILO frequency and tick period definitions.
Initialization and configuration logic specific to PSoC4.
Signed-off-by: Dharun krithik k <dharunkrithik@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
In commit 1f9e39752a ("drivers: watchdog: wdog32: add delay before
init") a reference to k_msleep was added to
drivers/watchdog/wdt_mcux_wdog32.c without including the necessary
header. At least for the board frdm_mcxw71/mcxw716c, this causes a
compile failure in this file as soon as CONFIG_WATCHDOG is enabled.
Add the missing include to zephyr/kernel.h to fix the issue.
Signed-off-by: Matthias Blankertz <matthias.blankertz@inovex.de>
Add support for named clocks in the WDOG32 driver to properly handle
different clock sources. The driver now uses clock-names property to
identify which clock source is being used, based on the clk-source
property.
This change enables proper clock configuration and control for platforms
where the clock frequency is not statically defined in the device tree.
The driver will now configure and enable the appropriate clock during
initialization.
Updated all affected device tree files to include the clock-names
property aligned with their clk-source configuration.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
nxp_ewm_install_timeout() accesses cfg fields before checking for
NULL, making the later NULL check ineffective.
Remove the redundant check.
Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
