The global otg interrupt hs/fs is enabled by the udc_stm32
driver. Get it in the list of interrupts of the OTG node.
Use UDC_STM32_IRQ naming.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Seems like not all stm32 devices define USBD_HS_SPEED in the HAL, only
check for USBD_HS_SPEED if defined. Fixes a build failure with the new
stack on F1 MCUs.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
A function, such as CDC ECM, can set the ZLP flag to handle a
class-specific protocol. This is not to be confused with the ZLP role in
control transfers.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add support for GPIO controlled disconnect pullups. This is used in F1
based devices, copied from the legacy driver.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
- If the peripheral is OTG_HS with ULPI, enable the OTG_HS ULPI clock
- The constant has a slightly different name on stm32h7
- Otherwise, if the peripheral is OTG_HS:
- Disable the OTG_HS ULPI clock in sleep/low power mode,
- If the peripheral is OTG_HS with PHYC[1], enable the PHYC clock.
- Otherwise, if the peripheral is OTG_FS[2] on stm32h7, also disable the
OTG_FS ULPI clock in sleep mode (in the device/ driver, this is done in
usb_dc_stm32_init()),
[1]: Internal HS PHY in stm32f7x2xx and (some) stm32f730xx
[2]: "OTG_FS" on stm32h7 is really just another OTG_HS peripheral, but
without any way to actually connect a HS PHY
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Mass Storage enumeration failed because udc_stm32_ep_mem_config() was only
increasing priv->occupied_mem on endpoint enable, and not decreasing it on
endpoint disable. Fix the issue by decreasing priv->occupied_mem
on endpoint disable.
Signed-off-by: Arne Bohnsack <arne.bohnsack@draeger.com>
When running the cdc_acm demo on a board with an external ULPI
phy, the device is unable to enumerate:
usb 1-1.8.3.1: new full-speed USB device number 51 using ehci-pci
usb 1-1.8.3.1: device descriptor read/64, error -32
usb 1-1.8.3.1: device descriptor read/64, error -32
the console shows:
[00:00:00.001,000] cdc_acm_echo: Wait for DTR
[00:00:00.007,000] usb_cdc_acm: Device suspended
[00:00:00.902,000] usb_cdc_acm: Device resumed
[00:00:00.902,000] usb_cdc_acm: from suspend
[00:00:25.526,000] usb_cdc_acm: Device suspended
By not disabling the ULPI clock in low power, the usb enumeration
is working and we can run the cdc_acm demo. While touching
this code, add some comments to clarify the macro nesting.
Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
Like the stm32H5, stm32u5 usb device has an independent
power supply, but control bit is PWR_SVMCR_USV.
The control bit for the stm32H5 is PWR_USBSCR_USB33SV (no change)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The stm32H5 mcu has an independent USB supply to be enabled
at init with LL_PWR_EnableVDDUSB function like the stm32U5 serie.
Both series have PWR_USBSCR_USB33SV bit in their USBSCR POWER reg.
and other series all have PWR_CR2_USV bit in their CR2 POWER reg.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add UDC driver for STM32 based MCU, relying on HAL/PCD.
This has been tested with cdc_acm sample on the following boards:
- 96b_carbon (STM32F4)
- disco_l475_iot1 (STM32L4)
- nucleo_wb55rg (STM32WB)
- nucleo_h723zg (STM32H7)
- stm32f3_disco (STM32F3)
This fails at runtime for the following:
- b_u585i_iot2a (STM32U5)
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
