... so that the pin is kept in a defined state when the IO3 line is
not controlled by the QSPI peripheral (when the peripheral is disabled
or disconnected from the pin).
The IO3 pin in Quad SPI flash chips usually has dual functionality -
it is an I/O line when the chip is configured to work in Quad (4 I/O)
mode and it is a HOLD# or RESET# line when the chip is configured to
work in non-Quad (2 I/O) mode. In the latter case, it is important that
the line is kept in the inactive (high) state, otherwise communication
with the chip may be disrupted (and this actually happens when e.g.
the spi_flash sample is used on a brand new nRF5340 or nRF52840 DK -
the nrf_qspi_nor driver fails to initialize and the sample just ends
up with the "mx25r6435f@0: device not ready" message).
This commit addresses the problem in the same way that it was done for
the CSN line in commit 6d8172f4e9.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
For certain peripheral signal lines in nRF54H20, it is required
to set the clockpin bitfield for pins assigned to them, otherwise
the peripheral may not work properly, for example, there will be
no output from UART.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
With the introduction of nrfx 3.0.0, values of `nrf_gpio_pin_drive_t`
constants may be defined differently, depending on the SoC family.
Since the nrf-pinctrl.h file is included also from dts files, it is
not possible to use there different definitions of `NRF_GPIO_PIN_*`
values based on Kconfig symbols that indicate given SoC family (as
Kconfig is processed after devicetree) so that those values could
still match `nrf_gpio_pin_drive_t` constants.
To solve this problem, the pinctrl_nrf driver now uses a lookup table
for mapping `NRF_GPIO_PIN_*` indexes to drive configuration values
required by the GPIO HAL.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This is a follow-up to commit 223cc3c6bd.
When a peripheral pin is disconnected, the pinctrl driver should skip
applying of GPIO configuration, as there is no pin number available in
such case, but due to an incorrect check, it actually did not skip it
and used an incorrect pin number for that. In nrfx prior to 3.0.0, this
caused an assertion failure, but because of a fallback routine, things
could still work in most cases (when assertions were disabled) as that
GPIO configuration was just applied to P0.31. Hence the bug was not
discovered until now. In the recent nrfx, this causes a null pointer
dereference, so always a crash.
This commit corrects the mentioned check and also uses the term "psel"
instead of "pin" where it is possible that the value is not a correct
pin number, in the hope of preventing a similar problem in the future.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
... so that the pin keeps the inactive state of the CSN line when it is
not controlled by the QSPI peripheral and the driver is not suspended.
Currently, the nrf_qspi_nor shim deinitializes the nrfx_qspi driver
after each operation, what leaves the pin uncontrolled until a new
operation is requested (and the nrfx_qspi driver is initialized again)
or the driver is suspended (and the pin is put into low-power state).
This can cause the flash chip to needlessly consume current when there
is no pull-up resistor on its CSN line and the line appears active.
Prevent this by keeping the pin in a defined (inactive) state.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
It was not possible to disconnect a pin using the nRF pinctrl driver.
That is, it was not possible to set PSEL to 0xFFFFFFFF (indicating pin
is not connected). This can be useful in certain scenarios, e.g. a
bootloader configures all signals of a certain peripheral but
application then needs to disconnect certain signals.
A new DT macro has been introduced to accomplish this:
NRF_PSEL_DISCONNECT. It can be used like this to explicitely disconnect
a peripheral signal:
```
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 1)>,
<NRF_PSEL_DISCONNECTED(UART_RX)>;
};
};
};
```
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This is a follow-up to commit fd07675574.
The above commit was supposed to introduce overriding of the S0S1
drive setting with S0D1 for TWI/TWIM peripherals, but since it did
not properly update the `nrf_pin_configure()` function (the `drive`
parameter was only added in the function signature, but then it was
not used...), the drive setting was in fact not overridden.
This commit corrects this embarrassing oversight.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The default S0S1 drive setting is not suitable for TWI/TWIM pins.
Override it with S0D1 as for some SoCs (e.g. nRF52833) without
this the peripheral will not work properly.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This is a follow-up to commit fd7633126e.
For some reason the above commit added several switch cases without
required break statements. In effect, the same pin could get assigned
to multiple signal lines in QDEC or QSPI peripherals if not all pins
were defined for them in devicetree, and consequently these peripherals
could not work properly.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The NRF_TWI_Type struct doesn't have an homogeneous layout between
nRF51/52 series. This patch tries to select the right layout based on
selected SoC.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add support for configuring pins to be used by the nRF PWM, QDEC, and
QSPI peripherals.
A new custom property "nordic,invert" is added to the pin configuration
group binding to allow configuring PWM channel outputs as inverted.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the SPI drivers that handle
the nRF SPI, SPIM, and SPIS peripherals. Update code of the drivers
and related devicetree bindings.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for configuring pins of the following nRF peripherals:
SPI, SPIM, SPIS, TWI, and TWIM.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for configuring UART/UARTE peripheral pins.
Co-authored-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add initial support for nRF pin controller driver. The implementation in
this patch does not yet support any peripheral. Only states
representation and basic driver functionality is introduced.
Note:
The nrf_pin_configure function has been marked as __unused since it may
not be used in certain scenarios until all peripherals are supported by
the pinctrl driver. For example, if only UART/E is supported but the
board does not enable UART, the function will never get called. However,
that board will likely have other peripherals that will gain support in
the future.
Thanks to Marti Bolivar for bindings documentation.
Co-authored-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
