Commit graph

15 commits

Author SHA1 Message Date
Jérôme Pouiller
1d4a0d78e3 drivers: memc: Add support for siwx91x QSPI controller
Silabs siwx91x includes a memory controller for (Quad-)SPI PSRAM. It
allows the application to use the PSRAM as if it was any other RAM.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
2025-05-15 09:00:39 +02:00
Jérôme Pouiller
91e3f78837 drivers: memc: Sort inclusions
These are only cosmetics changes to prepare integration of the further
patches.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
2025-05-15 09:00:39 +02:00
Pete Johanson
f4b52a43d9 drivers: memc: Add MAX32 HyperBus driver
Add memc driver for the MAX32 HyperBus peripheral, supporting HyperRAM
and Xccela PSRAM memory devices.

Signed-off-by: Pete Johanson <pete.johanson@analog.com>
2025-05-02 15:20:55 +02:00
The Nguyen
ee04db8b4d drivers: memc: enable support for SDRAM controller on Renesas RA family
First commit to add support for SDRAM controller on Renesas RA SoC

Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
2024-12-20 23:53:37 +02:00
Ioannis Karachalios
7c5c459440 drivers: memc: Fix various APS6404 device issues
This commit deals with fixing various issues that prevents
the device from being built. In specific:

1. Fix default timing macro definitions to build with
an MSPI controller, other than AMBIG.
Add macro definition for MSPI_PORT.
2. Timing settings should be applied only when MSPI_TIMING
is defined. Otherwise, the APS6404 initialization routine
will fail with -EIO.
3. Similarly, use MSPI_XIP and MSPI_SCRAMBLE to apply XIP
and SCRAMBLE device settings, respectively (optimization).
4. MEMC_INIT_PRIORITY is assigned higher priority than
MSPI_INIT_PRIORITY which results in compiler error as
APS6404 device initialization depends on its underlying
MSPI bus controller.
5. The 'acquire' subroutine should be compiled when PM_DEVICE
is used (suppress compiler warning).

Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
2024-11-08 13:56:31 -06:00
Declan Snyder
57d777b640 drivers: flash/memc: Source logging kconfig last
Some flash/memc drivers like flexspi will want to default the
value of the log level to off to avoid RWW hazard while XIP,
to do this, the logging template must be sourced after the driver
kconfig files so that the default value from the driver is able
to be checked, since logging template introduces an unconditional
default otherwise.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-08-22 09:14:24 +02:00
Swift Tian
c7ed0b6aa8 drivers: memc: Add APS6404L device driver
The APS6404L psram is a quad SDR SPI device that runs up to 100MHz.
It can provide 8MB of external RAM for SoCs that supports XIP feature.
The device driver uses MSPI bus API and could be used across
different controllers that implement the MSPI bus API.

Signed-off-by: Swift Tian <swift.tian@ambiq.com>
2024-06-14 21:07:00 -04:00
Ioannis Karachalios
02e739873e drivers: memc: smartbond: Add support for the memory driver class.
Add support for the memory controller by utilizing QSPIC2. The latter is
capable to drive both NOR and PSRAM memory devices. For this to work,
the RAM driving mode is enabled.

Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
2024-05-23 07:51:41 -04:00
Manuel Argüelles
5dad944351 drivers: memc: add NXP S32 QSPI controller
The NXP S32 QSPI controller acts as an interface to up to two serial
flash memory devices, each with up to eight bidirectional data lines,
depending on the platform. It is based on a LUT enginee to interface
through commands with different memory types including flash NOR and
Hyperram.

This patch adds support for the QSPI in S32K344 which supports a single
memory device (side A) with up to four bidirectional data lines and SDR
only. Nevertheless, the memory controller is implemented flexible enough
to be extended to support more feature-rich QSPI blocks.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-07-26 09:44:14 +02:00
Franciszek Zdobylak
71a6c22731 drivers: memc: implement sifive ddr mem controller
Implementation for DDR memory controller for FU740 SoC.

Signed-off-by: Franciszek Zdobylak <fzdobylak@antmicro.com>
2023-04-12 13:05:55 +02:00
Henrik Brix Andersen
c41dd36de2 drivers: kconfig: unify menuconfig title strings
Unify the drivers/*/Kconfig menuconfig title strings to the format
"<class> [(acronym)] [bus] drivers".

Including both the full name of the driver class and an acronym makes
menuconfig more user friendly as some of the acronyms are less well-known
than others. It also improves Kconfig search, both via menuconfig and via
the generated Kconfig documentation.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2023-03-28 15:06:06 +02:00
Pieter De Gendt
e328c2bb7d drivers: memc: Introduce Atmel SAM SMC/EBI driver
Add a driver to support external memory connected to the SMC port
for Atmel SAM devices.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2022-08-16 12:53:50 +02:00
Torsten Rasmussen
bd61122aa2 kconfig: drivers: experimental settings now uses select EXPERIMENTAL
With the introduction of `EXPERIMENTAL` and `WARN_EXPERIMENTAL` in
Zephyr all drivers settings having `[EXPERIMENTAL]` in their
prompt has has been updated to include `select EXPERIMENTAL` so that
developers can enable warnings when experimental features are enabled.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-10-25 10:46:48 +02:00
Pieter De Gendt
acca3c126c mcux flexspi: move bus driver to drivers/memc
Initially the flexspi device only supported a flash driver for
external NOR flash. As the controller supports HyperBus devices,
which can be either volatile or non-volatile, the driver iss moved
to drivers/memc.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2021-04-02 10:36:22 -05:00
Gerard Marull-Paretas
e671d363b8 drivers: memc: stm32: initial support for stm32 FMC
This commit adds a new driver category for memory controller
peripherals. There is no API involved for now, as it has not been found
necessary for first implementation.

STM32 Flexible Memory Controller (FMC) is the only controller supported
for now. This peripheral allows to access multiple types of external
memories, e.g. SDRAM, NAND, NOR Flash...

The initial implementation adds support for the SDRAM controller only.
The HAL API is used, so the implementation should be portable to other
STM32 series. It has only been tested on H7 series, so for now it can
only be enabled when working on H7.

Linker facilities have also been added in order to allow applications to
easily define a variable in SDRAM.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-11-24 16:33:17 +01:00