Silabs siwx91x includes a memory controller for (Quad-)SPI PSRAM. It
allows the application to use the PSRAM as if it was any other RAM.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Add memc driver for the MAX32 HyperBus peripheral, supporting HyperRAM
and Xccela PSRAM memory devices.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Flexram is really not a memory controller, and does not belong in memc
namespace or directory. Move it to it's own misc directory and remove
memc_ from the namespace.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The APS6404L psram is a quad SDR SPI device that runs up to 100MHz.
It can provide 8MB of external RAM for SoCs that supports XIP feature.
The device driver uses MSPI bus API and could be used across
different controllers that implement the MSPI bus API.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
Add support for the memory controller by utilizing QSPIC2. The latter is
capable to drive both NOR and PSRAM memory devices. For this to work,
the RAM driving mode is enabled.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Add driver for IS66WVQ8M4 PSRAM, using the MCUX FlexSPI interface to
write data to the PSRAM device.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The NXP S32 QSPI controller acts as an interface to up to two serial
flash memory devices, each with up to eight bidirectional data lines,
depending on the platform. It is based on a LUT enginee to interface
through commands with different memory types including flash NOR and
Hyperram.
This patch adds support for the QSPI in S32K344 which supports a single
memory device (side A) with up to four bidirectional data lines and SDR
only. Nevertheless, the memory controller is implemented flexible enough
to be extended to support more feature-rich QSPI blocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Update usage of zephyr_code_relocate to follow new API. The old method
of relocating a file was the following directive:
zephyr_code_relocate(file location)
The new API for zephyr_code_relocate uses the following directive:
zephyr_code_relocate(FILES file LOCATION location)
update in tree usage to follow this model. Also, update the NXP HAL SHA,
as NXP's HAL uses this macro as well.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce driver for APS6408L PSRAM, built on top of the MCUX memc
driver for flexSPI. This driver supports operating the PSRAM in high
speed mode (200MHz or more). Note that in order to support this
PSRAM's alignment requirements, either ahb-read-addr-opt or
ahb-prefetch must be set for the FlexSPI instance.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Rename flexspi-hyperram driver to flexspi-s27ks0641, and update
function names. This driver is only capable of supporting the
s27ks0641 HyperRAM chip, as the lookup table given in this driver
is specific to the s27ks0641.
Rename the flexspi-hyperram binding to reflect this, to
prevent confusion from users.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Only relocate memc driver when CONFIG_FLASH=y.
CONFIG_FLASH_MCUX_FLEXSPI_XIP previously was dependent on
CONFIG_FLASH, but the scope of this Kconfig has changed.
Due to this, the memc driver now must have two checks, as it should not
relocated when the driver is being used for a memory controller that does
not expose the flash driver interface.
Since the NXP HAL also relocates the underlying FlexSPI driver
using a similar check, it is updated in this commit as well.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Instead of putting object files inside libzephyr.a,
simply build a separate static library as most other
driver types are doing this already.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This change allows writing to the flash while running in XIP mode,
and enables mcuboot or NVS settings to be used on i.MX RT socs.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Initially the flexspi device only supported a flash driver for
external NOR flash. As the controller supports HyperBus devices,
which can be either volatile or non-volatile, the driver iss moved
to drivers/memc.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
This commit adds a new driver category for memory controller
peripherals. There is no API involved for now, as it has not been found
necessary for first implementation.
STM32 Flexible Memory Controller (FMC) is the only controller supported
for now. This peripheral allows to access multiple types of external
memories, e.g. SDRAM, NAND, NOR Flash...
The initial implementation adds support for the SDRAM controller only.
The HAL API is used, so the implementation should be portable to other
STM32 series. It has only been tested on H7 series, so for now it can
only be enabled when working on H7.
Linker facilities have also been added in order to allow applications to
easily define a variable in SDRAM.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
