Files including <zephyr/kernel.h> do not have to include
<zephyr/zephyr.h>, a shim to <zephyr/kernel.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Theoretically, source id check is not mandatory in the context we use
VT-D here (i.e. non VM one, just multi-vector MSI support)
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Not sure this is requered as we do not mangle with domains, but let's
make sure this cache is clear.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
A surprising issue: while sys_set_bit() on VTD_GCMD_REG work on
apollo_lake, it seems to create border effect on elkhart_lake: it may
reset some previous bit to 0.
So switching to full write of the register at once, which works for
both.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
QI operation are not supposed to last forever.
It's not an actual timeout based on clock, but a dummy counter instead.
That's because system clock might not have beed initialized yet, since
VT-D's init comes first (and that same init will use QI...)
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Depending on a VT-D capability, it might be necessary to flush objects
from the cache.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Looks like it's mandatory to invalidate the Interrupt Entry Cache in
VT-D and the only way to do so is to enable Queued Interface.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
IR faults are non-recoverable, so it's good to know why. Thus let's
handle the fault event and print the fault.
Other faults are printed as well.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Looks like a source of fault if pieces of IRTE are written instead of
the whole 64 bits block it belongs to.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Adding a way to pre-install the irg/vector on an irte and a way to get
an irte based on irq/vector.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This will not only be used by MSI remapping but by all relevant
interrupts.
Fix also IRTE settings:
- handle x2apic for destination id
- destination mode is always logical (as for IOAPIC)
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
In XAPIC mode, it's possible to tell VT-D to let interrupt in compatible
format passing through.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
SHV bit depends on the number of vectors allocated.
If it's facing a multi-vector MSI array, it will set the bit.
If not the bit must be 0.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Such interrupt remapping controller may be found along with Intel VT-D
hardware. Its base-address is via ACPI, and it enables up to 64K
interrupt indexes.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
